JPH08204151A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor memory device and a manufacturing method thereof in which a thick silicon oxide film can be formed only on a pad polycrystalline silicon film by a simple process. [Structure] Polycrystalline silicon film 9 on N-type impurity diffusion layer 5
Is introduced into the polycrystalline silicon film 9 on the N-type impurity diffusion layer 6, and phosphorus is introduced into the polycrystalline silicon film 9 on the N-type impurity diffusion layer 6 so as to cover the N-type impurity diffusion layer 5 and also contain arsenic.
And the lower electrode 15 of the capacitor containing phosphorus while covering the N-type impurity diffusion layer 6. Then, a silicon nitride film is formed on the pad polycrystalline silicon film 14 and the lower electrode 15 of the capacitor, and then thermal oxidation is performed to form the silicon oxide film 1 on the pad polycrystalline silicon film 14.
6'is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a manufacturing method thereof, and is particularly suitable for application to a DRAM (Dynamic Random Access Memory) having a stack type memory cell structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art In the case of forming a contact with a metal wiring on a silicon substrate, a pad polycrystalline silicon film is formed on the silicon substrate and a contact is made with the metal wiring through the pad polycrystalline silicon film. Further, it is possible to suppress leakage current and stably form a low resistance contact. When this manufacturing method is applied to a stack type DRAM to make contact with a bit line through a pad polycrystalline silicon film, the pad polycrystalline silicon film and the lower electrode of the capacitor are deposited on a silicon substrate. It is possible to form the same polycrystalline silicon film formed by patterning.

That is, the conventional stack type DRAM is
After forming a gate electrode on a silicon substrate via a gate insulating film, depositing a polycrystalline silicon film and patterning the polycrystalline silicon film, a contact is made on one of the impurity diffusion layers on both sides of the gate electrode. A pad polycrystalline silicon film for forming a lower electrode of the capacitor is formed on the other. Then, a cell plate electrode is formed on the pad polycrystalline silicon film and on the lower electrode of the capacitor through a capacitance insulating film, and a contact is made between the bit line formed on the cell plate electrode and the pad polycrystalline silicon film. The opening is formed in the cell plate electrode.
Then, an interlayer insulating film is formed on the cell plate electrode, a bit contact is formed by opening the capacitor insulating film and the interlayer insulating film, and then a bit line is formed on the interlayer insulating film to form a pad polycrystalline silicon film. Make contact with. With this manufacturing method, stable contacts can be formed without increasing the number of depositions of the polycrystalline silicon film.

[0004]

However, according to the conventional manufacturing method described above, when the cell plate electrode is selectively etched to form the opening, a thin capacitor is formed as an etching stopper on the pad polycrystalline silicon film. There is a problem that only the insulating film is present and the pad polycrystalline silicon film is also etched. Therefore, an etching protection film such as a thick silicon oxide film is formed on the pad polycrystalline silicon film in advance, but this method involves an increase in many steps such as deposition and patterning of the protection film. Therefore, the manufacturing yield and the throughput are deteriorated, and the silicon oxide film is deposited and removed on the silicon nitride film forming the capacitor insulating film, which causes a new problem that the insulating property of the capacitor insulating film is easily deteriorated. .

Therefore, an object of the present invention is to provide a semiconductor memory device capable of forming a thick silicon oxide film only on a pad polycrystalline silicon film by a simple process, and a manufacturing method thereof.

[0006]

In order to solve the above problems, according to the method of manufacturing a semiconductor memory device of claim 1, a gate electrode is formed on a first conductivity type semiconductor substrate via a gate insulating film. And a step of forming a pair of second conductivity type impurity diffusion layers separated by the gate electrode, a step of forming a polycrystalline silicon film on the second conductivity type impurity diffusion layer, and the polycrystalline silicon. A step of selectively introducing phosphorus into the film and selectively introducing arsenic into the polycrystalline silicon film, and patterning the polycrystalline silicon film to cover one of the second conductivity type impurity diffusion layers. And a step of forming a first polycrystalline silicon film containing phosphorus and a second polycrystalline silicon film containing arsenic while covering the other of the second conductivity type impurity diffusion layers, and the first polycrystalline silicon film. Forming a capacitive insulating film having oxidation resistance on the crystalline silicon film and the second polycrystalline silicon film, and forming a silicon oxide film on the surface of the second polycrystalline silicon film by thermal oxidation Forming a cell plate electrode on the capacitance insulating film; forming an opening in the cell plate electrode by selectively etching the cell plate electrode on the silicon oxide film; Forming an interlayer insulating film on the plate electrode; forming a bit contact by selectively etching the silicon oxide film and the interlayer insulating film through the opening; and the second contact through the bit contact. Forming a bit line connected to the polycrystalline silicon film on the interlayer insulating film.

According to another aspect of the semiconductor memory device of the present invention, a gate electrode formed on the first conductivity type semiconductor substrate via a gate insulating film, and a pair of second conductivity type separated by the gate electrode. It is formed on one of the impurity diffusion layer and the second conductivity type impurity diffusion layer, and is also formed on the other of the first polycrystalline silicon film containing the first impurity and the second conductivity type impurity diffusion layer. At the same time, a second polycrystalline silicon film containing a second impurity that reduces the oxidation resistance,
A silicon oxide film formed on the second polycrystalline silicon film and a capacitor insulating film having oxidation resistance on the first polycrystalline silicon film are formed on the silicon oxide film. A cell plate electrode having an opening and a conductive layer formed on the cell plate electrode and connected to the second polycrystalline silicon film through the opening.

According to another aspect of the semiconductor memory device of the present invention, the first impurity is phosphorus and the second impurity is arsenic.

[0009]

According to the present invention, the first impurity is introduced into the first polycrystalline silicon film which will be the lower electrode of the capacitor, and the second polycrystalline silicon film which will be the contact pad polycrystalline silicon film will be resistant to oxidation. After introducing the second impurity that deteriorates the property, a capacitive insulating film having oxidation resistance is formed on the first polycrystalline silicon film and the second polycrystalline silicon film, and thermal oxidation is performed. At this time, the first polycrystalline silicon film is not oxidized due to the oxidation resistance of the capacitive insulating film, but the second polycrystalline silicon film is oxidized due to the deterioration of the oxidation resistance of the capacitive insulating film formed thereon. To be done. Therefore, a thick silicon oxide film can be formed only on the pad polycrystalline silicon film which is contacted by a simple process.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings. 1 to 3 are sectional views showing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention in the order of steps.

First, as shown in FIG. 1A, a device isolation film 2 is formed on a P-type semiconductor substrate 1 by a selective oxidation method to a thickness of 500 nm.
After being formed to a thickness of about 20 nm, the gate insulating film 3 is deposited to a thickness of about 20 nm by a vapor phase growth method. Then, a gate electrode 4 is formed by depositing a polycrystalline silicon film containing impurities such as phosphorus at a high concentration to a thickness of about 150 nm by vapor phase epitaxy and patterning it by photolithography and etching techniques. Then, N-type impurity diffusion layers 5 and 6 are formed by ion-implanting impurities such as phosphorus and arsenic using the element isolation film 2 and the gate electrode 4 as a mask, and the N-type impurity diffusion layers 5 and 6 are formed on the gate electrode 4 by vapor phase epitaxy. The first interlayer insulating film 7 is deposited to a thickness of about 100 nm. Here, the element isolation film 2, the gate insulating film 3, and the first interlayer insulating film 7 are made of a silicon oxide film, a silicon nitride film, a laminated film of a silicon oxide film and a silicon nitride film, or the like. Further, the gate insulating film 3 may be formed by thermal oxidation.

Next, as shown in FIG. 1B, the first interlayer insulating film 7 on the N-type impurity diffusion layers 5 and 6 is selectively removed by patterning by photolithography and etching technique. An opening is formed on the N-type impurity diffusion layer 5 and a storage contact 8 is formed on the N-type impurity diffusion layer 6. Then, a polycrystalline silicon film 9 is deposited by a vapor phase epitaxy method, and ion implantation 11 is performed using the patterned photoresist 10 as a mask, so that arsenic is added to the polycrystalline silicon film 9 on the N-type impurity diffusion layer 5. Introduce.

Next, as shown in FIG. 2A, after the photoresist 10 is removed, ion implantation 13 is performed using the patterned photoresist 12 as a mask so that the N-type impurity diffusion layer 6 is formed. Phosphorus is introduced into the polycrystalline silicon film 9.

Next, as shown in FIG. 2B, the photoresist 12 is removed, and then the polycrystalline silicon film 9 is patterned to cover the N-type impurity diffusion layer 5 and to add pads containing arsenic. A crystalline silicon film 14 and a lower electrode 15 of a capacitor containing phosphorus and covering the N-type impurity diffusion layer 6 are formed. Then, a silicon nitride film having a thickness of about 60 Å is formed on the pad polycrystalline silicon film 14 and the lower electrode 15 of the capacitor by the vapor phase growth method, and then thermal oxidation is performed at a temperature of 900 ° C.

At this time, since the pad polycrystalline silicon film 14 contains arsenic, the oxidation resistance of the silicon nitride film formed on the pad polycrystalline silicon film 14 is lowered, the silicon nitride film is oxidized and the pad polycrystalline film is oxidized. The silicon film 14 is also oxidized to form a silicon oxide film 16 'having a thickness of about 140Å on the pad polycrystalline silicon film 14. On the other hand, since the lower electrode 15 contains phosphorus and does not affect the oxidation resistance of the silicon nitride film and the lower electrode 15 is not oxidized, the capacitive insulating film 16 having the ONO structure has a thickness of about 60Å on the lower electrode 15. Is formed.

Next, as shown in FIG. 3, a polycrystalline silicon film containing a high concentration of impurities such as phosphorus or arsenic is deposited by vapor phase epitaxy to form a cell plate electrode 17. Then, by patterning by photolithography and etching techniques, an opening 21 is formed in the cell plate electrode 17 on the silicon oxide film 16 '. Here, when the cell plate electrode 17 is etched, since the silicon oxide film 16 'is thickly formed as an etching stopper on the pad polycrystalline silicon film 14, the pad polycrystalline silicon film 14 is also etched at the same time. Can be prevented.

After that, an interlayer insulating film 18 such as a silicon oxide film is formed on the cell plate electrode 17 by a vapor phase growth method, and the interlayer insulating film 18 and the silicon oxide film 16 'in the opening 21 are formed by photolithography and etching techniques.
By selectively removing and, bit contact 1
9 is formed. Then, the interlayer insulating film 1 is formed by the vapor phase growth method.
A tungsten film, a tungsten polycide film, or the like is formed on 8 and patterned by photolithography and etching techniques to form the bit line 20 connected to the pad polycrystalline silicon film 14.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the technical idea of the present invention. For example, as impurities introduced into the polycrystalline silicon film 9,
Other impurities such as antimony may be used instead of phosphorus. Further, impurities such as arsenic contained in the pad polycrystalline silicon film 14 and phosphorus contained in the lower electrode 15 of the capacitor are formed by patterning the polycrystalline silicon film 9 to form the pad polycrystalline silicon film 14 and the lower electrode 15 of the capacitor. It may be introduced after this.

[0019]

As described above, according to the present invention, by introducing the second impurity which lowers the oxidation resistance into the pad polycrystalline silicon film to be contacted, a thick film is formed only on the pad polycrystalline silicon film. A silicon oxide film can be formed, and a stable contact can be formed in a simple process without deteriorating the insulating characteristic of the capacitor insulating film.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention in the order of steps.

[Explanation of symbols]

 1 P-type semiconductor substrate 2 Element isolation film 3 Gate insulating film 4 Gate electrode 5, 6 N-type impurity diffusion layer 7 First interlayer insulating film 8 Storage contact 9 Polycrystalline silicon film 10, 12 Photoresist 11 Arsenic ion implantation 13 Phosphorus ion Injection 14 Pad Polycrystalline Silicon Film 15 Capacitor Lower Electrode 16, 16 'Capacitance Insulating Film 17 Capacitor Upper Electrode 18 Second Interlayer Insulating Film 19 Bit Contact 20 Bit Line 21 Opening

Claims (3)

[Claims] 1. A step of forming a gate electrode on a first conductivity type semiconductor substrate via a gate insulating film, a step of forming a pair of second conductivity type impurity diffusion layers separated by the gate electrode, A step of forming a polycrystalline silicon film on the second conductivity type impurity diffusion layer, a step of selectively introducing phosphorus into the polycrystalline silicon film and a step of selectively introducing arsenic into the polycrystalline silicon film, By patterning the polycrystalline silicon film,
A first polycrystalline silicon film containing phosphorus and covering one of the second conductivity type impurity diffusion layers, and a second polycrystalline silicon film containing arsenic while covering the other of the second conductivity type impurity diffusion layers. And a step of forming a capacitive insulating film having oxidation resistance on the first polycrystalline silicon film and the second polycrystalline silicon film, and the second polycrystalline silicon by thermal oxidation. A step of forming a silicon oxide film on the surface of the film; a step of forming a cell plate electrode on the capacitive insulating film; and a step of selectively etching the cell plate electrode on the silicon oxide film to form the cell plate. Forming an opening in the electrode; forming an interlayer insulating film on the cell plate electrode; selectively etching the silicon oxide film and the interlayer insulating film through the opening. A step of forming a bit contact by etching, and a step of forming a bit line connected to the second polycrystalline silicon film through the bit contact on the interlayer insulating film. Device manufacturing method. 2. A gate electrode formed on a first conductivity type semiconductor substrate via a gate insulating film, a pair of second conductivity type impurity diffusion layers separated by the gate electrode, and the second conductivity type impurity. A first polycrystalline silicon film containing a first impurity and formed on one of the diffusion layers, and a second polycrystalline silicon film formed on the other of the second conductivity type impurity diffusion layers, which reduces oxidation resistance. A second polycrystalline silicon film containing impurities, a silicon oxide film formed on the second polycrystalline silicon film, and a capacitive insulating film having oxidation resistance on the first polycrystalline silicon film. And a cell plate electrode having an opening on the silicon oxide film and formed on the cell plate electrode and connected to the second polycrystalline silicon film through the opening. A semiconductor memory device comprising: a conductive layer. 3. The second impurity is phosphorus, and the second impurity is phosphorus.
3. The semiconductor memory device according to claim 2, wherein the impurity of is arsenic.