JPH08204457A - Signal processing circuit and television signal receiver - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a television signal processing circuit suitable for integration into an IC. A video intermediate frequency (VIF) signal is supplied to a frequency discriminator 42a and an AM detector 41c, respectively.
The discrimination output of the frequency discriminator 42a is the low-pass filter 42.
It is given to the voltage controlled oscillator 42c via b. The first oscillation output of the voltage controlled oscillator 42c is supplied to the frequency discriminator 42a, and the PLL block 42 is brought into the locked state. On the other hand, from the voltage controlled oscillator 42c, the second oscillating output, which is phase-shifted by 90 degrees with respect to the first oscillating output, is supplied to the AM detector 41c, and the AM detector 41c synchronously detects the video intermediate frequency signal and outputs the base signal. Demodulate the band's video signal output. The output of the low-pass filter 42b is generated as the AFT output by the reference circuit 42d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit and a television signal receiver suitable for use in processing television signals, for example.

[0002]

2. Description of the Related Art In a television signal receiver, an RF signal processing circuit of a tuner receives a target broadcast wave, converts it into a predetermined intermediate frequency signal, amplifies it in an intermediate frequency amplification circuit, and then a baseband by a detection circuit. Is configured to demodulate the video signal and the audio signal. Most of these circuits in the current television signal receiver are integrated circuits (ICs).

FIG. 11 shows a conventional I for demodulating a baseband video signal and audio signal from an intermediate frequency signal.
The example of the C-ized detection circuit is shown.

That is, the intermediate frequency signal from the tuner is the SAWF (Surface Acoustic) for the video band.
ic wave filter) 10, the SAWF 10 extracts the video intermediate frequency (VIF) band, and the output of the SAWF 10 is supplied to the VIF input terminal 20 of the IC detection circuit. The VIF signal supplied to the VIF input terminal 20 is supplied to the VIF amplifier 3
After being amplified by 0, AM detection is performed in the AM synchronization detection circuit 40 based on the synchronization signal obtained by the PLL circuit, and the result is output to the output terminal 50 as a video signal.

The video signal detected by the AM synchronous detection circuit 40 is level-detected by the AGC circuit 60, and the output of the AGC circuit 60 is the VIF amplifier 30.
Is fed back to the AGC input terminal, and the video signal output level by the AM synchronous detection circuit 40 is controlled to be kept constant.

The output of the VIF amplifier 30 is also supplied to the AFT circuit 70, and the AFT circuit 70 discriminates it from the reference phase and outputs the discriminated output of the AFT signal to the output terminal 80. ing.

On the other hand, the intermediate frequency signal from the tuner is also supplied to the audio band SAWF 90, where the audio intermediate frequency (SIF) band is extracted, and the output of the SAWF 90 is supplied to the SIF input terminal 100. Then, the SIF signal supplied to the SIF input terminal 100 is detected by the audio detection circuit 110 and is output as an audio signal to the output terminal 12
It is configured to be output to 0. As shown in FIG. 11, the AFT circuit 70 includes an AFT tank coil 130.
Are connected as external parts of the IC.

FIG. 12 shows the structure of the AM synchronous detection circuit 40 shown in FIG. As described above, the AM synchronous detection circuit 40 includes the AM detection block 41 and the PL.
It is composed of an L block 42. The VIF signal from the VIF amplifier 30 is supplied to the two phase shifters 41a and 41b in the AM detection block 41, respectively. By the two phase shifters 41a and 41b,
The first phase shifter 41a generates a VIF output whose phase is delayed by Δθ1 with respect to the VIF input, and the second phase shifter 41b has a phase shifter with respect to the VIF input. A VIF output whose phase is advanced by Δθ2 is generated.

FIG. 13 shows the relationship between the output phases of the two phase shifters. That is, in FIG. 13, the horizontal axis represents frequency and the vertical axis represents output phases of the phase shifters 41a and 41b. The first phase shifter 41a used here is composed of a low-pass filter (LPF), and the second phase shifter 41b is composed of a high-pass filter (HPF). Therefore, if the cutoff frequencies fc of the two filters are the same, the two phase shifters 41a and 4a.
As for the phase difference of the output of 1b, as shown in FIG. 13, the phase relationship of 90 degrees is maintained regardless of the input frequency.

Returning to FIG. 12, the output of the first phase shifter 41a is supplied to the first input terminal of the phase discriminator 42a which constitutes the PLL block 42. The discriminant output of the phase discriminator 42a is supplied to the low-pass filter 42b, and is smoothed by the low-pass filter 42b to generate a control signal. The control signal generated by the low pass filter 42b is supplied to the voltage controlled oscillator 42c, and the output of the voltage controlled oscillator 42c is supplied to the second input terminal of the phase discriminator 42a. The phase discriminator 42a, the low-pass filter 42b, and the voltage-controlled oscillator 42c constitute a PLL, and as is well known, the phase shift relationship between the signals supplied to the first and second input ends of the phase discriminator 42a is 90 degrees. Because of P
LL is locked.

On the other hand, the output of the second phase shifter 41b is A
It is supplied to the first input terminal of the M detector 41c, and the output of the voltage controlled oscillator 42c is supplied to the second input terminal of the AM detector 41c. Therefore, the phase relationship between the VIF input supplied to the first input terminal of the AM detector 41c and the synchronization signal supplied from the voltage controlled oscillator 42c becomes 0 degree or 180 degrees, and the detection efficiency of the AM detector 41c is maximized. And the distortion rate of the detection output becomes the minimum.

FIG. 14 shows an example of a conventional voltage controlled oscillator used in the PLL block 42. In this voltage controlled oscillator 42c, a capacitor C1 and a coil L1 are connected in parallel between the other ends of resistors R1 and R2, one ends of which are connected to the operating power supply + Vcc. And the resistors R1 and R2
To the other end of each of the NPN type transistors Q1 and Q2, the bases of the NPN type transistors Q1 and Q2 are connected to the collectors of the opposing transistors, and the emitters of the transistors Q1 and Q2 are commonly connected. It is connected to a reference potential point (earth) via a constant current source I1. The constant current source I1 is configured such that the amount of current is controlled by the control signal CS, and is configured to derive the oscillation output V from the connection point between the resistor R1 and the collector of the transistor R1.

In the above structure, each transistor Q
The on and off operations of 1 and Q2 are repeated mutually.
The current amount in the constant current source I1 is controlled by the control signal CS.
Is changed by the capacitor C1 and the coil L
The amount of the oscillating current flowing in 1 changes, and the frequency of the oscillation output V appearing at the output end changes.

In this circuit, assuming that the currents flowing through the resistor R1, the coil L1 and the capacitor C1 are Ir, Il and Ic, respectively, these three currents and the oscillation output V derived at the output end.
As shown in FIG. 15, the phase relationship of each is 90 degrees.

[0015]

In the conventional configuration described above, in order to maximize the detection efficiency of the AM detector 41c, the phase difference between the two input signals to the detector 41c should be 0 degree or 180 degrees. Need to On the other hand, the PLL locks when the phase difference between the two input signals of the phase discriminator 42a is 90 degrees.

For this reason, in the conventional AM detector described above, it is necessary to provide the phase shifters 41a and 41b for shifting the VIFs in a 90-degree relationship with each other at the entrance of the IC forming the detection circuit.

However, as shown in FIG. 16, the output level of the first phase shifter 41a gradually decreases on the high frequency side with the cutoff frequency fc as a boundary, and the second phase shifter 41b has the cutoff frequency fc. Has a characteristic that the output level gradually decreases on the low frequency side with respect to the two phase shifters 41a,
The output levels at 41b have different frequency characteristics.

Therefore, when the carrier waves of the VIF input have different frequencies, the phase discriminator 42a and the AM detector 4 are detected.
The input level to 1c changes, and as a result, the PLL
The lock range changes, the AM detection level also changes, and the VIF sensitivity changes.

Further, in the conventional configuration, the phase shifter 41
In order to avoid the level change at a and 41b, the phase shifter 4
The signals before 1a and 41b are input to the AFT circuit, and it is not possible to adopt a circuit configuration in which the AFT circuit is incorporated in the PLL circuit after the phase shifter. Therefore, the AFT circuit is provided separately from the PLL circuit, which causes an increase in component cost and an adjustment process.

The present invention has been made in view of the above problems, and eliminates a phase shifter that shifts VIFs in a 90-degree relationship with each other, thereby degrading the detection performance of the 90-degree phase shifter. It is intended to be removed. Also AFT
The purpose of the present invention is to provide a signal processing circuit and a television signal receiver in which the circuit is incorporated in a PLL circuit so that the tank coil for AFT is not required, thereby reducing the cost of parts and the adjustment process. To do.

[0021]

A signal processing circuit according to claim 1 of the present invention, which has been made to achieve the above object, comprises:
The input signal (eg VIF input in FIG. 1) is the first of each
Of the phase discriminator (for example, the phase discriminator 42a of FIG. 1) and an AM synchronous detector (for example, the AM of FIG.
Synchronous detector 41c) and 90
An oscillator (for example, oscillator 42c in FIG. 1) that provides a first and a second oscillating output having a phase difference of 90 degrees, the first oscillating output from the oscillator having a phase relationship of approximately 90 degrees to the input signal. (Eg output 1 in FIG. 1) is fed to the second input of the phase discriminator and is almost zero for the input signal.
Second from an oscillator having a phase relationship of 180 degrees or 180 degrees
The oscillation output (for example, the output 2 in FIG. 1) is supplied to the second input terminal of the AM synchronous detector, and the AM detection output of the input signal is extracted from the AM synchronous detector. Is characterized by.

The signal processing circuit according to claim 2 of the present invention uses a voltage controlled oscillator (eg, the voltage controlled oscillator 42c of FIG. 3 or FIG. 6) as an oscillator, and uses a phase discriminator (eg, the phase discrimination of FIG. 1). Low-pass filter (for example, the low-pass filter 4 in FIG. 1) that smoothes the discrimination output of the device 42a
The output of 2b) is applied to the control input terminal of the voltage controlled oscillator to form a PLL by the voltage controlled oscillator, the phase discriminator and the low pass filter.

The television signal receiver according to claim 3 of the present invention is also a phase discriminator (for example, FIG. 8) in which a video carrier signal (for example, VIF input in FIG. 8) is input to each first input terminal. The phase discriminator 42a) and the AM synchronous detector (for example, the AM synchronous detector 41c in FIG. 8), and the low-pass filter (for example, in FIG. 8) that receives the discrimination output of the phase discriminator and generates a control signal with the discriminated output smoothed. A low-pass filter 42b) and a control signal generated by the low-pass filter are received, and a first oscillation output (for example, output 1 in FIG. 8) having a phase relationship of approximately 90 degrees with the video carrier signal is generated based on the control signal. Then, the first oscillation output is supplied to the second input terminal of the phase discriminator, and the second oscillation output having a phase relationship of almost 0 degree or 180 degrees with respect to the video carrier signal (for example, It generates output 2) in FIG. 8, the second
A voltage-controlled oscillator (for example, the voltage-controlled oscillator 42c in FIG. 8) that supplies the oscillation output to the second input terminal of the AM synchronous detector, and the video detection output is extracted from the AM synchronous detector. Is characterized by.

The signal processing circuit according to claim 4 of the present invention is characterized in that the AFT output is extracted based on the output from the low-pass filter (for example, the low-pass filter 42b of FIG. 8).

According to a fifth aspect of the present invention, in a television signal receiver, a phase discriminator (for example, FIG. 8) in which a video carrier signal (for example, VIF input in FIG. 8) is input to each first input terminal. The phase discriminator 42a) and the AM synchronous detector (for example, the AM synchronous detector 41c in FIG. 8), and the low-pass filter (for example, in FIG. 8) that receives the discrimination output of the phase discriminator and generates a control signal with the discriminated output smoothed. A low-pass filter 42b) and a control signal generated by the low-pass filter are received, and a first oscillation output (for example, output 1 in FIG. 8) having a phase relationship of approximately 90 degrees with the video carrier signal is generated based on the control signal. Then, the first oscillation output is supplied to the second input terminal of the phase discriminator, and the second oscillation output having a phase relationship of almost 0 degree or 180 degrees with respect to the video carrier signal (for example, It generates output 2) in FIG. 8, the second
A voltage controlled oscillator (for example, the voltage controlled oscillator 42c in FIG. 8) that supplies the oscillation output to the second input terminal of the AM synchronous detector, the video detected output is extracted from the AM synchronous detector, and a low pass filter is provided. A based on the output from
It is characterized in that the FT output is extracted.

The signal processing circuit according to claim 6 of the present invention is a phase discriminator (for example, the phase discriminator of FIG. 1) in which an input signal (for example, the VIF input of FIG. 1) is input to each first input terminal. 42a) and an AM synchronous detector (see, for example, FIG.
AM synchronous detector 41c) and an oscillator (for example, the voltage controlled oscillator 4 shown in FIGS. 1 and 3) that provides first and second oscillation outputs having a phase difference of 90 degrees with each other in synchronization with the input signal.
2c) and a first oscillating output from an oscillator having a phase relationship of approximately 90 degrees with respect to the input signal (see FIG.
And output 1 in FIG. 3) is fed to the second input of the phase discriminator and a second oscillator output (eg FIG. 1 and FIG. 1) from an oscillator having a phase relationship of approximately 0 or 180 degrees with respect to the input signal. The output 2) of FIG. 3 is adapted to be supplied to the second input terminal of the AM synchronous detector, and the AM detected output of the input signal is extracted from the AM synchronous detector, The oscillator converts the inflow current into a capacitor (for example, the capacitor C2 in FIG. 3) connected to the first oscillation output end into a second oscillation output and converts the current into a phase difference of 90 degrees. It is characterized in that it is designed to provide two oscillation outputs.

Further, in the signal processing circuit according to claim 7 of the present invention, a phase discriminator (for example, FIG. 1) in which an input signal (for example, the VIF input of FIG. 1) is input to each first input terminal.
Of the phase discriminator 42a) and the AM synchronous detector (for example, the AM synchronous detector 41c of FIG. 1), and an oscillator (in synchronization with the input signal, which provides first and second oscillation outputs having a phase difference of 90 degrees with each other). For example, the voltage controlled oscillator 42c of FIGS. 1 and 6 is provided, and the first oscillation output (for example, the output 1 of FIGS. 1 and 6) from the oscillator having a phase relationship of approximately 90 degrees with respect to the input signal has a phase. It is supplied to the second input of the discriminator and is approximately 0 degrees or 180 degrees with respect to the input signal.
The second oscillating output (eg output 2 of FIGS. 1 and 6) from the oscillator having a phase relationship of degrees is the second of the AM synchronous detector.
And an AM detection output of the input signal from the AM synchronous detector, wherein the oscillator is a 90-degree phase shift circuit (for example, in FIG. 6). Transistors Q5 and Q6 and capacitor C
2) is provided in the loop, and by taking out the input voltage and the output voltage of this phase shift circuit respectively, two oscillation outputs having a phase difference of 90 degrees are provided.

[0028]

In the signal processing circuit having the structure of claim 1, V
An oscillator 42 that provides first and second oscillation outputs having a phase difference of 90 degrees with each other in synchronization with a carrier wave input signal such as IF.
c, a first oscillation output of which is supplied to the input end of the phase discriminator 42a, and a second output from the oscillator 42c having a phase relationship of approximately 0 degrees or 180 degrees with respect to the input signal.
Since the oscillation output is supplied to the AM synchronous detector 41c, it is possible to realize an AM detector without a phase shifter for shifting the VIF input and the like by 90 degrees.

Further, in the signal processing circuit according to the second aspect of the invention, the output of the low-pass filter 42b for smoothing the discrimination output of the phase discriminator 42a is applied to the control input terminal of the voltage controlled oscillator 42c to form a PLL. The stable AM synchronous detection action can be guaranteed.

The television signal receiver having the structure of claim 3 further includes an oscillator 42c which locks to the video carrier input to provide first and second oscillation outputs having a phase difference of 90 degrees with each other. And PL by the second oscillation output
Since the lock function of L and the AM synchronous detection are performed, it is possible to realize a highly versatile IC that can handle any video intermediate frequency.

Further, in the signal processing circuit according to the fourth aspect of the invention, the AFT output is extracted based on the output from the low pass filter 42b forming the PLL.
It is possible to reduce the number of parts and the adjustment cost.

In the television signal receiver of the present invention, the PLL and AM are provided at the output of the oscillator 42c which locks to the video carrier input and provides the first and second oscillation outputs having a phase difference of 90 degrees with each other. Since the AFT output is obtained based on the output of the PLL low-pass filter by operating the synchronous detection circuit, there is no deterioration in performance due to the phase shifter, and a television signal receiver that does not require an AFT tank coil is used. Can be provided.

In the signal processing circuit of the sixth aspect, the inflow current to the capacitor C2 connected to the first oscillation output terminal as an oscillator is converted into a voltage and taken out as a second oscillation output. Since it is designed to be used, it is possible to provide two oscillation outputs having a phase difference of 90 degrees with each other with a simple configuration.

Further, in the signal processing circuit according to the present invention, a 90 ° phase shift circuit is provided in the loop as an oscillator, and the input voltage and the output voltage of this phase shift circuit are respectively taken out. Is used, it is possible to provide two oscillation outputs having a phase difference of 90 degrees with each other by a similarly simple configuration.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A signal processing circuit and a television signal receiver according to the present invention will be described below based on the embodiments shown in the drawings. When the reference numerals used in FIGS. 1 to 10 described below are the same as those in FIGS. 11 to 16, the reference numerals indicate the same or corresponding portions, and accordingly, the detailed description thereof will be made. The description is omitted.

FIG. 1 is a block diagram showing the configuration of an embodiment of the signal processing circuit of the present invention. The configuration shown in FIG. 1 shows a VIF demodulation circuit corresponding to the AM detection block 41 and the PLL block 42 shown in FIG.

In FIG. 1, the phase discriminator 42a, the low-pass filter 42b, and the voltage control oscillator 42c constitute a PLL block 42. The VIF input is supplied to one input end of the phase discriminator 42a, and the phase discriminator 42a
A first output of the voltage controlled oscillator 42c is supplied to the other input terminal of the. The discriminative output of the phase valve 42a is smoothed by the low-pass filter 42b, and the smoothed control signal CS is supplied (feedback) to the voltage controlled oscillator 42c. With this configuration, the voltage controlled oscillator 42c
Has the same frequency as the carrier wave at the VIF input, and the phase difference between the carrier wave phase θ1 of the VIF input to the phase discriminator 42a and the phase θ2 of the output 1 of the oscillator is about 90 degrees. θ1-θ2 = 90 ° Equation 1

The VIF input is supplied to the first input terminal of the AM synchronous detection circuit 41c in the AM detection block 41, and the voltage controlled oscillator 42c is supplied to the second input terminal of the AM synchronous detection circuit 41c. The second oscillation output is supplied. The second oscillation output has a phase difference of 90 degrees with respect to the first oscillation output, whereby the VIF input is synchronously detected by the AM detector and a baseband video signal is obtained. .

The relationship between the phase θ3 of the second oscillation output and the phase θ2 of the first oscillation output in the voltage controlled oscillator 42c is expressed by the following equation 2. θ3 = θ2 ± 90 ° ... Equation 2

Since the relationship between the phases θ1 and θ3 of the two signals input to the AM detector 41c is expressed by the expression 3 according to the relationship between the expressions 1 and 2, the detection efficiency of the AM detector 41c is maximized. , The distortion rate is also the minimum. θ1-θ3 = 0 ° or 180 ° ... Equation 3

This state is shown as a vector diagram in FIG. The vector diagram shown in FIG. 2 shows a case where the relationship between the phase θ3 of the second oscillation output from the voltage controlled oscillator 42c and the phase θ1 of the carrier wave of the VIF is 0 degree.

As described above, in the processing circuit shown in FIG. 1, the voltage-controlled oscillator 42c is provided with two oscillating outputs whose phases are different by 90 degrees, so that the AM detector can be provided without providing a phase shifter in the VIF path. The two inputs are controlled to have the same phase (or 180 degrees) so that the AM detection block 41 can perform the synchronous detection.

FIG. 3 shows the voltage controlled oscillator 4 shown in FIG.
2c shows a specific example. The example shown in FIG. 3 is different from the conventional example described with reference to FIG. 14 in that a circuit including a capacitor C2 is further provided at the first oscillation output terminal to convert the current flowing into the capacitor into a second voltage. By taking out as oscillation outputs, two oscillation outputs having a phase difference of 90 degrees are provided.

That is, the operating power supply + Vcc line is
A resistor R3 is connected, and the other end of the resistor R3 is connected to the collector of the NPN transistor Q3 and constitutes a second output end. The base of the transistor Q3 is connected to the constant voltage source E, the emitter is connected to the constant current source I2, and the capacitor C2 is connected to the first output terminal 1.

The current I3 flowing through the capacitor C2 has the same phase as the current Il flowing through the capacitor C1. Therefore, the voltage V2 having the same phase as the current flowing through the capacitor C1 is output 2
Output from This makes it possible to extract two outputs with a phase difference of 90 degrees. Two output voltages V
The phase relationship between 1 and V2 is shown in FIG.

FIG. 5 is a block diagram showing another example of the voltage-controlled oscillator which produces 90 ° oscillation outputs. In the example shown in FIG. 5, the 90-degree phase shifter 42c1 is arranged in the loop, and the input signal and the output signal of the 90-degree phase shifter are taken out as the output 1 and the output 2, respectively. A specific circuit can be configured as shown in FIG.

That is, resistors R1 and R2 are connected to the power supply + Vcc.
Are connected to the collectors of the transistors Q1 and Q2, respectively, and the capacitor C1 is connected between both ends of the resistors R1 and R2. The emitters of the transistors Q1 and Q2 have resistors R3 and R, respectively.
4 are connected, and these are connected to the constant current source I1 controlled by the control signal CS.

The collectors of the transistors Q1 and Q2 are emitter follower-connected transistors Q4 and Q3.
Of the transistor Q3, and the emitter of the transistor Q3 is connected to the base of the transistor Q1 to form the output terminal of the first oscillation output V1. The emitter of the transistor Q3 is connected to the base of the transistor Q5 whose collector is connected to the power supply + Vcc.

The emitter of the transistor Q5 is connected to the constant current source I2 via the resistor R5, while the emitter of the transistor Q4 is connected to the constant current source I2 via the resistor R6.
Connected to the base of. The collector of the transistor Q6 is 1 / l of the sink current of the constant current source I2.
It is connected to a parallel circuit of a constant current source I2 / 2 and a capacitor C2 for allowing a constant current of 2 to flow in.

The collector of the transistor Q6 is connected to the base of an emitter follower transistor Q7 having a resistor R7 connected to the emitter thereof, and the emitter of the transistor Q7 is connected to the base of the transistor Q2 to form a feedback circuit. The collector of the transistor Q6 is further connected to the base of an emitter follower transistor Q8 having a resistor R8 connected to the emitter thereof, and the emitter of the transistor Q8 constitutes the output end of the second oscillation output V2.

In the above structure, the transistors Q5,
The Q6 and the capacitor C2 form a 90-degree phase shifter. A differential pair of the transistors Q5 and Q6 converts the oscillation output of the first oscillation output V1 into an in-phase current signal I3, and flows this into the capacitor C2 to make it 90 degrees out of phase with the first oscillation output V1. The voltage signal V2 is obtained. Note that FIG. 7 is a vector diagram showing the phase relationship among the V1, V2, and I3.

In the two types of voltage controlled oscillators described above, two oscillation outputs having a phase difference of 90 degrees can be obtained regardless of the lock frequency of the PLL. Therefore, this voltage controlled oscillator is useful for a signal processing circuit as shown in FIG. 1, that is, a synchronous detection circuit for carrier wave signals.

FIG. 8 shows that the AFT function is added to the configuration of FIG.
An example of a television signal receiver adapted to obtain a detection output and an AFT output of a video signal is shown. In FIG. 8, the same reference numerals as those in FIG. 1 described above indicate the same parts.
In the example shown in FIG. 8, a reference circuit 42d by an operational amplifier is newly provided, and the output of the low-pass filter 42b, which is the control voltage CS of the voltage controlled oscillator, is supplied to the first input terminal of this reference circuit 42d. There is. Further, a DC voltage from the constant voltage source 42e is supplied to the second input terminal of the reference circuit 42d.

FIG. 9 illustrates the operation of the reference circuit 42d. As shown in FIG. 9A, the DC voltage from the constant voltage source 42e corresponding to the center frequency (f0) of the AFT is used as the reference voltage. , And the control signal obtained by the low-pass filter 42b are compared.
Then, as shown in FIG. 9B, an AFT signal centered at the desired frequency (f0) is obtained by amplifying the result.

A block diagram of a television signal receiver using the circuit shown in FIG. 8 is shown in FIG. The difference from the conventional one shown in FIG.
By incorporating the T circuit, it is possible to reduce the number of AFT tank coils. This leads to a reduction in the number of parts and a reduction in tank coil adjustment costs. Secondly V
By reducing the phase shifters for making the IF inputs have a 90-degree relationship with each other, the same AM detection performance can always be obtained regardless of the frequency to be handled.

Taking a television receiver as an example, it is possible to support VIF frequencies of television broadcasting in the whole world by the same IC, there is no deterioration in performance due to the phase shifter, and the tank coil for AFT is required. The beneficial effect of not doing so is obtained.

[0057]

As is apparent from the above description, claim 1
According to the signal processing circuit described in (1), the signal processing circuit includes an oscillator that provides first and second oscillation outputs having a phase difference of 90 degrees in synchronization with a carrier input signal such as VIF, and the first oscillation output discriminates the phase. The second oscillation output from the oscillator, which is supplied to the input terminal of the detector and has a phase relationship of approximately 0 degrees or 180 degrees with respect to the input signal, is configured to be supplied to the AM synchronous detector. It is possible to realize an AM detector in which a phase shifter for shifting the phase shifts of 90 degrees from each other is eliminated.

Therefore, it is possible to provide a signal processing circuit which does not affect the lock range of the PLL, the AM detection level, etc. even if the carrier frequency such as VIF changes.

According to the signal processing circuit of the second aspect, the output of the low-pass filter for smoothing the discrimination output of the phase discriminator is applied to the control input terminal of the voltage controlled oscillator, and P
Stable AM because it is configured to form LL
The synchronous detection function can be guaranteed.

According to a third aspect of the present invention, there is provided a television signal receiver including an oscillator which locks to a video carrier input and provides first and second oscillation outputs having a phase difference of 90 degrees with each other. Since the PLL lock function and the AM synchronous detection are performed by the second oscillation output, it becomes easy to handle the video carrier frequency used all over the world with the same IC.

Further, according to the signal processing circuit of the fourth aspect, the AFT output is extracted based on the output of the low-pass filter forming the PLL. Therefore, it is possible to reduce the number of parts and the adjustment cost. Becomes

According to a fifth aspect of the present invention, there is provided a television signal receiver in which PLL and AM are provided at the outputs of the oscillators which lock to the video carrier input to provide first and second oscillating outputs having a phase difference of 90 degrees from each other. Operate the synchronous detection circuit,
Also, based on the output of the PLL low-pass filter, the AFT
Since the output is obtained, the performance is not deteriorated by the phase shifter, and it is not necessary to provide an AFT tank circuit or the like as in the conventional case.

According to the sixth aspect of the signal processing circuit, the current flowing into the capacitor, which is connected to the first oscillation output terminal of the oscillator, is converted into a voltage and taken out as the second oscillation output. Since such a circuit is used, it is possible to provide a circuit suitable for an IC having two oscillation outputs having a phase difference of 90 degrees with a simple configuration.

Further, according to the signal processing circuit of the seventh aspect, a 90 ° phase shift circuit is provided in the loop as an oscillator, and an input voltage and an output voltage of this phase shift circuit are respectively taken out. Since these are used, it is possible to provide two oscillation outputs having a phase difference of 90 degrees with each other with a similarly simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an AM synchronous detection circuit according to a signal processing circuit of the present invention.

FIG. 2 is a vector diagram showing an operation in the embodiment of FIG.

FIG. 3 is a connection diagram showing a first embodiment of a voltage controlled oscillator used in the embodiment of FIG.

FIG. 4 is a vector diagram showing an operation in the embodiment shown in FIG.

5 is a block diagram showing a second embodiment of the voltage controlled oscillator used in the embodiment of FIG. 1. FIG.

6 is a connection diagram showing a specific example of the configuration shown in FIG.

FIG. 7 is a vector diagram showing an operation in the embodiment shown in FIG.

FIG. 8 is a block diagram showing a partial configuration of a television signal receiver of the present invention.

9 is a characteristic diagram illustrating an AFT function in the block diagram shown in FIG.

10 is a block diagram of a case where a television signal receiver is configured using the configuration of FIG.

FIG. 11 is a block diagram showing an example of a conventional television signal receiver.

12 is a block diagram showing an example of an AM synchronous detection part used in FIG. 11. FIG.

FIG. 13 is a characteristic diagram showing an operation of the phase shifter used in FIG.

14 is a connection diagram showing an example of the voltage controlled oscillator used in FIG.

FIG. 15 is a vector diagram showing an operation in the example shown in FIG.

16 is a characteristic diagram showing frequency characteristics of the phase shifter used in FIG.

[Explanation of symbols]

 10 SAW filter for video band 20 VIF (video intermediate frequency) input terminal 30 VIF (video intermediate frequency) amplifier 40 AM synchronous detection circuit 41 AM detection block 42 PLL block 42a phase discriminator 42b low pass filter 42c oscillator (voltage controlled oscillator) 42d Reference circuit 42e Constant voltage source 50 Video signal output terminal 60 AGC circuit 70 AFT circuit 80 AFT signal output terminal 90 Audio band SAW filter 100 Audio intermediate frequency input terminal 110 Audio detection circuit 120 Audio signal output circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshito Kogure 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (7)

[Claims] 1. A phase discriminator and an AM synchronous detector whose input signals are input to respective first input terminals, and first and second phase shifters which have a phase difference of 90 degrees with each other in synchronization with the input signals. An oscillator providing an oscillating output, the first oscillating output from the oscillator having a phase relationship of approximately 90 degrees with respect to the input signal is supplied to a second input of a phase discriminator, and the input signal A second oscillating output from the oscillator having a phase relationship of approximately 0 degree or 180 degrees with respect to the AM synchronous detector, and the second oscillating output from the AM synchronous detector being supplied to the second input terminal of the AM synchronous detector. A signal processing circuit characterized by extracting an AM detection output of an input signal. 2. The oscillator is composed of a voltage controlled oscillator, and the output of a low pass filter for smoothing the discriminant output of the phase discriminator is applied to a control input terminal of the voltage controlled oscillator so that the voltage controlled oscillator and the phase discriminator are provided. The signal processing circuit according to claim 1, wherein the PLL is configured by a low-pass filter. 3. A phase discriminator and an AM synchronous detector, each of which receives a video carrier signal at a first input terminal thereof, and a discriminant output of the phase discriminator to generate a control signal having a smoothed discriminant output. Receiving a control signal generated by the low-pass filter, and generating a first oscillation output having a phase relationship of approximately 90 degrees with the video carrier signal based on the control signal,
The first oscillating output is supplied to the second input end of the phase discriminator and is approximately 0 degrees or 1 with respect to the video carrier signal.
A second oscillating output having a phase relationship of 80 degrees,
A television signal receiver, comprising: a voltage controlled oscillator for supplying an oscillation output to a second input terminal of the AM synchronous detector, and a video detection output is extracted from the AM synchronous detector. . 4. The signal processing circuit according to claim 2, wherein the AFT output is extracted based on the output from the low pass filter. 5. A phase discriminator and an AM synchronous detector, each of which receives a video carrier signal at its first input terminal, and a discriminant output of the phase discriminator to generate a control signal having a smoothed discriminant output. Receiving a control signal generated by the low-pass filter, and generating a first oscillation output having a phase relationship of approximately 90 degrees with the video carrier signal based on the control signal,
The first oscillating output is supplied to the second input end of the phase discriminator and is approximately 0 degrees or 1 with respect to the video carrier signal.
A second oscillating output having a phase relationship of 80 degrees,
A voltage-controlled oscillator for supplying an oscillation output to a second input terminal of the AM synchronous detector, wherein a video detection output is extracted from the AM synchronous detector, and an AF is detected based on an output from the low-pass filter.
A television signal receiver characterized in that T output is extracted. 6. A phase discriminator and an AM synchronous detector whose input signals are inputted to respective first input terminals, and first and second phases which have a phase difference of 90 degrees with each other in synchronization with said input signals. An oscillator providing an oscillating output, the first oscillating output from the oscillator having a phase relationship of approximately 90 degrees with respect to the input signal is provided to a second input of a phase discriminator, and the input signal is also provided. Almost 0 degrees or 180
A second oscillating output from the oscillator having a phase relationship of degrees is supplied to a second input end of the AM synchronous detector, and the AM synchronous detector detects the AM of the input signal.
The detection output is extracted, and the oscillator converts a current flowing into a capacitor connected to the first oscillation output end into a second oscillation output to convert a phase difference to a phase difference. A signal processing circuit, characterized in that it is configured to provide two oscillation outputs that are 90 degrees to each other. 7. A phase discriminator and an AM synchronous detector whose input signals are input to respective first input terminals, and first and second phase shifters which have a phase difference of 90 degrees with each other in synchronization with the input signals. An oscillator providing an oscillating output, the first oscillating output from the oscillator having a phase relationship of approximately 90 degrees with respect to the input signal is provided to a second input of a phase discriminator, and the input signal is also provided. Almost 0 degrees or 180
A second oscillating output from the oscillator having a phase relationship of degrees is supplied to a second input end of the AM synchronous detector, and the AM synchronous detector detects the AM of the input signal.
The detection output is extracted, and the oscillator has a phase shift circuit of 90 degrees in a loop, and by extracting the input voltage and the output voltage of this phase shift circuit, respectively, the phase difference is A signal processing circuit, which is configured to provide two oscillation outputs of 90 degrees.