JPH08204564A - SEMICONDUCTOR DEVICE, SEMICONDUCTOR CIRCUIT USING THE SAME, CORRELATION EQUIPMENT DEVICE, A / D CONVERTER, D / A CONVERTER, SIGNAL PROCESSING SYSTEM - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a semiconductor device having a structure capable of reducing the circuit scale, improving the operation speed, and reducing the power consumption. In a semiconductor device in which a capacitor is connected to multiple input terminals, one terminal of each capacitor is commonly connected and is input to a sense amplifier, the semiconductor device has means for resetting the commonly connected capacity terminals, and reset means Is a MOSFET and 2
A structure which is divided into one or more MOSFETs and which inputs the drive pulse of the reset means and the reverse phase pulse of the opposite phase of the drive pulse is connected to the capacitance terminal, and between the multiple input terminals and each capacitance. The switch means is provided, and the reset means is M
It is characterized in that a structure which is an OSFET and is divided into two or more MOSFETs and which inputs a drive pulse and a reverse phase pulse of the reset means is connected to a terminal between the switch means and the capacitor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multi-input terminal for performing parallel signal processing, and a semiconductor circuit using the same, a correlation operation device, an A / D converter, a D / A converter, and signal processing. It is about the system.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device which performs parallel operation processing, as the number of signals to be operated in parallel increases,
Since the circuit scale increases exponentially, the manufacturing cost increases and the yield decreases. Also,
There has been a problem that the delay of wiring and the like accompanying the increase in the circuit scale and the increase in the number of calculations in the circuit reduce the calculation speed and further significantly increase the power consumption.

For example, in the case of the solid-state image pickup device shown in FIG. 27, an image pickup device 41 is arranged along the vertical and horizontal axes, and a time series analog signal from a sensing section 60 as an area sensor is digitalized by an A / D converter 40. It is converted into a signal and is temporarily stored in the frame memory 39. These signals are arithmetically processed by the arithmetic circuit 38 and output from the arithmetic output circuit 50. Specifically, for example, the amount of movement (ΔX, ΔY) of the object can be output by the correlation calculation between the image data at different times.

[0004]

However, when attempting to perform real-time processing of a moving image, the number of processing operations is extremely large, and in order to obtain a more realistic image, the circuit scale is a series. However, there is a problem in that the processing speed is slowed down. For example, M, which has been proposed as a method of compressing / expanding moving images,
A device that can actually process the PEG2 system is still under development. Therefore, as a problem of the above-mentioned parallel operation processing, there are problems that the operation speed decreases and the power consumption increases with the increase of the circuit scale. Further, there is also a problem that the manufacturing cost is increased and the manufacturing yield is reduced due to the increase of the circuit scale.

Further, regarding a majority logic circuit useful for the above arithmetic processing circuit, Nikkei Electronics “Economical majority logic IC realized in CMOS” 1973.11.
5.132P to 144P. However, this is one in which a majority logic circuit is disclosed as one of digital signal processing and is formed by CMOS,
In this case as well, the number of elements by the CMOS increases and the number of stages of the arithmetic processing increases, so that the circuit scale and power consumption also increase, and the similar problem of reduction in the arithmetic speed occurs.

In view of the above conventional problems, the present invention provides a semiconductor device having an unprecedented structure capable of reducing the circuit scale, improving the operation speed, and reducing the power consumption, and a semiconductor using the semiconductor device. An object is to provide a circuit, a correlation operation device, an A / D converter, a D / A converter, and a signal processing system.

[0007]

According to a first aspect of the present invention, a capacitor is connected to multiple input terminals, one terminal of each capacitor is commonly connected, and a semiconductor device is input to a sense amplifier. In resetting a commonly connected capacitance terminal, the resetting means is a MOSFET and is divided into two or more MOSFETs, and a driving pulse of the resetting means and a negative phase opposite to the driving pulse The feature is that the structure for inputting a pulse is connected to the same terminal.

In the above configuration, the commonly connected terminals can be set to the reset potential more accurately, and as a result, the signals can be output in response to the minute signal change occurring at the commonly connected terminals, that is, the sensitivity is increased. Therefore, there is a great effect that a high-speed response is possible and, as a result, it also contributes to low power consumption.

According to a second invention of the present invention, the structure is
The semiconductor substrate formed by sandwiching the electrodes for applying the anti-phase pulse on the semiconductor substrate and a semiconductor impurity layer of a different conductivity type, the semiconductor impurity layers being electrically connected together and the capacitor commonly connected. It is connected to the terminal. In the above structure, it is possible to more accurately set the commonly connected terminals to the reset potential.

A third aspect of the present invention is characterized in that the sum of the gate capacitances of the MOSFETs of the reset means is approximately twice the gate capacitance of the structure.
In the above structure, it is possible to more accurately set the commonly connected terminals to the reset potential.

A fourth aspect of the present invention is characterized in that the sum of the gate widths W of the MOSFETs of the reset means is approximately twice the gate width of the structure. In the above structure, it is possible to more accurately set the commonly connected terminals to the reset potential.

According to a fifth aspect of the present invention, the MOSFET of the reset means is divided into two MOSFETs of the same type and the type of the semiconductor impurity layer of the structure is the same as the type used for the reset means. Is characterized by.

According to a sixth aspect of the present invention, the gate width W and the gate length L of the MOSFET of the reset means divided into two parts.
Are substantially equal to each other, and the gate width and the gate length of the structure are also substantially equal to each other.

According to a seventh aspect of the present invention, in a semiconductor device in which capacitors are connected to multiple input terminals, and one terminal of each capacitor is commonly connected to be input to a sense amplifier, the multiple input terminals and the capacitors are connected. And a reset means for resetting a voltage between the capacitance and the switch means, the reset means being a MOSFET and divided into two or more MOSFETs. And a structure for inputting the drive pulse and the anti-phase pulse is connected between the switch means and the capacitor. In the above configuration, the potential between the switch and the capacitor is
It becomes possible to reset more accurately and at high speed. Therefore, it is possible to more accurately set the absolute value of the minute voltage change caused by the capacitance division to the commonly connected terminals on the opposite side through the respective capacitances, and thus the sensitivity is increased, and therefore high-speed response and low response are possible. It has a great effect of contributing to power consumption.

According to an eighth aspect of the present invention, the structure has a semiconductor impurity layer of a conductivity type different from that of the semiconductor substrate formed on the semiconductor substrate with electrodes for applying the anti-phase pulse sandwiched therebetween. A semiconductor impurity layer of a conductivity type different from that of the substrate is electrically connected to a terminal of the capacitance on the input terminal side. With the above structure, the potential between the switch and the capacitor can be reset more accurately.

A ninth aspect of the present invention is characterized in that the total gate capacitance of the MOSFETs of the reset means is approximately twice the gate capacitance of the structure. With the above structure, the potential between the switch and the capacitor can be reset more accurately.

A tenth aspect of the present invention is characterized in that the sum of the gate widths W of the MOSFETs of the reset means is approximately twice the gate width of the structure. With the above structure, the potential between the switch and the capacitor can be reset more accurately.

An eleventh invention according to the present invention is that the MOSFET of the reset means is divided into two MOSFETs of the same type and the type of the semiconductor impurity layer of the structure is the same as the type used for the reset means. Characterize.

A twelfth aspect of the present invention is a gate width W and a gate length L of a MOSFET of reset means divided into two.
Are substantially equal to each other, and the gate width and the gate length of the structure are also substantially equal to each other.

A thirteenth invention according to the present invention is the first and seventh inventions.
In the invention, the reverse phase pulse rises / falls at the same time as or slower than the drive pulse.
In the above configuration, a large design margin can be secured, and each terminal can be set to the reset potential more accurately.

A fourteenth aspect of the present invention is characterized in that the input terminal of the reset means drive pulse is connected to the input terminal to the structure through a circuit including an inverter circuit. In the above configuration, a large design margin can be secured, and each terminal can be set to the reset potential more accurately.

A fifteenth invention according to the present invention is characterized in that the inverter circuit constitutes a delay circuit.
In the above configuration, a large design margin can be secured, and each terminal can be set to the reset potential more accurately.

A sixteenth invention according to the present invention has a plurality of semiconductor devices according to the first invention or the seventh invention, and the output of the first semiconductor device and / or the semiconductor device output among the plurality of semiconductor devices. The inverted output of is input to the second semiconductor device.

In a seventeenth aspect of the present invention, when the minimum capacitance of the capacitance means corresponding to the multiple input terminals is C, the total capacitance value of the capacitance means commonly connected is the minimum capacitance value. It is characterized in that it is almost an odd multiple of the capacity C.

An eighteenth invention according to the present invention is characterized in that a correlation calculating device is constituted by using the semiconductor circuit of the seventeenth invention.

A nineteenth invention according to the present invention is an A / D converter including the semiconductor device of the first invention or the seventh invention, wherein an analog signal is input to the semiconductor device and the analog signal is received in response to the analog signal. It is characterized by outputting a digital signal.

A twentieth invention according to the present invention is a D / A converter including the semiconductor device of the first invention or the seventh invention, wherein a digital signal is input to the semiconductor device and the digital signal is received in response to the digital signal. It is characterized by outputting an analog signal.

A twenty-first invention according to the present invention is a signal including any one of the correlation operation device of the eighteenth invention, the A / D converter of the nineteenth invention or the D / A converter of the twentieth invention. It is a processing system.

A twenty-second invention according to the present invention is characterized in that, in the signal processing system of the twenty-first invention, an image input device for inputting an image signal is included.

The twenty-third invention according to the present invention is characterized in that, in the signal processing system of the twenty-first invention, it includes a storage device for storing information, and, for example, a variety of signals such as image signal compression / expansion and arithmetic processing. It can be subjected to processing.

[0031]

Embodiments of the present invention will now be described in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a schematic explanatory view showing a semiconductor device of a first embodiment. In the figure, Q1 to Qn
Is an input terminal, and n multi-input terminals are provided. Two
Here, 21-1 to 221-n are NAND circuits,
The input from each input terminal Qi can be output at a desired voltage value. 202-1 to 202-n are capacitors, and their values may be common or different. 205 is a sense amplifier, 206 is an inverter in the sense amplifier 205, 204 is a second inverter in the sense amplifier 205, 207 is a reset switch for resetting the input part of the inverter 206, 210 is a reset power supply, and 211 is an output terminal. , 209 is the capacitor 2
2 shows the capacitance including the parasitic capacitance existing at one end including the input stage of the commonly connected first inverter 206 of No. 02.

The operation of this embodiment will be described with reference to FIG. 2. First, a low level signal is input to the set terminal of the NAND circuit 221 and the input side of each capacitor 202 is set to 2.5V or 5V, for example. It is fixed at a certain value. Then
The reset pulse φRES resets the input terminal of the inverter 206 in the sense amplifier 205 to the voltage of the reset power supply 210 by making the reset switch 207 conductive. When the reset pulse φRES is turned off, the commonly connected terminals 200 of the capacitor 202 are held at the reset potential. Next, each input signal is input terminal Q1
To Qn, then a high-level signal is input to the set of the NAND circuit 221, and a voltage change determined by the power supply voltage of each NAND circuit 221 is input to the input side of each capacitor 202. In this example, since signals are input from C1 and C2 to C1 and C2, V1 and C2 are input to the capacitor C1.
A voltage change of V2 has occurred in Cn, and no voltage change has occurred in Cn. Here, assuming that the capacitance of the capacitor 202 is Ci and the capacitance value of the parasitic capacitance is C0, and it is assumed that N capacitors 202 are connected in parallel, one end of the capacitors 202 connected in common has a capacitance for one input. The division changes the reset potential by Ci × V / (C0 + (C1 + C2 + ... + Cn)). V is a potential change at the capacitance input end. Therefore, the voltage change due to multiple inputs is caused by, for example, when the set terminal becomes high level and the NAND circuit 221 becomes conductive,
It is inverted and output, and Ci × V = C1 × V1 + C2 × V2 ...
Is applied to the input terminal of the sense amplifier 205.

When the input terminal voltage of the inverter 206 changes beyond the logic inversion potential of the inverter 206, the output terminal voltage of the inverter 206 is inverted accordingly. When a signal is input to each of the N inputs, the sum (Vp) of the capacitance division outputs is input to the input terminal of the inverter 206. Eventually, a high level signal or a low level signal is output to the output terminal 211 of the sense amplifier 205 according to the potential change input to the input end side of each capacitance. In this case, a low level is output to the output terminal 211. With the above configuration, a circuit for performing parallel calculation at high speed can be configured by inputting a certain multivariable signal to multiple input terminals. Further, this circuit can be configured with a smaller number of transistors as compared with a normal logic circuit, and is suitable for high speed operation and low power consumption. Furthermore, here is NA
Although the input is performed using the ND circuit 221, the present invention is not particularly limited to this. Even if the NAND circuit 221 is removed and direct input is performed, the essence does not change, and it goes without saying that there is no problem with other methods. Absent. For example, in the case of direct input, there are three kinds of inputs such as voltage change from a certain potential to the positive side, voltage change to the negative side, and no voltage change, or more inputs. It is possible to perform a multi-variable parallel operation such that an output is output accordingly.

Next, the means for resetting the commonly connected capacitance terminals 200 will be described in detail with reference to FIG. FIG. 3 is a diagram showing an example of details from the capacitor C (202) in FIG. 1 to the output of the sense amplifier 205 through the commonly connected terminal 200. In this example, two NMOS transistors 400 are used as means (switch 207 in FIG. 1) for resetting the commonly connected terminals 200 by the power supply 210. The drive pulse φRES for resetting is input to the gate of each NMOS transistor 400. Here, the NMOS transistor 400
Therefore, for example, the terminal 200 commonly connected while the control signal pulse is at the high level is reset by the power supply 210, and then the control signal pulse is set to the low level to turn off the NMOS transistor 400 to make the common connection. The terminal 200 is placed in a floating state. On the other hand, φRE
The S signal and φRES (bar, inverted signal) of the anti-phase pulse are input to the commonly connected terminals 200 via the capacitor 401.

By connecting this structure, the voltage change caused by the overlapping capacitance of the gate and drain (commonly connected terminal side) of the NMOS transistor, which occurs when the control signal pulse φRES turns on and off the NMOS transistor 400. , ΦR in anti-phase with control signal pulse φRES
Since the ES (bar) is canceled by the voltage change due to the supplied capacitance 401, the voltage changes of the commonly connected terminals 200 can be canceled each other, and the reset potential of the power supply 210 can be shared more accurately and at high speed. The connected terminal 200 can be reset. For example, when the control signal pulse φRES changes from 0V to 5V,
When RES (bar) changes from 5V to 0V and is reset, the changes can be canceled because they are applied as opposite phases via the NMOSFET 400 and the capacitor 401, respectively. Further, as an example, when the voltage of the commonly connected terminal 200 is set near the logic inversion voltage of the inverter 206, the value is set to the inverter 20.
It is clear that the closer it is to the logic inversion voltage of 6, the more the signal can be output corresponding to the minute signal change occurring at the commonly connected terminals 200, that is, the higher the sensitivity is, and the faster response is possible, and therefore Needless to say, it also contributes to the reduction of power consumption, and a great effect can be obtained. It is preferable that the value of the capacitance 401 used here is closer to the value of the gate-drain overlapping capacitance of the NMOS transistor 400 because the value is reset closer to the reset potential of the power supply 210, but the value is not limited thereto. Needless to say, even if the values are different, for example, half the values, a great effect can be obtained.

In FIG. 3, an NMOS as a reset means
Two transistors are connected in parallel. 1 NMO
Dividing into a plurality of transistors has the following advantages as compared with the case of resetting with an S transistor.

FIG. 4 shows a simple layout diagram of an NMOS transistor having the same gate width W when it is configured by one transistor and when it is configured by two transistors. In FIG. 4A, reference numerals 1 and 2 denote source or drain regions,
3 is a gate, and 8 and 9 are contact portions. In addition, although the scale of the drawing is different, in FIG. 4B, reference numerals 5, 6 and 7 are source or drain regions, 4 is a gate, 10, 11 and 12 are contact portions. When divided into a plurality of regions, the source region 1 can be shared like the source region 6 shown in FIG. 4B, and the area of the active region of the reset MOSFET having the channel length L = 1 μm and the channel width W = 4 μm is about 20%. Can be reduced.

FIG. 5 shows an example in which a PMOS transistor is used as the structure. In FIG. 5, two PMOS transistors 402 are used instead of the capacitor 401 shown in FIG. ΦRES (inversion signal) is input to the gate of the PMOS transistor 402, the drain side is connected to the commonly connected terminal 200, and the source side is connected to the reset power supply 210. The effect is similar to the case of the capacitor described in FIG. 3, the NMOS 400 that switches on and off by the control signal pulse φRES, and φRES (inversion signal).
The PMOS 402 that turns on and off with
Since the change in the common connection terminal 200 at the moment of turning off is canceled, as a result, the sensitivity is increased and a high-speed response is possible.
Therefore, it also contributes to low power consumption. That is,
The reset voltage can be set accurately and at high speed with respect to the capacitance C0209 on the common connection terminal 200 side.

[Embodiment 2] Embodiment 2 is an example in which the terminal 200 commonly connected to the potential of the reset power supply 210 can be reset more precisely. A semiconductor device of Example 2 will be described with reference to FIG. Similar to FIGS. 3 and 5, FIG. 6 shows an example of a detailed diagram from the capacitor C (202) of FIG. 1 to the output 211 of the sense amplifier 205 through the commonly connected terminal 200. In this example, as a means for resetting the commonly connected terminals 200 by the power supply 210, the NMOS transistor 400 is
It is divided and used. The driving control signal pulse φRES for resetting is input to the gate of the NMOS transistor 400, respectively. Since the NMOS transistor 400 is used here, for example, the control signal pulse φRE
The power supply 210 resets the terminal 200 commonly connected while S is at a high level, and then the control signal pulse φR
ES is set to low level to turn off the NMOS transistors 400, and the commonly connected terminals 200 are brought into a floating state. On the other hand, the φRES signal and the φR of the opposite phase pulse
As the structure for inputting ES (bar), the structure shown by the NMOS transistor 403 is used. This structure has a semiconductor impurity layer of a conductivity type different from that of the semiconductor substrate formed by sandwiching a gate electrode for applying a reverse phase pulse φRES (bar) on the semiconductor substrate. It is connected to the commonly connected capacitance terminals 200. That is, the source and the drain of the NMOS transistor 403 are commonly connected, and the reverse phase pulse φRES (ba
The capacitance from the gate electrode to which r) is applied to the side of the common connection terminal 200 is twice the capacitance between the gate and the drain, and it is possible to exactly cancel with the two NMOS transistors 400 to which the positive phase pulse φRES is applied. Becomes

In FIG. 6, this structure is connected to the terminal 200 having the drain and source of the NMOS transistor connected in common and the gate-drain capacitance thereof connected in common. The capacity of the NMOS transistor 400 is mainly the overlapping capacity of the gate and drain of the transistor (on the side of the commonly connected terminal 200), but the capacity value depends on the amount of impurities in the source / drain and the thermal history of forming the transistor. It is a large amount, and it is quite difficult to design and create accurately, and it has gate voltage dependence. A structure that is considered to have the same capacitance including the NMOS transistor 400 and the voltage dependency is shown in FIG.
It is a structure as shown by. The capacitance of such a structure can be approximately the same as the capacitance value of the NMOS transistor 400 used as the means for resetting, including the voltage dependency. Therefore, the capacity 209 shown in FIG.
It becomes possible to cancel the voltage change of the commonly connected terminals 200 due to the capacity division of
More accurately, the commonly connected terminals 200 can be reset.

For example, the terminals 2 commonly connected as an example.
When the voltage 00 is set near the logic inversion voltage of the inverter, the closer the value is to the logic inversion voltage of the inverter, the more the signal can be output corresponding to the minute signal change occurring at the commonly connected terminals 200. That is, it is obvious that the sensitivity becomes high, and high-speed response is possible, and it is needless to say that it contributes to the reduction of power consumption. Furthermore, the MO for the reset means
If the sum of the gate capacitance values of the S-transistors is approximately twice the gate capacitance of this structure, since the structure has a common source / drain, the total capacitance values are approximately the same, and the gate electrodes have opposite phases. Since the pulse is applied, the common-connected terminal 200 can be more accurately reset to the potential of the power supply 210. More preferably, if the sum of the gate widths of the MOS transistors for the reset means is set to be approximately twice the gate width of this structure, the structure has a common source / drain, and therefore the total gate overlap capacitance value is almost the same. Since they are equal to each other and a reverse phase pulse is applied to each gate electrode, the power supply 2
It is possible to more accurately reset the commonly connected terminals 200 to the potential of 10.

More preferably, the MOS of the reset means
If the FET is P-type, it is P-type, and if it is N-type, it is N-type
It is preferable that the type of the semiconductor impurity layer of the structure divided into two is equal to the type used for the reset means. MOSFE which is a reset means
When T is turned off, the voltage feed-through of the terminal 200 to which the capacitance is commonly connected is caused by the MOSFET as described above.
Depends on the overlapping capacitance of the gate and drain parts. This overlapping capacitance will be described with reference to FIG. In the figure, 1 and 2 are source or drain, 8 and 9 are contact portions, 14 is a gate electrode, 15 is a source or drain electrode, and 16 is a semiconductor substrate, and an NMOS transistor is illustrated as a whole. As the component of the above-mentioned overlapping capacity,
As shown in FIG. 7, the component A attributed to the drain region immediately below the gate electrode 14, the fringe effect component B depending on the channel width W, and the fringe effect at the edge end which is the drain end perpendicular to the channel width W direction. It is represented by the sum of the components C. Of these components, the capacity represented by components A and B is M
If the type of the OSFET and the total sum of the gate channel widths W are matched in the MOSFET of the reset means and the structure to which the anti-phase pulse is applied, they can be set to be substantially equal. On the other hand, in order to match the capacitance value of the fringe effect component C at the edge end, the MO of the reset means is used.
For the structure to which the anti-phase pulse is applied with the SFET, M
It is necessary to match the type of OSFET and the number of edges. That is, in a structure in which the drain and source of a MOSFET are common terminals, there are a total of four drain ends, so it is necessary to divide the MOSFET of the reset means into two and make four drain ends in the same manner. Become. If not divided, there are two drain ends, and the capacitance of the difference is insufficient. Therefore, when the MOSFET of the reset means is turned off, the feedthrough of the capacitance difference ΔC is added to the terminal 200 to which the capacitance is commonly connected. This leads to a decrease in accuracy. Here, the drain capacitance seen from the gate of the MOSFET of the reset means is Cr, the capacitance seen from the gate of the structure is Cr ′, and the capacitance parasitic on the commonly connected terminals 200 is Co.
When the control signal voltage input to the gate is V _DD , the feedthrough amount is ΔV = (Cr'-Cr) V _DD / (Cr + Cr '+ Co) = ΔCV _DD / (Cr + Cr' + Co). However, ΔC is Cr′-Cr.

Since the capacitance at the edge of the drain end does not depend on the value of the channel width W, the smaller the channel width W, the larger the value of this capacitance becomes, which is a problem in terms of characteristics.

In principle, even if the gate channel width W of each MOSFET divided into two is different, there is no problem in principle. For example, the channel width W of the structure is 10
In the case of μm, the channel width W of the MOSFET of the reset means may be 15 μm and 5 μm, respectively. However, when considering layout problems and other subtle variations (edge shapes, impurity diffusion, etc.) due to differences in patterns that occur due to other processes, MOSs of the same type and size
Needless to say, the FET is more preferable, and W = 10 μm for the structure having the channel width W of 10 μm.
It is more preferable to use two MOSFETs of the same type and the same size as the reset means.

In the example of FIG. 6, the reset means and the structure to which the anti-phase pulse is applied are all connected to the NMOS transistors, but the structure is not limited to this. When the reset means and the structure to which the anti-phase pulse is applied are each a PMOS transistor or a plurality of structures are connected, both the NMOS transistor and the PMOS transistor are used as the reset means and the anti-phase pulse is applied to each of them. It does not matter even if it has a structure to which is applied. Further, the reset means may be an NMOS transistor, and the structure to which the anti-phase pulse is applied may be a PMOS transistor, or vice versa.

[Third Embodiment] A resetting means according to a third embodiment of the present invention will be described in detail with reference to FIG. FIG.
Similar to FIGS. 3 and 5, shows an example of a detailed diagram from the capacitor C (202) corresponding to the multi-input terminal of FIG. 1 through the commonly connected terminal 200 to the output 211 of the sense amplifier 205. Here, as the sense amplifier 205, not the mere inverter 206 shown in the first and second embodiments, but the input and output of the inverter 206 are reset means (switch).
It is connected through. The NMOS transistor indicated by 400 is the reset means, and when this transistor is on, the input / output terminal 2 of the inverter 206 is
00 is common and is exactly equal to the logic inversion voltage of the inverter 206. In this state, if the input / output terminal of the inverter 206 is cut off, it changes depending on the actual input value Q, that is, a sense amplifier that is very sensitive to a minute voltage change generated at the terminal 200 to which the capacitance is commonly connected. Become.

The structure 404 is the source / drain common NMOS transistor described in the second embodiment, and the drain-gate capacitance and the source-gate capacitance overlap in parallel, and equivalently has the same capacitance as the NMOS 400. A reverse phase pulse φRES (bar) having a phase opposite to that of the pulse to the reset means is applied to the gate electrode. By using such a structure, the positive-phase control pulse φRES and the control pulse φRES (bar) of the opposite phase are applied to the respective NMOS transistors, so that the voltage change due to the capacitance when each pulse is turned on / off is canceled. It is possible to make the input voltage of the inverter floating in an accurate state by the logical inversion voltage of the inverter, resulting in higher sensitivity and faster response, which also contributes to lower power consumption. Needless to say, a great effect can be obtained. Here, in this embodiment, two NMOS transistors are used as the reset means, and an NMOS is used as the structure to which the antiphase pulse is applied.
Although an example in which one transistor is connected is shown,
Needless to say, it is not limited to this.
Of course, another structure described in the first and second embodiments may be used. It goes without saying that the circuit configuration for connecting the reset means and the structure for inputting the reset means drive pulse and the anti-phase pulse to the same terminal is not limited to the configurations shown in the present embodiment and the first and second embodiments.

[Fourth Embodiment] A fourth embodiment according to the present invention will be described in detail with reference to FIGS. This embodiment will be described in detail with reference to a reset means that has a switch means between multiple input terminals and each capacitance and that resets the voltage between the capacitance and the sense amplifier 205. In FIG. 9, Q1 to Qn are input terminals and are n multi-input terminals. 201 is a reset switch, 202 is a capacitor,
203 is a signal transfer switch, 205 is a sense amplifier, 2
Reference numeral 06 is an inverter in the sense amplifier, 204 is a second inverter in the sense amplifier, 207 is a second reset switch for resetting the inverter, 208 is a reset power supply, 210 is a second reset power supply, and 211 is an output terminal. , 209 are capacitances that schematically represent the parasitic capacitances attached to the commonly connected ends of the capacitors 202, and the capacitance 209 is not limited to this.

FIG. 10 is a timing diagram showing the operation of this embodiment. The operation of this embodiment will be described with reference to FIG.
One end of 02 is reset to the reset power supply 208. For example, if the power supply voltage is a 5V system, the reset voltage is 2.5V, which is almost half of the reset voltage. The reset voltage is not limited to this, and another voltage may be used. At this time, the input terminal 200 of the inverter 206 in the sense amplifier 205 is reset to the second reset power supply 210 by making the reset switch 207 conductive almost at the same time, but there is no restriction that this timing must be the same. Needless to say. At this time, in this example, a value near the logic inversion voltage at which the output of the inverter 206 is inverted is selected as the reset voltage. When the reset pulse φRES is turned off, both ends of the capacitor 202 are held at their respective reset potentials. Next, when the transfer switch 203 is turned on by the transfer pulse φT, the signal is transferred to one end of the capacitor 202, and the potential of the one end of the capacitor 202 is 0, which corresponds to a low level from the reset voltage of 2.5V, for example.
It changes to V or 5V corresponding to a high level. After that, the operation is the same as that described in the first embodiment, and the output 21 of the sense amplifier 205 is output according to the input signals to the multi-input terminals.
A high-level or low-level output signal is output to 1.

FIG. 11 is a diagram showing a detailed example from the multi-input terminal shown in FIG. 9 to the capacitor C (202). Figure 9
7, the same reference numerals as those in FIG. 7 have the same functions, and detailed description thereof will be omitted. In the figure, 202 is a capacitor corresponding to multiple input terminals, 203 is a signal transfer switch for transferring an input signal to the capacitor 202 corresponding to multiple input terminals, 2
Reference numeral 08 denotes a reset power supply that resets the input side of the capacitor 202 corresponding to the multiple input terminals, and 212 denotes a capacitance C0 'such as a parasitic capacitance at the input side terminal of the capacitance 202. Further, as a means for resetting the terminal between the signal transfer switch 203 and the capacitor 202 by the power supply 208, the NMOS divided into two parts.
Transistor 407 and this NMOS transistor 40
7 and a series-structured NMOS transistor 408 is used. The drive pulse φRES for resetting is input to the gates of the two NMOS transistors 407.

Since the NMOS transistor 407 is used here, for example, the signal pulse φRES is input at the timing shown in FIG. 10, the terminal between the switch and the capacitor is reset by the power supply 210 between the high level, and then the low level. As a level, the terminal between the switch and the capacitor is set in a floating state. On the other hand, the φRES signal and the φRES (bar) of the antiphase pulse are input to the structure body 408. This structure has a semiconductor impurity layer of a conductivity type different from that of the semiconductor substrate formed on the semiconductor substrate with electrodes for applying a reverse phase pulse sandwiched therebetween, and the semiconductor impurity layers are electrically and commonly connected to each other. It is connected to the input side of 202.

In FIG. 11, this structure is connected to the terminal between the switch and the capacitor with the drain and source of the NMOS transistor as a common terminal. By connecting this structure, the overlapping capacitance of the gate and drain (on the side of the commonly connected terminal 200) of the transistor, which occurs when φRES turns off the NMOS transistor, and 212
It is possible to cancel the voltage change of the terminal between the switch and the capacitance due to the capacitance division with the capacitance C0 ′ shown in FIG. 3, and it is possible to more accurately reset the terminal between the switch and the capacitance to the potential of the reset power supply 208. . Therefore, it is possible to more accurately set the absolute value of the minute voltage change caused by the capacitance division to the commonly-connected terminal 200 on the opposite side through the capacitor 202, and thus the sensitivity is increased, which enables a high-speed response. Therefore, it is possible to obtain a great effect that it can also contribute to lower power consumption.

The structure and reset means used here are not limited to those of this embodiment.
This is as described in 3 above. Also, it is obvious that the signal transfer switch should not be particularly limited.

Further, the structure shown in FIG. 12 is also included in the present invention. In FIG. 12, the switch means 230 is provided between the multi-input terminal and the capacitor, but it can be used as the reset means as well as the switch means. That is, the period in the reset state in which the input is set to the reset potential and the switch is opened and the period in which the input IN is changed to the information signal and the switch is opened are divided in time series, and the switch 230 may be set to high / low in the meantime. The timing diagram is shown in. In this case as well, in order to reset the input terminal side of the capacitor, the structure body 231 for inputting the pulse of the reset means and the anti-phase pulse can be connected. Structure 2
The configuration of 31 is similar to that of the circuit shown in FIG.
It is needless to say that the transistors are connected in series and the operation is as described above, and such a configuration is also included in the present invention.

[Fifth Embodiment] A fifth embodiment according to the present invention will be described with reference to FIGS.

FIG. 14 is almost the same as FIG. 9, but 2
The reset potential of 08 is variable. Reset potential 2
When 08 is fixed (V₀Of input value Q and fixed value
Difference (Q-V₀) Minute signal change is divided into
The signal is propagated to the commonly connected terminals 200. On the other hand, the input signal
If a reverse-phase signal of the signal Q value is used as the reset potential,
The signal change can have full amplitude at the power supply voltage.
For example V_DD= 5V, V ₀= 2.5V, reset
When the electric potential is fixed, the signal change is 5-2.5 = 2.5V
Or 0-2.5 = -2.5V and ± 2.5V
In contrast, when the reset potential is the opposite phase signal of the input signal,
In this case, the signal change is 5-0 = 5V or 0-5 = -5
It becomes ± 5V at V.

In such a case, the reset means 201 must be a switch that passes both the power supply voltage and 0 V, and such a switch is an NMOSFE.
A transmission type MOSFET having both T and PMOSFETs is well known.

When the feed-through characteristic of this transmission type MOSFET was measured, it was found that there was a dependency on the reset potential value. The experimental value is shown by the curve A in the graph of reset voltage vs. feedthrough amount in FIG. 15A, and the circuit diagram at that time is shown in FIG.
It is shown in the circuit diagram A of FIG. The larger the reset potential is on the positive side, the more positive feedthrough the feedthrough by the PMOSFET occurs, and the closer the reset potential is to 0, the more negative feedthrough the feedthrough by the NMOSFET 410 occurs. PMOSFET
The feedthrough by 409 becomes more remarkable as the reset voltage approaches 5V.

That is, a transmission type MOS
In order to suppress the feedthrough with the FET, it is effective when the reset potential is fixed, but when the reset potential is variable as in this embodiment, the PMOSFET and the NMOSF are provided.
It is effective to match the structure to which the antiphase pulse is applied to each ET. The result is shown in a straight line B of FIG. 15A, and a concrete circuit diagram thereof is shown in a circuit diagram B of FIG. 15B. Here, in the circuit diagram B, two NMOSFETs 413 and one structure NMOSFET 4 are provided on the input side of the capacitor 202.
14 and two PMOSFETs 411 and one structure PMOSFET 412 are connected to each other, and the reset voltage 20
8 is being supplied.

By adopting such a configuration, φRE
Between the switch and the capacitance due to capacitance division between the overlapping capacitance of the gate and drain (commonly connected terminal side) of the transistor and the capacitance 212 such as the parasitic capacitance on the input side of the capacitance 202, which occurs when S turns off the NMOS transistor. It becomes possible to cancel the voltage change at the terminal of
It is possible to more accurately reset the terminal between the switch and the capacitor to the potential of 8. Therefore, it is possible to more accurately set the absolute value of the minute voltage change caused by the capacitance division to the commonly-connected terminal 200 on the opposite side through the capacitor 202, and thus the sensitivity is increased, which enables a high-speed response. Can contribute to lower power consumption,
A great effect can be obtained.

The structure and reset means used here are not limited to those of this embodiment.
This is as described in 3 above. Also, it is obvious that the signal transfer switch should not be particularly limited. Further, it goes without saying that the same can be said when the transmission type MOSFET is used for resetting the terminals 200 commonly connected to the capacitors shown in the first to third embodiments.

On the other hand, it goes without saying that the division of the MOSFET of the reset means is exactly the same for the transmission type MOSFET.

[Sixth Embodiment] A sixth embodiment of the present invention will be described with reference to FIGS. 16 and 17
Both show an example of a detailed view from the input terminal to the capacitance C (202) in FIG. 7. In the example of FIGS. 16 and 17, 4
Regarding the pulse input to each of the NMOS transistor which is the reset means indicated by 07 and the structure which is indicated by 408, the pulse φRES to the reset means is the reverse phase pulse φR.
When it is later than ES (bar), the NMOS transistor 407 which is the reset means is in the ON state during the delay, so that the terminal between the switch and the capacitor is reset even if the negative-phase pulse φRES (bar) changes. It is the potential of the power supply 208. Therefore, the effect of the structure shown at 408 is reduced.

In FIG. 16, φRES (bar) is φRE.
From the input of S through the inverter 409, the inverter 4
Inputting is delayed with a slight time which is a delay of signal transmission at 09. By doing so, it is possible to bring out the effect of the structure of 408 without waste.

In FIG. 17, the reverse phase pulse φRE is set so as to be almost the same timing through a plurality of inverters 410.
S (bar) and pulse φRES are input. At this time, the voltage change is suppressed to a small level even while φRES (bar) and φRES are changing. Such an example is not limited to the description of this embodiment, and the same applies to the commonly connected terminals 200 shown in the first to third embodiments. Further, it goes without saying that the structure including the other structures described in Examples 1 to 5 is not limited to the structure according to the present embodiment.

[Embodiment 7] Next, an example in which the above semiconductor device is applied to a correlation operation circuit will be described as a seventh embodiment with reference to FIG. In FIG. 18, 7
21-A, 21-B, and 21-C having two input terminals are majority operation circuit blocks, 22 is an inverter, and 23 is a comparator. Reference numerals 24 and 25 denote input terminal groups, to which signals similar to the seven input signals input to the majority arithmetic operation circuit block 21-A are input. 26, 27 and 28 are input terminals for inputting the output signal from the majority arithmetic circuit block in the previous stage, and 29, 30 and 31 are input terminals 26, 27 and 28, where C is the capacitance connected to the normal input terminals. Capacitance values 4C, 2C, and 4C connected corresponding to the above are shown.

In FIG. 18, the input signals are first input to the comparator 23 together with the respective correlation coefficients 33. The comparator 23 outputs HIGH LEVEL if the respective input signals and the correlation coefficient 33 match, and outputs LOW LEVEL if they do not match. The output of the comparator 23 is input to the majority arithmetic operation circuit blocks 21-A to 21-C. For example, when the output of the comparator 23 is input to the 7-input majority calculation circuit block 21-A, if the number of HIGH LEVELs is a majority, that is, if 4 or more of the 7 inputs are HIGH LEVEL, the majority calculation circuit HIGH LEVEL is output from the block 21-A. This output state is shown in S3 of the chart of FIG.

Similarly, for example, in the 11-input majority decision operation circuit block 21-B of 7 inputs and 4C equivalent to 4 inputs of the input terminal 26, HIGH LEVEL is output when 6 or more inputs are HIGH LEVEL. It This output state is shown in Figure 1.
It is shown in S2 of the chart of FIG. In addition, 7 inputs and 4C equivalent to 4 inputs of the input terminal 28, 2 equivalent to 2 inputs of the input terminal 27
Majority operation circuit block 21 with a total of 13 inputs by C
In C, when 7 or more inputs are HIGH LEVEL, HIGH L
EVEL is output. This output state is S1 in the chart of FIG.
Shown in

More specifically, the output values of the 7-input majority decision operation circuit block are shown for each number of HIGH LEVEL inputs, as shown in S3 of FIG. Next, as shown in FIG. 18, 7-input majority decision operation circuit block 21-A
The polarity of the output of the above is inverted by the inverter 22 and applied to the weighting input terminal 26 of the majority arithmetic operation circuit block 21-B.

The circuit configuration of the majority decision operation circuit block 21-B is shown in FIG. This is a circuit with weighting. In FIG. 20, reference numeral 29 is a capacitor having a capacitance value approximately four times that of the capacitor C connected to another input terminal path. In the circuit of FIG. 20, assuming that the capacitor value connected to the input terminal path is C, 11 Cs are commonly connected, and a signal from the weighting input terminal is applied to 4Cs of them, and the other 7Cs are applied to the other 7 terminals. Is an 11-input majority operation circuit configured so that the same signal as that input to the majority operation circuit block 21-A is applied. For example, when 4 or more of 7 inputs are HIGH LEVEL, LOW LEVEL is applied to the weighting input terminals as described above. Furthermore, if 6 or more of the 7 inputs among the signals applied to the input terminals other than the weighted input terminals are HIGH LEVEL, the 11-input majority calculation circuit judges that the total is a majority and outputs HIGH LEVEL. . If the number of inputs is 4 or more and 5 or less among 7 inputs, LOW LEVEL is output without reaching the majority. On the other hand, if 3 or less of 7 inputs are HIGH LEVEL, HIGH LEVEL is applied to the weighted input terminal. When more than 2 inputs and less than 3 inputs are HIGH LEVEL among 7 inputs, 4 + 2 or 4 + 3 is 6 or more and it is judged as a majority and HIGH LEVEL is output. Also, 1 input or less is HIGH L
If EVEL, 4 + 0 or 4 + 1 is 6 or less and LOW
LEVEL is output. Majority calculation circuit block 21-B
When the output value of is shown for each number of HIGH LEVEL of input, it becomes like S2 of the chart 1 of FIG.

According to the present invention, the control pulse φ in FIG.
By using the NMOS or PMOS and each structure described in the first to sixth embodiments for the switch unit operated by RES, the accuracy and speed of data and the reduction of the overall circuit size can be achieved.

Also in the majority arithmetic circuit block 21-C, the majority arithmetic circuit 21-A is connected to the two weighting terminals having the capacitance value 4C which is four times that of the input terminal 28 and the capacitance value 2C which is twice that of the input terminal 27. , Majority calculation circuit 21-B
By applying an inverted signal of the output of the above and operating it, the output as shown in S1 of the chart 1 of FIG. 20 is obtained. With this circuit configuration, as shown in FIG. 20, it is possible to convert the number of inputs having the same correlation coefficient as the signal among the plurality of inputs into a three-digit binary number and output the binary number.

FIG. 21 shows a schematic circuit diagram of the majority operation circuit block. This is a circuit without weighting. In FIG. 21, 41 is a reset switch, 42 is a capacitor, 43 is a signal transfer switch, 205 is a sense amplifier, 46 is a first inverter in the sense amplifier 205, 44 is a second inverter in the sense amplifier 205,
47 is a second reset switch for resetting the input end of the inverter 46, 48 is a reset power supply, 50 is a second reset power supply, 51 is an output terminal, 49 is a parasitic capacitance attached to one end of the capacitor 42 connected in common However, the present invention is not limited to this.

FIG. 22 is a timing chart for explaining the operation timing of the majority arithmetic circuit of this embodiment. The operation will be described with reference to FIG.
Reset one end of 2. For example, when the power supply voltage is a 5V system, the reset voltage is 2.5V which is almost half of that. The reset voltage is not limited to this and may be another voltage. At this time, almost simultaneously, the input end of the inverter 46 in the sense amplifier 205 is reset by making the reset switch 47 conductive. At this time, a value near the logic inversion voltage at which the output of the inverter 46 is inverted is selected as the reset voltage.

Next, when the reset pulse φRES is turned off, both ends of the capacitor 42 are held at the respective reset potentials. Next, by the transfer pulse φT, the transfer switch 43
When is turned on, the input signal is transferred to one end of the capacitor 42, and the potential of one end of the capacitor 42 is, for example, from the reset voltage of 2.5V to 0V corresponding to LOW LEVEL, or
It changes to 5V corresponding to HIGH LEVEL. Assuming that the capacitance of the capacitor 42 is Ci and the capacitance value of the parasitic capacitance is CO, assuming that N capacitors 42 are connected in parallel, one end of the capacitors 42 connected in common has a capacitance for one input. Due to the division, (Ci × V) / (Co + N × Ci) [V] (Ci × 2.5) / (Co + N × Ci) [V] changes from near the logic inversion voltage of the inverter 46.

When the input terminal voltage of the inverter 46 changes from the logic inversion voltage, the output terminal voltage of the inverter 46 inverts accordingly. When a signal is input to each of the N inputs, the capacity division output N is input to the input terminal of the inverter 46.
The sum of the numbers is entered. After all, HIGH LEV out of N inputs
If the number of EL signals is a majority, the input terminal of the inverter 46 shifts to a potential higher than the logic inversion voltage, and the sense amplifier 2
The output terminal 51 of 05 outputs HIGH LEVEL, and if the number of LOW LEVEL signals is a majority, LOW LEVEL is output. With the above configuration, the circuit of FIG. 21 functions as a majority operation circuit that outputs a logical value occupying the majority of the plurality of inputs. That is, this embodiment also functions as a majority calculation circuit. As described above, according to the present invention, FIG.
In the middle, a switch 41 operated by a control pulse φRES,
By using the NMOS or PMOS and each structure described in the first to sixth embodiments for 47 or the like, accuracy and speed of data of the majority operation circuit and reduction in overall circuit scale can be achieved.

[Eighth Embodiment] With respect to the eighth embodiment,
This will be described with reference to FIGS. 23 and 24. This embodiment is a 3-bit precision analog / digital converter (hereinafter referred to as an AD converter) using the present invention. Particularly, when the reset means is used for the other input terminal portion of each operation block and the input portion of the sense amplifier, it is preferable to apply the reset means described above. In FIG. 23, 121-A,
Reference numerals -B and -C denote 1-input, 2-input and 3-input arithmetic circuit blocks, respectively, and 122 denotes an inverter. 123, 12
4, 125 are input terminals for inputting the output signal from the arithmetic circuit block of the previous stage, 126, 127, 128 are 123, 12 when the capacitance connected to the normal input terminals is C.
Capacitance values C / 2, C / connected corresponding to 4, 125
2 shows C / 4. 129 is an analog input terminal,
Reference numeral 130 is a set input terminal, and 131 and 132 indicate capacitance values C / 4 and C / 8, which are respectively connected correspondingly. Further, S1, S2 and S3 are digital output signal terminals.

Here, the case of using a 5V power supply in this embodiment will be described. In FIG. 23, first, the sense amplifier inputs in the arithmetic circuit blocks 121-A to 121-C are reset to 0V for the arithmetic circuit blocks 121-A and about 2.5V for the arithmetic circuit blocks 121-B and C. Further, the input sides of the signal calculation terminals 202 of the signal input terminals 123, 124, 125 and the set input terminal 130 are reset to 5V. At this time, the signal input terminal 129 is 0
V. Next, when the set input terminal 130 is set to 0V and the input voltage of the input terminal 129 is changed from 0V to the analog signal voltage, when the analog input signal becomes approximately 2.5V or more in the arithmetic circuit block 121-A, The sense amplifier input voltage in the arithmetic circuit block 121-A exceeds the logic inversion voltage (here, 2.5V is assumed), and HIGH LEVEL is output. The result is shown in S3 of the chart of FIG.

When the analog input signal is 2.5 V or more, the input terminal 123 changes from the reset potential of 5 V to 0 V. At this time, the potential change at the sense amplifier input terminal in the arithmetic circuit block 121-B is expressed by the following equation when the analog input signal voltage is VA. {C × VA− (C / 2) × 5− (C / 4) × 5} / (C + C / 2 + C / 4) [V] From this expression, the arithmetic circuit block 121-B has an analog signal voltage VA of 3 It can be seen that HIGH LEVEL is output when the voltage is 0.75V or more, and LOW LEVEL is output when the voltage is 2.5V or more and less than 3.75V. The result is shown in S2 of FIG.

Similarly, the output of the arithmetic circuit block 121-C is as shown in S1 of FIG.

According to the present embodiment, as shown in the chart of FIG. 24, the AD converter for converting the analog signal voltage into the 3-bit digital signal and outputting the digital signal is very small in scale, and the operation speed is high. It can also be realized by reducing the voltage.

In this embodiment, the 3-bit AD converter has been described, but the present invention is not limited to this, and can be easily expanded to more bits.

In the present embodiment, an example of a flash type AD converter using a capacitor has been described, but the present invention is not limited to this method, and for example, a signal input to a resistor string and a reference signal are compared by a comparator. Needless to say, even if the present invention is applied to the encoder circuit section of the AD converter by encoding the result with an encoder, the same effect as described above can be obtained.

As described above, in the circuit block in which one terminal of the capacitance means corresponding to each of the multi-input terminals is connected in common and is input to the sense amplifier, the minimum capacitance among the capacitances connected to the multi-input terminals is obtained. When the capacity is C, the total of the capacity means is an odd multiple of C.

Incidentally, in the case of the correlation circuit, when it does not have a control input terminal, it is configured from the minimum value, and when it has a control input terminal, it will be described in the seventh embodiment shown in FIG. 18, for example. As described above, the capacitances connected to the control input terminals are even, that is, 2C and 4C, and the sum of the capacitances with the odd input signal terminals is approximately an odd multiple of C. With such a configuration, it is possible to clearly distinguish the magnitude from the desired reference value and improve the calculation accuracy.

Although the above description has described the correlation circuit,
The binary DA converter has a minimum bit LSB signal input capacity of C
Then, the next bit is 2C, and the next bit is 4C.
Then, the total capacitance of the multi-input terminals becomes almost an odd multiple of C, and highly accurate DA conversion can be realized.

Also for the AD converter, as described in the eighth embodiment shown in FIG. 23, it is clearly determined whether the analog signal level exceeds 1/2 or less than 1/2 of the full range. The number of divisions to be made is one of 1C in 121-A,
In 121-B, the number of divisions such as 1/4, 2/4, and 3/4 becomes an odd number of 3, and the total is 1 + 2 with C / 4 being the minimum value.
It becomes an odd multiple of + 4 = 7 times, and in the case of 121-C, C / 8 is the minimum value, and in C / 4, C / 2, and C that are doubled, 1 + 2 + 4 +
It is set to an odd multiple of 8 = 15.

With these configurations, particularly high-precision arithmetic operations can be performed. Therefore, arithmetic operations can be executed without providing an unnecessarily large capacity, and low power consumption and high-speed arithmetic operations are realized.

Further, although the correlation calculator and the AD converter have been described as examples above, the present invention is not limited to this, and is applied to various logic circuits such as a digital / analog conversion circuit, an addition circuit, a subtraction circuit and the like. However, it goes without saying that the same effect can be obtained.

In particular, when configuring a DA converter, the LSB is
When the capacity for inputting data is C, binary digital-analog conversion can be realized by multiplying by 2C, 4C, and 8C as the next higher bit becomes. In this case, the MOS-type source follower amplifier may receive the commonly connected capacitance terminals.

[Ninth Embodiment] FIG. 25 shows a ninth embodiment of the present invention. The ninth embodiment is one in which the technique of the present invention is fused with the conventional circuit technique to realize a motion detection chip for moving images and the like. In FIG. 25, 61 and 62 are a memory unit which is a storage device for respectively storing standard data and reference data, 63 is a correlation calculation unit, 64 is a control unit for controlling the entire chip, and 65 is a correlation calculation unit 63. A result addition calculation unit, 66 is a register unit that stores the minimum value of the addition result of the addition calculation unit 65, 67 is a comparison storage unit that stores the address of the comparator and the minimum value, and 68 is an output buffer and It is an output result storage unit. Input bus 6
A reference data string is input to 9 while a reference data string to be compared with the reference data string is input to the input bus 70. The memory units 61 and 62 are composed of SRAMs and are composed of normal CMOS circuits.

The data sent from the reference data memory unit 62 and the standard data memory unit 61 to the correlation operation of the correlation operation unit 63 is subjected to the correlation operation by the correlation operation circuit according to the present invention, so that it is a high-speed parallel processing. In addition to achieving extremely high speed, the number of elements was small, the chip size was small, and the cost was low. The correlation calculation result is scored (evaluated) for the correlation calculation by the addition calculation unit 65, and the result is compared with the register unit 66 in which the maximum correlation result before the correlation calculation (the added value is the minimum value) is stored. This is done in the storage unit 67. If the calculation result this time is smaller than the minimum value up to the last time,
The result is newly stored in the register unit 66, and if the result up to the previous time is small, the result is maintained. By performing such an operation, the maximum correlation result is always stored in the register unit 66, and after the calculation of all the data strings is completed, the result is output from the output bus 71 as, for example, a 16-bit signal.

The control unit 64 and the addition operation unit 6
5, the register unit 66, the comparison storage unit 67, and the output result storage unit 68 are composed of normal CMOS circuits this time, but the addition arithmetic unit 65 and the like in particular use the circuit structure including the reset means of the present invention. Accurate high gain operation of the sense amplifier is realized, and high speed processing is realized. As described above, not only high speed and low cost, but also the reset means is achieved accurately and at high speed, and the calculation is executed based on the capacity, so that the current consumption is small and the power can be reduced.
It is also suitable for portable devices such as mmVTR cameras.

[Tenth Embodiment] A tenth embodiment of the present invention will be described with reference to FIG. The tenth embodiment shows a chip configuration in which the technique of the present invention is integrated with an optical sensor (solid-state image sensor) to perform high-speed image processing before reading image data.

FIG. 26 (a) is a block diagram showing the overall structure of a chip to which the present invention is applied, and FIG. 26 (b) is a circuit diagram showing the structure of the pixel portion of the chip of the present invention.
(C) is a conceptual diagram explaining the operation contents of the chip to which the present invention is applied.

In the figure, 141 is a light receiving portion including a photoelectric conversion element, 143, 145, 147 and 149 are line memory portions, 144 and 148 are correlation calculation portions, and 150 is a calculation output portion. Further, in the light receiving unit 141 shown in FIG. 26B, 151 and 152 are optical signal output terminals 142 and 146.
Coupling capacitance means for connecting to the output bus line shown in 15
3 is a bipolar transistor, 154 is capacitance means connected to the base region of the bipolar transistor 153,
55 is a switch MOS transistor. The image data incident on the image data sensing unit 60 is photoelectrically converted in the base region of the bipolar transistor 153.

The output corresponding to the photoelectrically converted photocarriers is read out to the emitter of the bipolar transistor 153, and the potentials of the output bus lines 142 and 146 are set to the input accumulated charge signal via the coupling capacitance means 151 and 152. Push up. By the above operation, the addition result of the pixels in the vertical direction is read to the line memory 147, while the addition result of the pixels in the horizontal direction is read to the line memory 143.
This is because if a region (not shown in FIG. 26) in which the base potential of the bipolar transistor 153 is raised is selected via the capacitor 154 of the pixel portion by a decoder (not shown in FIG. 26) or the like, the X direction of any region of the sensing portion 160, the Y direction. The result of addition in the direction can be output.

For example, as shown in FIG. 26 (c), if an image as shown at 156 at time t ₁ and an image as shown at 157 at time t ₂ are input, the output results of addition in the Y direction are As indicated by 158, 159, image signals of the moving state of the illustrated car are obtained, and these data are stored in the line memories 147, 149 of FIG. 26A, respectively. Also in the case of the horizontal direction, the line memory 143,
145.

Data string output 1 of image signal of FIG. 26 (c)
As can be seen from 58 and 159, both data are shifted corresponding to the movement of the image, and the correlation calculation unit 148 calculates the shift amount, and similarly the correlation calculation unit 144 calculates the horizontal data. For example, the movement of an object in a two-dimensional plane can be detected by a very simple method.

The correlation calculation circuit according to the present invention can be applied to the correlation calculation sections 144 and 148 shown in FIG. 26, and the number of elements is smaller than that of the conventional circuit and can be arranged particularly in the sensor pixel pitch. Although the present configuration is based on the analog signal of the sensor, it goes without saying that the AD converter according to the present invention may be provided between the line memory section and the output bus line to support the digital correlation calculation.

Further, although the bipolar type has been described as the sensor element of the present invention, it is needless to say that the MOS type or the configuration of only the photodiode without providing the amplifying transistor is also effective.

Further, in the present embodiment, the correlation calculation between the data strings at different times is performed. However, if the X and Y projection results of a plurality of pattern data to be recognized are stored in one memory section, pattern recognition is performed. Can also be realized.

As described above, the following effects can be obtained by fusing the pixel input section and the correlation calculation circuit according to the present invention. (1) Rather than serially reading from a conventional sensor and performing post-processing, parallel and batch-read data are processed in parallel, so that high-speed motion detection and pattern recognition processing can be realized. (2) A one-chip semiconductor device including a sensor can be configured,
Since image processing can be realized without increasing the number of peripheral circuits, the following high-performance products with a small circuit scale and low cost can be realized. That is, (a) a control device for directing the TV screen toward the user, (b) a control device for directing the wind direction of the air conditioner toward the user, (c) a tracking control device for the 8 mm VTR camera, (d) a label recognition device at the factory, ( The present invention can be applied to e) an automatic human recognition acceptance robot, (f) an inter-vehicle distance control device, and the like.

The fusion with the image input unit has been described above, but it goes without saying that it is effective not only for image data but also for processing such as voice recognition.

[0106]

As described above, according to the present invention, a circuit for performing parallel operation on a multi-variable signal can be configured with a smaller number of transistors as compared with an ordinary logic circuit, and high sensitivity to a minute signal can be achieved. Therefore, there is an effect that the calculation speed can be increased and the power consumption can be reduced.

Particularly, in the present semiconductor device in which a multi-input terminal, a capacitance corresponding to the multi-input terminal, and the other of the capacitances are commonly connected and input to the sense amplifier, the input portion of the sense amplifier, and the input portion of the capacitance. In addition, by minimizing the effect of the reset pulse on and off, it is possible to obtain a highly sensitive and accurate high-speed data output without shortening the reset time and affecting the signal without noise mixing. As a result, it is possible to realize a small circuit scale, high-speed calculation, and low power consumption.

Further, the circuit for performing parallel operation by the present semiconductor device can be configured with a smaller number of transistors as compared with a normal CM0S type logic circuit, and high sensitivity to a minute signal can be achieved.

Further, by applying the present invention to a semiconductor circuit using this semiconductor device, a correlation operation circuit, an A / D converter, a D / A converter, and a signal processing system using these,
It is possible to reduce the circuit scale, improve the operation speed, reduce the power consumption, and reduce the manufacturing cost and the manufacturing yield.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment according to the present invention.

FIG. 2 is a timing diagram for explaining the operation of FIG.

FIG. 3 is a circuit diagram showing in detail from a capacitance C of FIG. 1 to a sense amplifier output.

FIG. 4 is a layout diagram of the reset MOSFET of FIG. 1.

FIG. 5 is a circuit diagram showing in detail from the capacitance C to the output of the sense amplifier when the PMOS transistor is used in FIG.

FIG. 6 is a circuit diagram showing an embodiment according to the present invention.

FIG. 7 is a diagram showing an overlapping capacitance between a gate and a drain.

FIG. 8 is a circuit diagram showing an embodiment according to the present invention.

FIG. 9 is a circuit diagram showing an embodiment according to the present invention.

FIG. 10 is a timing diagram for explaining the operation of FIG.

11 is a circuit diagram showing in detail from the input terminal to the capacitance C of FIG.

FIG. 12 is a circuit diagram showing a modification of FIG.

13 is a diagram showing the operation timing of FIG.

FIG. 14 is a circuit diagram showing an embodiment according to the present invention.

FIG. 15 is a graph and a circuit diagram for explaining an example according to the present invention.

FIG. 16 is a circuit diagram showing an embodiment according to the present invention.

FIG. 17 is a circuit diagram showing an embodiment according to the present invention.

FIG. 18 is a circuit diagram showing an embodiment according to the present invention.

19 is a diagram showing the relationship between the input and output of the correlator in FIG.

20 is a circuit diagram showing a majority operation circuit block 21-B of FIG.

21 is a circuit diagram showing a majority decision operation circuit block 21-A of FIG. 18. FIG.

22 is a diagram showing the operation timing of FIG. 21. FIG.

FIG. 23 is a circuit diagram showing an embodiment according to the present invention.

24 is a diagram showing a relationship between an analog input signal and a digital output signal of the A / D converter in FIG.

FIG. 25 is a block diagram showing an embodiment according to the present invention.

FIG. 26 is a block diagram and a conceptual diagram showing an embodiment according to the present invention.

FIG. 27 is a block diagram showing a conventional solid-state imaging device.

[Explanation of symbols]

1,6 Source region 2,5,7 Drain region 3,4 Gate electrode 8,9,10,11,12 Contact part 13 Insulating film 14 Gate electrode 15 Metal 16 Si substrate 21 Majority operation circuit block 22 Inverter 23 Comparator 61 , 62 memory unit 63 correlation calculation unit 64 control unit 65 addition calculation unit 66 register unit 121 calculation circuit block 122 inverter 200 commonly connected terminal 201, 207 switch 202, 209, 212, 401 capacitance 203 signal transfer switch 204, 206, 409 inverter 205 sense amplifier 208, 210 reset power supply 211 output terminal 221 NAND circuit 230 signal transfer switch and reset switch 231 structure 400, 405, 407 NMOS transistor 402, 406 PMO S-transistors 403, 404, 408 NM with common source and drain
OS transistor

Claims (23)

[Claims] 1. A semiconductor device in which capacitors are connected to multiple input terminals, and one terminal of each capacitor is commonly connected to be input to a sense amplifier, comprising means for resetting the commonly connected capacitor terminals. A structure in which the reset means is a MOSFET and is divided into two or more MOSFETs, and a structure for inputting a pulse having a phase opposite to the drive pulse input to the MOSFET of the reset means is connected to the capacitance terminal A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein
The structure has a semiconductor impurity layer of a conductivity type different from that of the semiconductor substrate, which is formed on a semiconductor substrate with electrodes for applying the anti-phase pulse sandwiched therebetween, and the semiconductor impurity layers are both electrically and common to each other. A semiconductor device characterized by being connected to a connected capacitance terminal. 3. The semiconductor device according to claim 2,
The semiconductor device, wherein the sum of the gate capacitances of the MOSFETs of the reset means is approximately twice the gate capacitance of the structure. 4. The semiconductor device according to claim 2,
The semiconductor device, wherein the sum of the gate widths W of the MOSFETs of the reset means is approximately twice the gate width of the structure. 5. The semiconductor device according to claim 2,
The MOSFET of the reset means is the same type MO
A semiconductor device characterized in that it is divided into two SFETs, and the type of the semiconductor impurity layer of the structure is the same as the type used for the reset means. 6. The semiconductor device according to claim 5,
2. A semiconductor device characterized in that the gate width W and the gate length L of the MOSFET of the reset means divided into two are substantially equal, and the gate width and the gate length of the structure are also substantially equal. 7. A capacitor is connected to each of the multiple input terminals,
In a semiconductor device in which one terminal of each of the capacitors is commonly connected and input to a sense amplifier, a switch unit is provided between the multi-input terminal and each of the capacitors, and between the switch unit and the capacitor. A reset means for resetting the voltage, wherein the reset means is M
A structure which is an OSFET and is divided into two or more MOSFETs and which inputs a pulse having a phase opposite to the drive pulse of the reset means is connected to a terminal between the switch means and the capacitor. Semiconductor device. 8. The semiconductor device according to claim 7,
The structure has a semiconductor impurity layer of a conductivity type different from that of the semiconductor substrate formed on the semiconductor substrate with an electrode for applying the anti-phase pulse sandwiched therebetween, and a semiconductor impurity layer of a conductivity type different from the substrate, A semiconductor device, both of which are electrically connected to a capacitance terminal on the input terminal side. 9. The semiconductor device according to claim 8, wherein
The semiconductor device, wherein the sum of the gate capacitances of the MOSFETs of the reset means is approximately twice the gate capacitance of the structure. 10. The semiconductor device according to claim 8, wherein the sum of the gate widths W of the MOSFETs of the reset means is approximately twice the gate width of the structure. 11. The semiconductor device according to claim 10, wherein the MOSFET of the reset means is divided into two MOSFETs of the same type, and the type of the semiconductor impurity layer of the structure is also used for the reset means. A semiconductor device characterized by being equal to. 12. The semiconductor device according to claim 11, wherein the MOSFET of the reset means divided into two has a gate width W and a gate length L substantially equal to each other, and a gate width and a gate length of the structure are substantially equal to each other. Characteristic semiconductor device. 13. The semiconductor device according to claim 1, wherein the negative phase pulse rises / falls at the same time as or slower than the drive pulse. 14. The semiconductor device according to claim 1, wherein an input terminal of the drive pulse of the reset means is connected to an input terminal of a reverse phase pulse to the structure through a circuit including an inverter circuit. A semiconductor device characterized in that 15. The semiconductor device according to claim 14, wherein the inverter circuit constitutes a delay circuit. 16. A plurality of semiconductor devices according to claim 1 or 7, wherein a plurality of the semiconductor devices are provided, and an output of the first semiconductor device and / or an inverted output of the semiconductor device is a second output. A semiconductor circuit for inputting to the semiconductor device. 17. A semiconductor circuit using the semiconductor device according to claim 1, wherein when a minimum capacitance of the capacitance means corresponding to the multiple input terminals is C, the capacitance of the capacitance means commonly connected is set. A semiconductor circuit, wherein a total capacitance value is approximately an odd multiple of the minimum capacitance C. 18. A correlation calculation device for performing a correlation calculation using the semiconductor circuit according to claim 17. 19. An A / D converter including the semiconductor device according to claim 1 or 7, wherein an analog signal is input to the semiconductor device and a digital signal corresponding to the analog signal is output. An A / D converter characterized by: 20. A D / A converter including the semiconductor device according to claim 1 or 7, wherein a digital signal is input to the semiconductor device and an analog signal corresponding to the digital signal is output. D / A converter characterized by: 21. The correlation calculation device according to claim 18, the A / D converter according to claim 19, or the D / A converter according to claim 20. Signal processing system. 22. The signal processing system according to claim 21, further comprising an image input device for inputting an image signal. 23. The signal processing system according to claim 21, further comprising a storage device that stores information.