JPH08204566A - A/d converter - Google Patents

Abstract

PURPOSE: To provide an A/D converter suitable for operation with a low supply voltage and a low power consumption. CONSTITUTION: The energy of an analog input signal is sampled by a first switch 101 and an electric charge storage means 103, and the energy stored in this means 103 is supplied to an oscillation means 104 as the supply energy by a second switch 102. The oscillation output of the oscillation means 104 is counted by a counting means 105, and the counted result is converted into a digital code corresponding to the analog input signal by a code conversion means 106. The digital output or the digital code is held during A/D conversion by a holding means 106. For the purpose of improving the precision, the code conversion means 106 may consist of the memory where conversion data can be changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more particularly to an A / D converter that can operate with a low power supply voltage and low power consumption.

[0002]

2. Description of the Related Art Recently, an A / D converter which can operate with a low power supply voltage and a low power consumption has been required. However,
Since it is difficult to realize a high-gain operational amplifier (operational amplifier) at a low power supply voltage, an A / D that does not use an operational amplifier
A converter is required.

A comparatively low speed conventional A / D converter which does not use an operational amplifier will be described below.

As a conventional A / D converter of this type, an integration type (integration type) A / using voltage-time (VT) conversion is used.
There is a D converter. Most of them use an operational amplifier as an integrator. For example, a conventional discharge integration type A / D shown in FIG.
The converter (referred to as “first conventional example”) is a capacitor 501.
It is possible to charge an analog input signal at the same time, measure the time for discharging by the constant current source 502, perform A / D conversion, and perform A / D conversion without using an operational amplifier. More specifically,
After the first switch SW1 is closed to charge the capacitor 501 with the analog input signal, the charge accumulated in the capacitor 501 is closed by the second second switch SW2 to close the constant current source 5
While discharging through 01, the terminal voltage of the capacitor 501 is compared with the reference voltage Vref by the comparator 503, and the capacitor 50
When the terminal voltage of 1 drops below the reference voltage Vref, for example, the counting means 505 stops counting the output of the oscillating means 504, and the count value of the counting means 505 is output as a digital code via the holding means 506.

Further, another conventional A /
As a D converter, as shown in FIG. 6, voltage-frequency (V
-F) There is one using a conversion (referred to as "second conventional example").

Referring to FIG. 6, this A / D converter converts an analog input signal voltage into a frequency signal (pulse, sine wave, etc.) by a V-F converter 601, and outputs the signal from the V-F converter 601. By counting the output signals by the counting means 602, A / D
This is a conversion method. In this method, the VF converter 601 is configured without an operational amplifier,
A / D conversion can be performed without using an operational amplifier.

[0007]

However, in realizing an A / D converter that can operate with a low power supply voltage and low power consumption, the conventional A / D converter has the following problems. .

That is, in the first conventional example, since the electric charge charged in the capacitor 501 is unnecessarily discharged, energy loss cannot be avoided. Further, the comparator 503 is used to compare the terminal voltage of the capacitor 501 and the reference voltage Vref, and the power consumption increases accordingly.

Further, in the second conventional example, the V-F converter 601 itself operates independently of the analog input signal, and power consumption is always generated. The current path deteriorates the power efficiency of the entire A / D converter.

Therefore, an object of the present invention is to provide an A / D converter which can operate with a low power supply voltage and low power consumption.

[0011]

In order to achieve the above object, the present invention provides a charge storage means for sampling an analog input signal for charging, and an oscillating means to which power is supplied from the charge storage means. And an A / D converter configured to count the output of the oscillating means and digitally output the counting result.

In the present invention, code conversion means for converting the counting result into a desired digital code corresponding to the analog input signal may be provided.

In a preferred embodiment of the A / D converter of the present invention, an analog input terminal for inputting an analog input signal, a charge storage means, and an electrical connection between the analog input terminal and the charge storage means are provided. A first switch for controlling, an oscillating means, a second switch for controlling electrical connection between a power supply terminal of the oscillating means and the charge accumulating means, and a counting means for counting the number of oscillations of the oscillating means, Code conversion means for converting the counting result of the counting means into a desired code, holding means for holding the output of the counting means or code conversion means, a reset signal for initializing the oscillation means and the counting means, respectively, Timing control means for generating timing signals for opening and closing the first and second switches and a timing signal for the holding means;
An A / D converter is provided.

In a preferred embodiment of the present invention, the code conversion means is a rewritable memory means for changing the conversion data.

[0015]

According to the present invention having the above structure, the energy of the analog input signal is sampled by the first switch and the charge storage means, and the energy stored in the charge storage means by the second switch is oscillated as the power source energy. Supply to the means. As a result, the oscillation frequency depending on the energy of the analog input signal is obtained, and the energy of the input signal is converted into the oscillation energy with the minimum loss.

Therefore, in the present invention, the power consumption of the extra circuit is low, so that the power consumption is low. Further, as the oscillating means, not only the VF converter but also a normal oscillator or oscillating element having no input terminal can be used.

In general, the oscillating frequency of the oscillating means is not always proportional to the analog input signal. In this case, it is inconvenient to use the counting result of the counting means as it is as the output of the A / D converter. Therefore, code conversion means for converting the digital output, which is the counting result of the counting means, into a desired digital code is provided.

By the way, when operating at a low power supply voltage,
Variations in the characteristics of the circuit elements of the oscillation means and the charge storage means cannot be avoided. According to the present invention, since the conversion data of the code conversion means can be rewritten even after the manufacturing, it is possible to correct the variation of the characteristics and improve the accuracy of the A / D converter.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

[0020]

First Embodiment FIG. 1 shows an A / D according to a first embodiment of the present invention.
The structure of a converter is shown.

Referring to FIG. 1, a capacitor 103 serving as a charge storage means is charged with an analog input signal via a first switch 101 and sampling is performed. Then, the energy accumulated in the capacitor 103 is supplied to the oscillation means 104 via the second switch 102. That is, the capacitor 103
Is connected to the power supply terminal of the oscillating means 104 via the second switch 102.

Therefore, when the second switch 102 is closed (while it is in the ON state), the oscillating means 104 is operated by the capacitor 103.
Oscillates while consuming the energy, and stops the oscillation when the terminal voltage of the capacitor 103 becomes lower than the oscillation operation voltage of the oscillation means 104.

The oscillation signal output from the oscillation means 104 is counted by the counting means 105. The counting method in the counting means 105 includes [1] counting the number of oscillations within a predetermined time, [2] counting the number of oscillations until the oscillation is almost stopped, and the like.

As shown in FIG. 1, in this embodiment,
A code converting means / holding means 106 is provided after the counting means 105, and even if the analog input signal and the number of oscillations of the oscillation means 104 are not in a linear relationship, if they correspond to each other on a one-to-one basis, the code The conversion unit 106 can convert the digital output (oscillation number) of the counting unit 105 into a desired digital code corresponding to an analog signal and perform A / D conversion.

Oscillation means for the analog input signal
If the number of oscillations of 104 is proportional, the code converting means 106 is unnecessary.

The digital code output from the code conversion means 106 is held by the holding means so that the digital code output of the A / D converter does not change even when the next conversion operation starts.

In FIG. 1, the code conversion means 106
And the holding means for holding the digital code which is the output thereof are shown as one circuit block. Further, as shown in FIG. 1, in this embodiment, the holding means holds the output of the code converting means 106, but the number of oscillations of the oscillating means 104 is proportional to the analog input signal. In the case where the code converting means is not provided, the holding means holds the counting result of the counting means 105.

The oscillating means 104 and the counting means 105 are initialized for each conversion so that the state of the circuit in the previous conversion does not affect the next conversion.

The timing control means 107 includes timing signals T1 and T2 for controlling the opening and closing of the first switch 101 and the second switch 102, and an oscillating means so that each circuit portion performs an A / D conversion operation in synchronization. A timing signal T4 for resetting 104 and counting means 105 and a timing signal T3 for holding means 106 are generated.

Referring to FIG. 1, in the present embodiment, the oscillating means
The circuits other than 104, that is, the counting means 105, the code converting means / holding means 106, and the timing control means 107 are all supplied from an external power source, but these circuits are equal to or less than the oscillation operable voltage of the oscillation means 104. However, it is possible to operate by using the energy remaining in the charge storage means 103, and in this case, the power source of these circuits is supplied from the charge storage means 104 and A /
The power supply directly supplied to the D converter becomes unnecessary.

[0031]

[Embodiment 2] FIG. 2 shows the configuration of a second embodiment of the present invention.

With reference to FIG. 2, in this embodiment, a ring oscillator 204 in which CMOS inverters are connected in a 5-stage cascade form is used as the oscillation means. In this way, an oscillation circuit without an input terminal such as a ring oscillator can be used.

As shown in FIG. 2, in this embodiment, the power supply terminal of the ring oscillator 203 is connected to one terminal of the capacitor 203 via the second switch 202, and the capacitor 203
The first switch (SW1) 201 is charged by the analog input signal when closed, and the ring oscillator 204 oscillates using the terminal voltage of the capacitor 203 as the power supply voltage when the second switch (SW2) 202 is closed. . At that time, the ring oscillator 204 stops the oscillation when the terminal voltage of the capacitor 203 becomes equal to or lower than a predetermined voltage.

The counter 205 receives the oscillation output from the ring oscillator 204, counts the number of oscillations, and outputs the latch circuit 20.
6 holds the counting result of the counter 205. Encoder 20
6 converts the counting result into a predetermined code and outputs it as a digital code. The timing control circuit 207 is
ON / OFF switching signals for the first and second switches 201 and 202,
The reset signal (CNTR RESET) of the counter 205 and the latch clock (LAT CLK) of the latch circuit 206 are output to the respective circuits to control the timing of the A / D conversion operation.

In this embodiment, a sinusoidal oscillator circuit such as an LC oscillator circuit, an RC oscillator circuit, or a crystal oscillator circuit, or a pulse oscillator circuit such as a multivibrator or a blocking oscillator can be used as the oscillator circuit.

FIG. 3 shows a timing chart for explaining the operation of this embodiment.

Referring to FIG. 3, the first switch (SW1) 2
When 01 is on (closed), the second switch (SW2) 2
02 is turned off (open), and the capacitor 203 is charged.

When the second switch (SW2) 202 changes to the ON state (closed state), the reset signal (CNTR R
ESET) is released (transition to low level), the counter 205 counts the output (OSC OUTPUT) of the ring oscillator 204,
The latch circuit 206 activates the latch clock (LAT CLK) in synchronization with the transition of the ON / OFF switching signals of the first and second switches (SW1, SW2), and the latch circuit 206 latches the count value of the counter 205. Then, after the latch circuit 206 latches the count value of the counter 205, the reset signal (CNTR RESET) is set to a high level (active) to initialize the count value of the counter 205 to, for example, zero. In FIG. 3, the second switch (SW
2) Although the configuration is shown in which the number of oscillations is counted within a certain period in which 202 is activated, as described above, the number of oscillations until the oscillation of the oscillation circuit is almost stopped may be counted. Of course.

[0039]

Third Embodiment Next, a third embodiment of the present invention will be described. In this embodiment, the conversion data of the code converting means 106 in the first embodiment shown in FIG. 1 can be rewritten. With such a configuration, it becomes possible to absorb the variation in the characteristics when operating at a low power supply voltage.
The accuracy of the D converter can be improved.

In this embodiment, the code conversion means 106
A memory is preferably used as. Normally, a memory reads data from address information, but by inputting the count output of the counting means 105 as an address and outputting the data stored at that address as conversion data, the memory functions as the code conversion means 106. Function. A non-volatile memory or the like can be used as the memory.

As described above, in the present embodiment, by using the memory as the code conversion means 106, it is possible to easily correct the variation in characteristics by appropriately changing the conversion data even after manufacturing. Have.

FIG. 4 shows a specific example of the conversion process from the analog input signal to the output of the digital code in the A / D converter according to this embodiment. In FIG. 4, for simplicity, the A / D converter has a 3-bit configuration.

Referring to FIG. 4, for example, when the analog input voltage is 1.2 V and the number of oscillations of the oscillating means is 21 or 22 due to variations, the address of the memory as the code converting means. If data “111” is stored in “10101” address (21 address) and “10110” address (22 address), it will be converted into the desired digital code “111” regardless of the number of oscillations. Of the variation of
It is possible to improve the linearity of the A / D converter and realize a highly accurate A / D converter.

By connecting a plurality of A / D converters according to the present invention in parallel and operating a plurality of A / D converters in parallel in a time-sharing manner, the conversion speed when N pieces are in parallel is one A. / D
This is N times as high as that of the converter configuration, and high-speed conversion is possible.

Although the present invention has been described with reference to the above-described embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that the present invention includes various embodiments according to the principle of the present invention.

[0046]

As described above, the present invention can be operated at a low power supply voltage without using an operational amplifier and is configured to supply the energy of the analog input signal as the power supply energy of the oscillating means. Power loss can be minimized, and an A / D converter with low power consumption can be realized.

Further, according to the present invention, by using the rewritable storage means as the code conversion means, it is possible to change the conversion data even after the manufacture, and the variation of the characteristic is corrected to obtain the high precision A / A. A D converter can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 3 is a timing diagram illustrating the operation of the embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of an A / D conversion process in the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional A / D converter.

FIG. 6 is a block diagram showing another configuration of a conventional A / D converter.

[Explanation of symbols]

 101, 201 First switch 102, 202 Second switch 103, 203, 501 Capacitor (charge accumulating means) 104, 504 Oscillating means 105, 505, 602 Counting means 106 Code converting means / holding means 107, 207 Timing control means 204 Ring oscillator 205 Counter 206 Latch 208 Encoder 502 Constant current source 503 Comparator 506, 603 Holding means 601 V-F converter T1 to T4 Timing signal CNTR RRESET Reset signal LAT CLK Latch clock OSC OUTPUT Ring oscillator output

Claims (4)

[Claims] 1. A charge storage unit for sampling and charging an analog input signal, and an oscillating unit to which power is supplied from the charge storage unit. At least an output of the oscillating unit is counted to obtain a counting result. An A / D converter configured for digital output. 2. The A / D converter according to claim 1, further comprising code conversion means for converting the counting result into a desired digital code corresponding to the analog input signal. 3. An analog input terminal for inputting an analog input signal, a charge storage means, a first switch for controlling electrical connection between the analog input terminal and the charge storage means, an oscillating means, and the oscillation. A second switch for controlling the electrical connection between the power supply terminal of the means and the charge storage means, a counting means for counting the number of oscillations of the oscillating means, and a code for converting the counting result of the counting means into a desired code. Conversion means, holding means for holding the output of the counting means or the code conversion means, a reset signal for initializing the oscillation means and the counting means, and timing for opening and closing the first and second switches. A timing controller for generating a signal and a timing signal for the holding means, and an A / D converter. 4. The A / D converter according to claim 2, wherein the code conversion means includes a rewritable storage means capable of changing the conversion data.