JPH08205143A - Parallel decoding device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a novel parallel decoding device encoding device capable of performing parallel processing without using a shared memory system and decoding an encoded digital video signal. [Structure] A slice start code detector 31 for generating a slice start detection signal based on an encoded digital video signal, and the number of slice start codes of an encoded bit stream are counted, and in response thereto, A control unit 32 for generating a control signal,
A switching block 33 for dividing the video frame data into two subframes, and two first-in first-out (FIFO) buffers 34, 3 for storing the divided video frame data.
5 and an image processing device 40 for reproducing the original video image signal by expanding the encoded digital video signal.
And a frame former 80 for coupling the reproduced original video image signal.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to video image systems and, more particularly, to an improved video image decoding apparatus having two decoding modules for decompressing incoming compressed video image data in parallel.

[0002]

2. Description of the Prior Art Generally, in various electronic / electrical applications such as high definition television and video telephone systems, video signals need to be transmitted in digital form. When this video signal is represented in digital form, a considerable amount of digital data is generated. However, since the applicable frequency bandwidth of the normal transmission channel is limited, a video signal encoding device that compresses a considerable amount of digital data is required to transmit the video signal through the normal transmission channel. . Therefore, most video signal coding devices employ various compression techniques (or coding techniques) based on using or reducing spatial and / or temporal redundancy in the input video signal. Among various video compression techniques, a "hybrid coding technique", which is a combination of a statistical coding technique and a temporal and spatial compression technique, is known to be most effective.

Most hybrid coding techniques employ motion compensated DPCM (differential pulse code modulation), two-dimensional DCT (discrete cosine transform), DCT coefficient quantization and VLC (variable length coding). Motion-compensated DPCM determines the motion of an object between the current frame and the previous frame, predicts the current frame according to the motion of the object, and generates a difference signal that represents the difference between the current frame and the predicted frame. . Such a method is described in, for example, the article by Staffan Ericsson "Fixe
d and Adaptive Predictors for Hybrid Predictive / Tr
ansform Coding '', IEEE Transactions on Communicatio
ns, COM-33, No.12 (December 1985), Ninomiya and Ohtsu
ka, `` A Motion Compensated Interframe Coding Scheme
for Television Pictures '', IEEE Transactions on Com
munications, COM-30, No. 1 (January 1982).

The two-dimensional DCT reduces or removes spatial redundancy between video data such as motion compensated DPCM data and transforms blocks of digital video data (eg, 8x8 pixels) blocks into sets of transform coefficient data. . Such techniques are described in Chen and Pratt's article "Scene Adaptive Code.
r '', IEEE Transactions on Communications, COM-32, No.
3 (March 1984). By processing such transform coefficient data with a quantizer, a zigzag scanner and a VLC circuit, the amount of data to be transmitted can be effectively reduced.

In motion compensated DPCM, in particular, the data of the current frame is predicted from the data of the previous frame based on the motion estimation between the current frame and the previous frame. Such estimated motion may be explained by a two-dimensional motion vector representing a displacement of a pixel or the like between the previous frame and the current frame.

In order to compress a video signal by the above-mentioned technique, a processor capable of processing data at a high speed is required, and this is usually done by using a parallel processing technique. Generally, in a video signal decoding apparatus capable of parallel processing, the area of one video video frame is divided into a number of subframes, and the video data in the video video frame area is processed in subframe units.

On the other hand, in order to specify the motion vector to the search block in the current frame, the search block of the current frame and a large number of candidate blocks having the same size as the search block are similar to each other. Calculation (sim
ilarity calculation) is performed. This candidate block is included in the search area in the previous frame, and the size of the candidate area is much larger than the search block. Typically, the search block size has a range between 8x3 and 32x32 pixels. Therefore, the search area including the partition of any subframe also includes the partition of the adjacent subframe. Therefore, the motion estimation performed by each processor is based on multiple random access.
a shared memory system that can be accessed).

[0008]

SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide an improved video and video decoding device that can be processed in parallel without using a shared memory system that can be accessed multiple times randomly.

[0009]

In order to achieve the above object, according to the present invention, an encoded digital video in an encoded bitstream for reproducing an original video image signal is provided. A parallel decoding apparatus for decoding a signal, wherein the encoded digital video signal includes a large number of video frame data, each video frame data having a plurality of slice start codes indicating the start of each slice. A means for detecting a slice start code from the encoded digital video signal to generate a slice start detection signal, and the slice start of the encoded bit stream in response to the slice start detection signal. The number of codes is counted, and the counted slice start code is counted. Control means for generating a control signal in response to the number of frames, means for dividing the video frame data into two sub-frames in response to the control signal, and the divided video frame data. Two first-in first-out (FIFO) buffers, a video processing unit for expanding the encoded input data to reproduce the original video image signal, and a coupling of the reproduced original video image signal. And means for doing so. In the above,
The image processing unit includes two decoder modules and a frame memory unit for reproducing the original video image signal. The decoder module reproduces each of the two sub-frames, and the memory unit is divided. Memory module for storing the frame data, the memory module selection controller for generating the first and second selection signals and the first and second address data, and the first and second selection signals Further in response to the selection means for generating the pixel data stored in the corresponding memory module.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The parallel decoding apparatus of the present invention will be described in more detail below with reference to the drawings.

The present invention is provided for the communication of high definition television (HDTV) signals from a transmitter to a subscriber's receiver. At the transmitter at the encoder end of the communication link,
A digital video signal into successive frames of a television image is divided into subframes etc. for processing by a multiplexing processor. The decoding device of the invention comprises two decoder modules, each decoder module being assigned for the purpose of decoding video data from a particular subframe.

FIG. 1 shows a video image frame area 10 divided into two sub-frames. The total frame area comprises M horizontal picture lines, each picture line consisting of N pixels. For example,
A single HDTV frame consists of 960 picture lines, each picture line containing 1408 pixels. That is, a single HDTV frame consists of 60 slices, and each slice comprises 16 horizontal picture lines.

According to the invention, the video image frame area is divided into two sub-frames, for example sub-frames 13, 16 as shown in FIG. Its divided 2
To process one subframe, the processor is bounded by subframes in a video frame,
It is assigned to each subframe that expands the compressed digital data. At the encoder, motion estimation / compensation techniques are used to reduce data redundancy between the current video frame and one or more previous video frames.

FIG. 2 shows a block diagram of the parallel video decoding apparatus of the present invention. The parallel video decoding device includes a video data division circuit 30 and a video processing device 40.

The video data division circuit 30 includes a slice start code (SSC) detector 31, a control unit 32, a switching block 33 and two first-in first-out (FIF).
O) Includes buffers 34, 35 and is coupled to the video processor 40 and serves to divide the encoded digital data into two subframes for processing on a subframe-by-subframe basis. The video processing device 40 includes two decoder modules 50, 60, each of which has a variable length decoding (VLD) circuit 51, 61, a motion compensator 52, 62,
Inverse zigzag scanners 53 and 63, inverse quantizers (IQ) 54 and 64, inverse discrete cosine transform (IDCT) circuits 55 and 65 and adders 56 and 66, respectively, are combined and compressed with the frame memory unit 70 The input digital data of is expanded.

As shown in FIG. 2, a variable length coded digital video signal coming from a coding device (not shown) is inputted to a slice start code (SSC) detector 31 through a terminal 20. To be done. The encoded digital video signal comprises a large number of video frame data,
Each of the video frame data occupying the video image frame area has a motion vector and a plurality of slice start codes such as variable length coded transform coefficients. Here, each SSC represents the beginning of a slice included in the encoded bitstream. SSC detector 31
Detects the slice start code from the encoded digital video signal and generates a slice start detection signal to the control unit 32 which controls the switching block 33. The control unit 32 counts the number of SSCs in response to the slice start detection signal provided from the SSC detector 31. Whenever the number of counted SSCs reaches a predetermined value (eg 30), the control unit 32 switches the encoded digital video signal from the SSc detector 31 between S1 and S2. Control signal is generated, and thereby each frame of the incoming encoded digital video signal is divided into two sub-frames and the like and stored in the two FIFO buffers 34 and 35.

The FIFO buffer outputs the subframe data to the corresponding decoder modules 50 and 60 installed in the video processing device 40. Each decoder module is assigned to process video image data partitioned by a specific subframe, and is substantially the same as each other. The image processing device 40 reconstructs the DCT coefficient, performs motion compensation based on the motion vector, and forms the image data of the block given in the current frame. The decoded frame data that has been decoded from the video processing device 40 is sent to a frame former, where it is combined and a single data representing the original video video signal displayed on the display device (not shown). Form a stream.

FIG. 3 shows a block diagram of a video processing device 40 coupled to the video data division circuit 30 shown in FIG. The decoder modules 50 and 60 installed in the video processing device 40 are composed of the same components that perform the same functions.

As shown in FIG. 3, the video image data whose partition is defined by a specific subframe is transmitted from the image data division circuit 30 to the variable length decoding (VLD) circuits 51 and 61 through lines 501 and 601, respectively. Provided. Each VLD circuit 51, 61 processes video image data partitioned by a corresponding subframe. That is, each VLD circuit decodes the variable length coded transform coefficient and motion vector, and transform coefficient data and motion vector data are each inverse zigzag scanner 53 installed in the decoder module 50, 60. 63 and respective motion compensators 52,62
Transmit to. This VLD circuit is basically a lookup table. That is, a large number of code sets are provided in the VLD circuit, and a variable length code and a run length code (run
-length code) or the relationship between motion vectors. Thereafter, the output from each VLD circuit is distributed to the corresponding processor, which processes the video image data partitioned by the corresponding subframe.

Video image data whose partition is defined by the first sub-frame 13 shown in FIG.
Through the VLD circuit 51 to the inverse zigzag scanner 53. DC quantized by this inverse zigzag scanner 53
The T-coefficients, etc. are reconstructed to provide the original block of quantized DCT coefficients. The quantized block of DCT coefficients is converted into a DCT coefficient or the like by the inverse quantizer (IQ) 54 and provided to the inverse discrete cosine transform (IDCT) circuit 55.
The IDCT circuit 55 converts the DCT coefficient into difference data between the block of the current subframe and its corresponding block of the previous subframe. Then, the difference data from the IDCT circuit 55 is transmitted to the adder 56.

On the other hand, the variable length decoded motion vector from the VLD circuit 51 is provided to the motion compensator 52 and the memory module selection controller 75 in the frame memory unit 70 through lines 502 and 701. The motion compensator 52 extracts the corresponding pixel data from the previous sub-frame stored in the frame memory unit 70 based on the motion vector, and transmits the extracted pixel data to the adder 56. Corresponding pixel data from motion compensator 52 and IDCT circuit
The difference data from 55 is combined by the adder 56 so as to form the video data of the given block in the current sub-frame, recorded in the first memory module 71, and shown in FIG. Transmitted to 80.

Further, the decoder module 60 is the same as the decoder module 50 in terms of structure and handling. That is, the video image data whose partition is defined by the second sub-frame 16 shown in FIG. 1 is provided from the VLD circuit 61 to the inverse zigzag scanner 63 through the line 603,
After that, the quantized DCT coefficients are reconstructed.
This quantized DCT coefficient etc. is converted into a DCT coefficient etc. by IQ64 and provided to the IDCT circuit 65.
The DCT coefficient and the like are converted into difference data between the block of the current subframe and its corresponding block of the previous subframe. After that, the difference data from the IDCT circuit 65 is transmitted to the adder 66.

On the other hand, the motion vector from the VLD circuit 61 is
It is provided to the motion compensator 62 and the memory module selection controller 75 via lines 602 and 702. The motion compensator 62 extracts the corresponding pixel data from the previous sub-frame stored in the frame memory unit 70 based on the motion vector, and transmits the extracted pixel data to the adder 66. Corresponding pixel data and ID from motion compensator 62
The difference data from the CT circuit 65 is combined by the adder 66 so as to form the video data of the given block in the current sub-frame, recorded in the second memory module 72, and shown in FIG. It is transmitted to the former 80.

According to the present invention, one video image frame area is divided into two subframes, and each subframe data is processed using its corresponding decoder module. In such a case, when processing a partition between two sub-frames, for example slice 30 or slice 31 shown in FIG.
62 can access either one of the two memory modules 71, 72. That is, if the first motion vector provided from the VLD circuit 51 is found in the subframe 16 during the processing of the slice 30 in the subframe 13, the motion compensator 52
Must access the memory module 72.
Similarly, while processing slice 31 in subframe 16, VLD
The second motion vector applied from the circuit 61 is the subframe.
If at 13, the motion compensator 62 must access the memory module 71. At this time, the motion compensation process performed by each of the two decoder modules is controlled so that the two motion compensators do not access the same memory module at the same time. That is, the two memory modules are controlled to have an appropriate deadlock so that the two motion compensators do not access the same memory module at the same time. A more detailed description of the above operation will be described with reference to FIG.

As shown in FIG. 3, in order to access such mutually exclusive memory modules, the frame memory unit 70 includes two memory modules 71 and 72, two multiplexer circuits 73 and 74, and a memory module. Includes a selection controller 75. In the memory module selection controller 75, it is checked whether or not the motion vector is in the adjacent subframe.

The memory module selection controller 75 is a line
First and second motion vectors are received from VLD circuits 51 and 61 through 701 and 702, and first and second selection signals are generated to multiplexer circuits 73 and 74 through lines 703 and 704.
In addition, the memory module selection controller 75 is connected to the line 70
The first and second address data are generated through 5,706 and provided to the memory modules 71 and 72.

When each motion vector provided from the VLD circuits 51, 61 to the memory module selection controller 75 is within each corresponding subframe, the memory module selection controller 75 causes the first and second selection signals, For example, the logical value "low" is applied to the multiplexer circuits 73 and 74. Each multiplexer circuit has a first and second logic value "low".
In response to the selection signal, the corresponding pixel data based on the motion vector is output from the previous sub-frame stored in the corresponding memory module. That is, when the first selection signal has the logical value “low”, the multiplexer circuit 73
The pixel data from the memory module 71 to the motion compensator 52
To provide. Similarly, when the second select signal has a logical value “low”, the multiplexer circuit 74 causes the memory module 72 to operate.
Provide the pixel data from the to the motion compensator 62.

The memory module selection controller 75 if each motion vector is in another adjacent subframe.
Generates first and second select signals that are logic "high". In such a case, the multiplexer circuits 73 and 74 output the pixel data from the memory modules 71 and 72, respectively. As described above, under the control of the memory module selection controller 75, mutually exclusive memory access handling between the two memory modules 71 and 72 is performed.

FIG. 4 is a timing diagram showing the processing sequence for each subframe.

As shown in FIG. 4, the decoder module 50 begins processing the video image data that occupies subframe 13. After processing all slices contained in sub-frame 13, decoder module 60
Handle the handling of. At this time, the decoder module 50
Holds the deadlock state until the processing of the subframe 16 slice 31 is completed in order to prevent the two motion compensators 52 and 62 shown in FIG. 3 from accessing the same memory module. During processing of slice 31 in decoder module 60, decoder module 50 begins processing the next subframe data in the next video image frame area, eg slice 1 '. Decoder module
60 holds the deadlock until the decoder module 50 processes the slice 30 'in the next video image frame area. With this method, each decoder module 50, 60 repeats the decoding process until all the incoming video image data has been processed.

While an embodiment of the invention has been described above, those skilled in the art will be able to make various modifications without departing from the scope of the invention.

[0032]

Therefore, according to the present invention, when the compressed digital video data is decoded in parallel, the motion estimation process of each decoder module is such that each decoder module mutually accesses the same memory module. Controlled not to. Therefore, parallel processing can be performed without using a shared memory system capable of multiple random access.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a video image frame area divided into two sub-frames.

FIG. 2 is a block diagram of a decoding device of the present invention including a video data division circuit and a video processing device.

FIG. 3 is a block diagram showing in detail a video processing device coupled to the video data division circuit shown in FIG.

FIG. 4 is a timing diagram showing a processing order for each subframe.

[Explanation of symbols]

 30 video data division circuit 31 slice start code detector 32 control unit 33 switching block 34, 35 first-in first-out (FIFO) buffer 40 video processing device 50, 60 decoder module 70 frame memory unit

Claims (2)

[Claims] 1. To reproduce the original video image signal, a plurality of video frame data is included, each of the plurality of video frame data having a variable length encoded set of transform coefficients, a motion vector and a slice vector. A parallel decoding device for decoding a coded digital video signal in a coded bitstream having a plurality of slice start codes representing a start, wherein a slice from the coded digital video signal A means for detecting a start code and generating a slice start detection signal; and, in response to the slice start detection signal, counting the number of the slice start codes of the encoded bit stream, and counting the counted number of the slice start codes. Generates a control signal in response to the number of slice start codes And control means, responsive to the video frame data in said control signal,
Means for splitting into two subframes, two first in first out (FIFO) buffers for storing the split video frame data, decompressing the encoded input data to obtain the original video image A parallel decoding apparatus comprising: a video processing unit for reproducing a signal; and a unit for coupling the reproduced original video image signal. 2. The image processing means comprises two decoder modules and a frame memory unit for reproducing the original video image signal, each of the decoder modules being a decompressed digital video. The frame memory unit generates two signals, a memory module for storing the expanded digital video signal, first and second selection signals, and first and second address data. A memory module selection controller and selection means for generating pixel data stored in its corresponding memory module in response to the first and second selection signals. 1. The parallel decoding device according to 1.