JPH0820966B2 - Data processor test method - Google Patents

Description

The present invention relates to a data processing device test system, and more particularly to a data processing device test system suitable for use in a test of a preceding control function.

[Conventional technology]

A method using a random number program is known as a conventional technique for performing a preceding control function test in a data processing device. In this test method, there are cases where all test target instructions are not uniformly generated or a certain instruction is never generated, and it is difficult to perform a uniform test within a fixed time. In addition, this test method does not test the test items for which the expected value of the test instruction result is not uniquely determined by excluding it from the result comparison, and only executes the generated test instruction sequence once. Therefore, the test for the relation between the state of the buffer memories in the hardware and the advance control function is insufficient.

As a conventional technique of this type of test system, a technique described in, for example, Japanese Patent Laid-Open No. 61-23248 is known.

[Problems to be solved by the invention]

In the above-mentioned conventional technology, with respect to the generation of the test instruction, since the generation frequency of the generation instruction is not controlled, it is difficult to completely execute the test according to the purpose within a certain time.
Regarding the method of obtaining the expected value, test items with different expected values depending on the model are excluded from the comparison results of the execution results to narrow the effective test range. Since the instruction sequence is executed only once, there is a problem in that it is not possible to perform an operation test for the advance control function for the states of various buffer memories inside the hardware.

The object of the present invention is to solve the above-mentioned problems of the prior art, to make test instruction generation by random numbers uniform, and to compare all expected values of the execution results obtained by the test with the states of various buffers inside the hardware. It is to provide a data processing device test method capable of executing a preceding control function test for the.

[Means for solving problems]

According to the present invention, the object is to generate a test instruction by inputting random number data, obtain an expected value of the execution result of the test instruction by simulation, and cause the data processing device under test to execute the generated test instruction. In the data processor testing method of comparing the execution result with the expected value, the frequency of test instruction generation is registered for each instruction to control the frequency of test instruction generation with random number data as an input, and to generate one random number. The test environment is changed by executing the generated test instruction with data multiple times, and by performing comparison by obtaining the expected value for the next execution of the same generated test instruction by inverse simulation using the execution result of the generated test instruction as input. And execute a test instruction.

[Action]

The test instruction is created by the test instruction generator with reference to the random number data and the contents of the test instruction generation frequency table. The test instruction generation unit preferentially creates a test instruction with a low occurrence frequency based on the test instruction generation frequency table, and generates a uniform test instruction as a whole. As a result, the test command generation is made uniform. Regarding the operation to obtain the expected value that differs depending on the model, if the expected value is not uniquely determined by the result value obtained by executing the instruction, the result judgment section performs inverse simulation with the execution result value as the input. , The obtained value is the expected value. The state of the various buffer memories inside the hardware and the operation test of the advance control function are determined by the instructions and data from the main memory being transferred to the various buffer memories inside the hardware during the first execution of the first generation test instruction sequence. Since the preceding control function operates slowly, the instructions and data are transferred from the main storage device to various buffers at that time to execute the instructions, and when the second same generation test instruction sequence is executed, The instruction and data are executed without using the instruction and data from the main storage device by using the instructions and data in various buffer memories in the hardware. Therefore, for the advanced control function,
It becomes possible to send commands and data at high speed, the advanced control function operates at high speed, and it is possible to perform a combination test of the advanced control function and the status of the buffer memory inside the hardware under different environments. It consists of

〔Example〕

An embodiment of a data processor testing method according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of an embodiment of the present invention, FIG. 2 is a diagram for explaining the execution of instructions by the advance control function, and FIG. 3 is a diagram for explaining the overall operation of one embodiment of the present invention. FIG. 4 is a flow chart for explaining the operation of equalizing test command generation, FIG. 5 is a flow chart for explaining an operation for obtaining an uncertain expected value, and FIG. 6 is for the operation of FIG. A diagram explaining necessary information in the main storage device,
FIGS. 7 (a) and 7 (b) are diagrams for explaining the execution of instructions during the combination test of the state of the buffer memory inside the hardware and the preceding control function unit. In FIG. 1, 1 is a data processing device, 2 is a preceding control function unit, 3 is a buffer memory, 4 is a main storage device, 5 is a random number program, and 6 is an external storage device.

As shown in FIG. 1, the data processing device 1 for executing the data processing device test according to the present invention has a preceding control function unit 2 as shown in FIG.
And a buffer memory 3 inside the hardware and a main storage device 4. Then, in the test method according to the present invention, the random number program 5 is loaded from the test program library in the external storage device 6 to the main storage device 4 with this data processing device as a test target, and the random number program 5 generates a test instruction sequence. Let the advance control function unit 2
Is to be tested. As shown in FIG. 2, the advance control function unit 2 decodes the instruction D with respect to the generated test instruction sequence 8.
Address conversion A, reading of operand data OF, execution E
In this order, each stage operates according to the machine cycle 7 and sequentially processes each instruction of the generated test instruction sequence.

The present invention tests the preceding control function unit 2 by processing the test instruction sequence generated by the random number program 5 as described above, and the overall operation thereof will be described below with reference to FIG. .

(1) A random number is generated by the random number program 5, and a test instruction is generated using this random number as input data (Flow 1
3,14).

(2) By reading a test instruction generation frequency table (not shown) provided in the main storage device 4, checking the number of times of generation of the generated test instruction, and re-creating the test instruction so that the test instruction is uniformly generated. Adjustment is performed, and the test instruction generation frequency table is counted up in accordance with the generated test instruction (Flow 15 to 17).

(3) Next, the expected value for the execution result of the test instruction is obtained by simulating, and in response to the execution of the generated test instruction, the test instruction and data existing in the buffer memory 3 in the hardware are expelled. Clear the buffer memory (Flow 18,19).

(4) The result value is obtained by the first execution of the generated test instruction, and the expected value depending on the model is obtained by inverse simulation based on this result value (flow 20, 72).

(5) Check if the expected value and the result value match, and if they do not match, output an error message (flow 21, 22).

(6) If the expected value and the result value match in Flow 21,
Also, after outputting the error message in the flow 22, it is checked whether or not the same test instruction is executed twice consecutively (flow 23).

(7) If the test instruction is executed only once,
Returning to flow 20, the same instruction is re-executed. At this time,
Since the instruction and data at the time of the previous test instruction execution remain in the buffer memory 3, the execution of the test instruction this time causes the hardware internal environment to be different from that at the time of the first execution. The test of the advanced control function unit 2 for the state of the buffer memory 3 can be performed (flow.
20,72,21,22).

(8) If the same test instruction is executed twice in the flow 23, check whether or not the test instruction has been executed a prescribed number of times capable of completely testing all the functions of the advanced control function unit 2.
If the specified number of times has not been reached, the entire flow described above is repeatedly executed, and if the specified number of times has been reached, the random number program 5
A series of tests according to is completed (Flow 24).

In the test instruction execution process described above, the flow 15 to 16
Thus, although the test instructions are generated uniformly, the process for uniformly generating the test instructions is shown in FIG. 4 as a flow. Next, this process will be described. The test instruction re-creation for uniformly generating the test instruction does not have to be performed each time the test instruction is generated. In the example shown in FIG. 4, the test instruction is regenerated every time the number of executions of the test instruction becomes a multiple of 100. There is.

(1) When the test instruction is generated in the flow 14 shown in FIG. 3, it is checked whether the test instruction is in the re-creation mode. If not, whether the test instruction is executed is a multiple of 100. Check. If the number of executions of the test instruction is not a multiple of 100, the process moves to the flow 17 of FIG. 3 (25, 26).

(2) In the flow 26, if the number of executions of the test instruction is a multiple of 100, set the test instruction re-creation mode, extract the test instruction generation count value from the test instruction generation frequency table, and average these generation count values. The value is calculated, and the test instruction generation frequency table having a value smaller than this average value is moved to the test instruction reproduction frequency table in correspondence with the instruction code (Flow 2
7,28).

(3) In the test instruction re-creation mode in Flow 25 and after the processing in Flow 28 described above is completed, the number of valid test instruction generation frequency tables, which is the number of test instruction generation frequency tables, is calculated, and the number is “0”. Check whether or not (Flow 29,3
0).

(4) When the number of valid test instruction generation frequency tables is "0" in the flow 30, the test instruction re-creating mode is reset and the process proceeds to the flow 17 in FIG. 3 (flow 31).

(5) If the number of valid test instruction generation frequency tables is not “0” in the flow 30, as a process for equalizing test instruction generation, a random number value corresponding to the test instruction generation and the number of valid test instruction generation frequency tables are used. A new test instruction is generated, the count value of the test instruction generation frequency table for that instruction is incremented by 1, and the next random number value is set (flows 32 to 34).

(6) It is determined whether or not the prescribed number of test instructions has been selected. If the prescribed number has not been reached, the processing from flow 32 onward is repeated. If the prescribed number has been reached, the generation count value is the generation count. The test command reproduction generation frequency table having a value equal to or larger than the average value of the values is returned to the test command generation frequency table, and the normal processing of FIG. 3 is performed (flow 36).

Next, the operation of determining the execution result for the result value for which the expected value cannot be uniquely determined will be described with reference to FIGS. 5 and 6. For example, as shown in FIG. 6, a test instruction 54 created in the random number program area 5 of the main storage device 4, that is,
OP1 and OP2 in the instructions MVC, OP1 and OP2 have different address translation exception factors, and cannot uniquely determine the expected value. Regarding the execution of this instruction, the flow of FIG. 5 will be described below, and this flow is a detail of the flows 72 and 21 shown in FIG.

(1) First, a comparison judgment is made regarding an address translation exception. In this case, since the test instruction has an address translation exception factor, the interrupt code 52 and the interrupt code are determined from the hardware execution result of this instruction. Address translation exception addresses 53 are obtained as related information, and these are stored in the prefix area 55 of the main memory 4 as shown in FIG. 6 (flows 47 to 49).

(2) Next, the address translation address 53 obtained above
To the LRA instruction for execution. The execution of this LRA instruction is
Since the interrupt code corresponding to the given address translation address is generated, the execution result of this LRA instruction and the above-mentioned interrupt code 52 are checked (flow 50, 5).
1).

(3) If a match is not obtained in flow 51, an error message is output, and if a match is obtained, after the error message is output, and if the test instruction is not an address translation exception in flow 47, FIG. Flow 22 of.

As described with reference to the flow charts shown in FIGS. 3 and 5 and FIG. 6, the test method according to the embodiment of the present invention uses the test instruction sequence generated by the process of returning from the flow 23 to the flow 20 in FIG. Is executed multiple times. That is, in one embodiment of the present invention, the same test instruction sequence is executed twice. The process of obtaining the expected value by the inverse simulation performed by this process is a process of inversely obtaining the expected value based on the first execution result of the test instruction sequence to be executed a plurality of times, and the details of this process are shown in FIG. Will be described again with reference to.

The instruction 54 generated in the random number program area 5 shown in FIG. 6, “OP1 and OP2 in MVCOP1 and OP2”, have different address translation exception factors.
Which of them detects the exception factor first depends on the model. Therefore, an expected value that is uniquely determined as the expected value of the execution result of this test instruction cannot be obtained. That is, in this case, the expected value is not one. Therefore, it is necessary to perform processing for obtaining an expected value by inverse simulation.

Now, it is assumed that an address translation exception occurs due to either OP1 or OP2 of the instruction 54. As a result, the interrupt code 52 and the address translation exception address 53 that caused the address translation exception are obtained as information as the hardware execution result of the MVC instruction. The hardware stores this information in the prefix area shown in FIG.

Next, the address translation exception address 53 obtained above is
It is given as an operand of the LRA instruction and executed. LRA
An instruction is an instruction that translates a logical address indicated by an operand into a real address. When an exception factor is detected in the address translation process for finding the real address, the condition code and the address of the table that caused the address exception factor are detected as the execution result of the instruction. Is obtained. That is, the obtained LRA
The condition code of the instruction execution result is obtained as 2, for example, and the invalid bit of the page table is obtained as 1, for example. Here, by comparing the interrupt code 52, which is the hardware execution result of the MVC instruction, with the condition code, which is the execution result of the LRA instruction, it is possible to verify whether or not the address translation exception is a correct operation.

Further, as described above, when the condition code of the execution result of the LRA instruction is 2, the page table entry address causing the address exception factor is obtained, and the content indicated by the table entry address is the invalid bit = "1". By checking whether or not there are all expected values before executing the test instruction sequence, it is possible to create expected values from the execution results. As described above, according to the embodiment of the present invention, it is possible to reversely determine from the execution result whether or not the operation process and the operation result are normal by the inverse simulation process.

FIG. 7 is a diagram for explaining the execution of instructions during the combination test to enable the combination test of the state of the buffer memory 3 inside the hardware and the preceding control function unit 2.

As already explained with reference to FIG. 3, the first of the test instructions
The execution of the first time is performed after the contents of the buffer memory 3 inside the hardware have been swept out and cleared, so that in the processing of the machine cycle 70, for each test instruction of the test instruction sequence 8 It becomes necessary to transfer the instruction and the data to the buffer memory 3 of. Therefore, the first execution of the test instruction requires an extra machine cycle as shown in FIG. 7 (a), and its processing time becomes long. For example, in the execution of the test instruction, when the address translation A is performed after the instruction decoding D, the A stage is used by the test instruction, so that the dummy φ is inserted and waited in this machine cycle. Similarly, in the test instruction, the dummy φ will be inserted over two machine cycles.

The subsequent second execution of the same test instruction is performed using the contents of the buffer memory 3 because the contents of the buffer memory 3 inside the hardware have not been expelled.
Therefore, the execution of the second test instruction is performed as shown in FIG.
As shown in, the machine cycle 71 is performed by executing lean processing for the test instructions.

By executing the same test instruction twice, a combination test of the state of the buffer memory 3 and the preceding control function unit 2 can be performed.

Here, the combination test of the advanced control function unit 2 will be described in more detail.

The advance control function, which is also called pipeline control, is a function for continuously executing processes in parallel. Although the depth of parallel processing of the advanced control differs depending on the model, the outline of the advanced control is shown in FIG. 7 as an example.

In the above-described embodiment of the present invention, the test environment is changed and the test instruction sequence is executed a plurality of times. The reason is that the computer is provided with various buffers in order to realize high-speed processing of the computer. This is because the states of various buffers are different between the execution of the first test instruction sequence and the second and subsequent executions of the test instruction sequence. The fact that the states of the various buffers are different also means that the operation of the preceding control processing is also different.

 This will be described with reference to FIG.

FIG. 7A shows the first execution of the test instruction sequence. As described with reference to FIG. 3, since the first execution of the test instruction is performed after the contents of the buffer memory 3 inside the hardware are flushed and cleared, each test of the test instruction sequence 8 is performed in the processing of the machine cycle 70. In response to the instruction, it becomes necessary to transfer the instruction and the data from the main storage device 4 to the buffer memory 3 inside the hardware. For address translation, information is similarly set in the address translation buffer. Therefore, the first execution of the test instruction requires an extra machine cycle and the processing time becomes long.

On the other hand, the second and subsequent executions of the test instruction sequence shown in FIG. 7B are performed using the contents registered in the buffer memory 3, and the preceding control is performed without being disturbed. Can proceed.

As described above, according to the embodiment of the present invention, different test environments can be tested by changing the test environment and executing the test instruction sequence a plurality of times.

Then, in a computer in which the advanced control is very deep, the expected value may not be uniquely determined depending on the state of the pipeline, as described above. For example, depending on the state of the pipeline, there is an instruction in which whether or not an address translation exception is detected cannot be determined.

The inverse simulation according to the embodiment of the present invention can effectively perform the test of the test item whose expected value is not uniquely determined even in the computer having the preceding control function.

According to the above-described embodiment of the present invention, it is possible to improve the accuracy and efficiency in the test of the advance control function, as compared with the related art.

〔The invention's effect〕

As described above, according to the present invention, the generation of test instructions by random number data is controlled using the test instruction generation frequency table, so that the generation of test instructions is made uniform as a whole, and the test is performed. For test items for which the expected value cannot be uniquely determined, two types of related hardware values are extracted from the execution results, and the test target depends on whether or not they are mutually inconsistent. It is possible to completely compare the test results to each other, and by repeatedly executing the same test instruction sequence multiple times, the states of various buffer memories inside the hardware are changed, and the preceding control function unit related to it changes. There is an effect that the test of the operation combination of can be executed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram for explaining the execution of instructions by the advance control function, and FIG. 3 is a diagram for explaining the overall operation of one embodiment of the present invention. Flow chart, FIG. 4 is a flow chart for explaining the operation of equalizing test command generation, FIG. 5 is a flow chart for explaining an operation for obtaining a non-unique expected value, and FIG. 6 is necessary for the operation of FIG. FIG. 7A and FIG. 7B are views for explaining the information in the main memory device, and FIG. 7A and FIG. 7B are views for explaining the execution of the instruction at the time of the combination test of the state of the buffer memory inside the hardware and the preceding control function unit. . 1 ... Data processing device, 2 ... Advance control function unit, 3 ...
Buffer memory, 4 ... Main storage device, 5 ... Random number program, 6 ... External storage device.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masayoshi Tanaka, 1 Horiyamashita, Horiyamashita, Hadano, Kanagawa Prefecture, Kanagawa Plant, Nitrate Seisakusho Co., Ltd. (72) Toshihiko Takekoshi 1-16-5 Dogenzaka, Shibuya-ku, Tokyo Stock Company In Japan Business Consultant (72) Inventor Satoshi Someya 1 Horiyamashita, Hinoyamashita, Hadano City, Kanagawa Prefecture (72) Inventor Kaoru Suzuki, 1 Horiyamashita, Hadano City, Kanagawa Prefecture Hitate Manufacturing Kanagawa Plant ( 56) References JP 62-100847 (JP, A)

Claims (1)

[Claims] 1. A test command is generated by inputting random number data, an expected value of the execution result of the test command is obtained by simulation, the generated test command is executed by a data processing device under test, and the execution result and the expectation are obtained. In the data processor testing method of comparing with a value, the frequency of test instruction generation is registered for each instruction to control the frequency of test instruction generation with random number data as an input, and to generate a test instruction with one random number data. Is performed multiple times, and the expected value for the next execution of the same generated test instruction is obtained by inverse simulation using the execution result of the generated test instruction as an input, and the comparison is performed to change the test environment and execute the test instruction. A data processing device test method characterized by executing.