JPH0821018B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device provided with a priority control means for a common bus, and particularly to an occupation control when the number of signals on the common bus is small and in a high occupation state. The present invention relates to a data processing device having a bus priority control means suitable for the above.

[Conventional technology]

As described in Japanese Patent Publication No. 61-42306, the first data processing apparatus provided with the common bus priority control means has a common bus use request and a common bus self number (hereinafter referred to as ID number) when the common bus is not in use. A number (called a device number) is output and priority determination is performed. The second is JP-A-59-2086.
As described in No. 23, the data processing device that has acquired the common bus outputs the ID number along with the transfer data during data transfer, and each data processing device receives this ID number and uses it for priority determination of the next transfer. Take the method.

[Problems to be Solved by the Invention]

In the above-mentioned prior art, firstly, the priority determination for the next transfer must be made after the use of the common bus for data transfer is completed, so that the data transfer use efficiency of the common bus is lowered, and consequently the data transfer throughput of the common bus is reduced. There was a problem. The second is that the data processing device that has acquired the common bus needs an ID number signal line in order to notify the other data processing device of the ID number. For example, if the common bus can connect four data processing devices, Since two ID signals are required, the number of common bus signal lines will increase, and if there is no signal cable margin signal line, one signal cable will be used.
There may be a case where a book has to be newly added, which causes a problem that the number of signals increases.

It is an object of the present invention to provide a data processing device provided with a common bus priority control means which reduces the number of common bus signal lines and has high data transfer efficiency of the common bus.

[Means for solving the problem]

The above object is to transfer the previous data, which is the result of the bus priority determination from the bus acquisition request signal by the occupancy control means, which are connected to the plurality of devices sharing the common bus, respectively via the occupancy control lines. This is achieved by a data processing device in which a register for storing the device number is provided, and the bus priority determination for the next bus acquisition request signal is performed based on the contents of the register.

[Action]

When the occupancy control means determines the bus priority by the preset priority order and the bus acquisition request signal sent via the occupancy control line, the data processing device sets the previous bus acquisition request in its own device. Since it is possible to change the priority order by the device number of the previous data transfer generated from the signal and stored in the above register to make the priority determination for the next bus acquisition request signal, reduce the number of signal lines of the common bus and During the data transfer of the common bus, the priority determination for the next data transfer is performed to improve the transfer efficiency.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.

FIG. 2 is a system configuration diagram showing an embodiment of the data processing device according to the present invention. In FIG. 2, 1a to 1d are shared memory devices, 4a to 4d are CPU input / output buses, 5a to 5d are CPUs,
51a to 51d are main memory devices, and 6 is a shared memory bus. The system shown in FIG. 2 is an example that is configured by devices (data processing devices) including four CPUs 5a to 5d and the like.
When you want to transfer data from a to 5d to the CPU of another device, access the shared memory devices 1a to 1d connected via the CPU input / output buses 4a to 4d, and access the shared memory. The devices 1a to 1d are connected to the shared memory bus 6 and transfer data to other shared memory devices via the shared memory bus 6.

FIG. 3 is an internal block diagram of the shared memory device of FIG. In FIG. 3, 110 is a FIFO, 12 is a priority selection circuit, 13 is a bus acquisition control circuit (occupancy control means), 14 is a shared memory, 150 and 151 are selectors, 16 is a memory control circuit, 41
Is a connection signal, 171, 172 is a start, response connection signal, 181-187
Is an output buffer or an input gate. 1 in FIG.
An internal block diagram of one shared memory device 1a is shown, and the other shared memory devices 1b to 1d are also the same. When there is a write operation from the CPU 5a in FIG. 3, the access address is set to FIFO11.
The data is stored in the shared memory 14 by setting to 0, and the memory control circuit 16 is activated. The activated memory control circuit 16 reports the transfer request to the shared memory bus 6 to the bus acquisition control circuit 13.

FIG. 1 is a priority decision block diagram of the shared memory device of FIG. FIG. 1 is a detailed block diagram of the priority selection circuit 12 and the bus acquisition control circuit (occupancy control means) 13 shown in FIG. 3, 61 is a bus acquisition request signal bus (occupancy control line), and 62 is a bus use status signal. , 121 is a priority determination circuit, 122
Is a selector, 123 is an initial ID register, 124 is the previous master memory (register), 125 is PRESEL (preselect)
Signal, 131 is comparator, 132 is AND gate, 133 is I
D setting device, 134 is a flip-flop circuit, 135 is a LOCK generation circuit, 136 and 137 are output buffers, 138 is an input gate, 139 is a connection signal, 141 is a LOCK signal, 142 is a latch register, 143 is a flip-flop, and 144 is a reset signal. , 16
1 is a transfer request signal.

FIG. 4 is a time chart of the priority determination operation of FIG. In the configuration of FIG. 1, when the above-mentioned transfer request is input to the bus acquisition control circuit 13 from the memory control circuit 16 of FIG. 3 as the transfer request signal 161, the bus acquisition is performed by the output buffer 136 via the latch register 142. The request signal is output to the signal line corresponding to the ID number (device number) of the shared memory device 1a in the bus acquisition request signal bus 61 of the shared memory bus 6. When four common memory devices are connected as shown in FIG. 2, the bus acquisition request signal bus 61 is composed of the same four as the number of connected common memory devices. The bus acquisition request signal REQa-P shown in FIG.
When (Fig. 4) is output from the shared memory device 1a to the bus acquisition request signal bus 61, all the connected shared memory devices are connected.
It is input to the LOCK generation circuit 135 of the bus acquisition control circuit 13 in 1a to 1d. This LOCK generation circuit 135 is a LO signal if any of all signals on the bus acquisition request signal bus 61 is ON.
LOCK-P (Fig. 4) of CK signal 141 is output. This LOCK
The signal 141 acts on the latch register 142 to latch the state of the transfer request signal 161 at that time, prohibit the generation of a new bus acquisition request signal, and set the flip-flop 134. After the output of the LOCK signal 141, the bus acquisition request signal bus 61 is stabilized, and after the priority judgment time t ₁ (FIG. 4) in the priority judgment circuit 121 in the priority selection circuit 12 has elapsed, A sampling signal SAMPLE-P (FIG. 4) of the priority determination result is generated. Here, the priority determination circuit 121 inputs the lowest priority ID number in the previous mask storage memory 124 via the selector 122 as A input,
The bus acquisition request signal bus 61 is used as the B input for priority determination, and the priority determination result is latched by the sampling signal SAMPLE-P and the PRESEL signal 125 is output. If the lowest ID number of the priority order, which is the A input of the priority determination circuit 121, is the ID number d, the ID number a of the priority determination result can acquire the bus occupancy right, and the PRESELa-P of the PRESLE signal 125 can be obtained. (4th
Only the figure) turns on. The PRESEL signal 125 is provided in the same number as the bus acquisition request signal bus 61 in each of the shared memory devices 1a to 1d.

The PRESEL signal 125 and the ID number of its own ID setter 133 are compared by the comparator 131 of the bus acquisition control circuit 13, and if the bus can be acquired by itself, it is ANDed with the transfer request signal 161.
The bus usage status flip-flop 143 is set via the gate 132 to output the SEL (select) signal SELa-P (FIG. 4), and the bus usage status signal 62 BU on the shared memory bus 6.
In addition to outputting SY-P (Fig. 4), the memory control circuit 16 of Fig. 3 is notified by the connection signal 139 that the bus has been acquired. When the bus use status signal 62 is output to the shared memory bus 6, it is taken in by the input gate 138 and the LOCK generation circuit 135 is reset (FIG. 4) to reset the unnecessary bus acquisition request signal bus 61. , Preparing to accept the next bus acquisition request signal REQ. Here, the shared memory device is accessed and data is transferred by the CPU 5a (fourth
When the data transfer is completed, the memory control circuit 16 outputs the FF reset signal 144 and resets the bus use status flip-flop 143. The PRESEL signal 125, which is the priority determination result of the priority determination circuit 121, is the previous master storage memory 124.
The ID number, which is the contents of the previous master storage memory 124, is input via the selector 122 to the priority determination circuit 121 as A input in order to change the priority order in the next priority determination. Subsequently, when the bus acquisition request signal bus 61 is turned on while the bus is in use and the bus acquisition request signal REQb-P (Fig. 4) is output, the bus usage status signal 62 BUSY-P
Is output, the priority determination circuit 121 completes the priority determination and enters the waiting state with only PRESELb-P (FIG. 4) of the PRESEL signal 125 turned on, and the data transfer on the shared memory bus 6 ends. When the BUSY-P of the bus usage status signal 62 is turned off, the shared memory device 1b that has acquired the shared memory bus 6 sets the bus usage status flip-flop 143 and outputs the signal SEL.
b-P (Fig. 4) is output, and BUSY of bus usage status signal 62
-P is turned on and data transfer by the CPU 5b is started.

The operation when one device connected to the shared memory bus 6 is restored or when the device is disconnected from the shared memory bus 6 and then reconnected to the shared memory bus 6 is described in the shared memory device. The contents of the previous master storage memory 124 in the previous master storage memory 124 are unknown and it is different from the contents of the previous master storage memory 124 in the shared memory device which is performing other data transfer. There is a possibility that the data transfer may be started by erroneously determining that the bus has been acquired by the priority determination order. In order to avoid data transfer due to such erroneous judgment, the connection signal 41 from the CPU side causes the ID setting unit 133 of its own
The ID number is selected by the selector 122 and input to the A input of the priority determination circuit 121, and when the data is transferred from another device next time with the own ID number as the lowest ID number in the priority order, the ID number of the device is selected. Is reset to the master storage memory 124 the last time, so that the same contents as those of other devices are obtained. Next, the operation in the case where the devices connected to the shared memory bus 6 simultaneously restore power and a plurality of shared memory devices simultaneously output the bus acquisition request signal 62 will be described with reference to FIG.

FIG. 5 is a time chart of priority determination operation at the time of simultaneous power recovery in FIG. In the configuration of FIG. 1, all of the shared memory devices connected to the shared memory bus 6 are restored at the same time, and the ID numbers
The shared memory devices 1a and 1b of a and b are REQb of the bus acquisition request signal 62.
When -P and REQa-P (Fig. 5) are simultaneously output, the LOCK generation circuit 141 of the bus acquisition control circuit 13 outputs the LOCK signal 141 LOCK-
P (FIG. 5) is output and, at the same time t ₁ has elapsed, priority determination is made by the sampling signal SAMPLE-P (FIG. 5) of the priority determination circuit 121 and PRESELb-P of the PRESEL signal 125 is output. , The priority determination circuit 121 in the shared memory device 1a, 1b determines that the own ID number a, b is the lowest priority, respectively, so it is determined that the other party has acquired the bus, and both are in a waiting state. . To get out of this state, LOCK signal 141
If BUSY-P of the bus usage status signal 62 is not output even after the lapse of time t ₁ + t ₂ (FIG. 5) from ROCK-P of No. 5, it is regarded as time-out and the flip-flop 134 outputs the time-out signal TIMEOUT-P (No. 5). Output), selector 1
22 is selected by selecting the initial ID register 123 having a predetermined ID number (ID number “3” (d) in FIG. 1), and the priority determination circuit 121 performs the bus priority determination again. In the example, ID number a has the highest priority, so P of PRESEL signal 125
RESELa-P (Fig. 5) is output and the bus usage status signal 62
BUSY-P is output to enable bus acquisition.

〔The invention's effect〕

According to the present invention, in the distributed masterless data transfer of the data processing device, it is possible to transfer with a small number of common bus signal lines and to increase the total transfer amount of the common bus.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a priority determination block diagram showing an embodiment of a data processing device according to the present invention, and FIG. 2 is a system configuration diagram of the same,
FIG. 3 is a block diagram of the shared memory device, FIG. 4 is an operation time chart of FIG. 1, and FIG. 5 is an operation time chart of simultaneous power recovery. 1a to 1c ... shared memory device, 5a to 5d ... CPU, 6 ... common memory bus, 61 ... bus acquisition request signal bus (occupancy control line), 12 ... priority selection circuit, 121 ... priority determination circuit , 124
...... Previous master memory memory (register), 13 ...... Bus acquisition control circuit (occupancy control means).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-61-163458 (JP, A) JP-A-59-208623 (JP, A) JP-B-61-42306 (JP, B1)

Claims (3)

[Claims] 1. A plurality of common buses each having a bus acquisition request signal line corresponding to a device, and a plurality of means each outputting a bus acquisition request to a corresponding bus acquisition request signal line to request occupation of the common bus. In the data processing device, the setting means sets the device number of each device, the register for storing the device number of the device that previously occupied the common bus, and the bus acquisition request signal line. When the bus acquisition request from each device is acquired and the device with the highest priority for acquiring the bus occupation right is determined and the device number of the device is output, the device number stored in the register is referred to. Priority determining means for determining and outputting the priority of the device of the device number as the lowest and updating the contents of the register with the output content, device number output by the priority determining means, and The data processing apparatus characterized by self compares the device number set in the constant unit provided with occupancy control means for occupying the common bus when it is determined that earn bus usage right. 2. The contents of the register according to claim 1, when the power of each device is restored or when the device is switched from being disconnected from the common bus to being connected to the common bus. A data processing apparatus comprising a switching means for inputting the equipment number set in the setting means to the priority determination means to make the equipment number the lowest equipment number in the priority order. 3. A means for outputting a bus use status signal to a common bus when a bus occupancy right is acquired for each device, and a predetermined time after a bus acquisition request is output to a bus acquisition request signal line. If the bus usage status signal is not output to the common bus even after the elapse, a predetermined device number is given to the priority determination means as the lowest priority device number instead of the device number set in the setting means. And a means for determining the priority order.