JPH08211367A - Liquid crystal display - Google Patents
Liquid crystal displayInfo
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- JPH08211367A JPH08211367A JP7289546A JP28954695A JPH08211367A JP H08211367 A JPH08211367 A JP H08211367A JP 7289546 A JP7289546 A JP 7289546A JP 28954695 A JP28954695 A JP 28954695A JP H08211367 A JPH08211367 A JP H08211367A
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- Prior art keywords
- voltage
- liquid crystal
- crystal display
- gradation
- circuit
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Abstract
(57)【要約】
【課題】 低消費電力と高画質表示を可能とする液晶表
示装置の階調電圧生成回路を提供すること。
【解決手段】 複数の階調基準電圧の各階調基準電圧間
を直列抵抗分圧回路により分圧して液晶層に印加する多
階調の階調電圧を生成する液晶表示装置であって、前記
直列抵抗分圧回路の各階調基準電圧を印加する端子間の
抵抗値を、各階調基準電圧間の電位差にほぼ比例した抵
抗値とする。
(57) Abstract: To provide a gradation voltage generation circuit of a liquid crystal display device capable of low power consumption and high image quality display. A liquid crystal display device for generating a multi-gradation gray scale voltage applied to a liquid crystal layer by dividing a gray scale reference voltage of a plurality of gray scale reference voltages by a series resistance voltage dividing circuit, The resistance value between the terminals to which each gradation reference voltage is applied in the resistance voltage dividing circuit is set to a resistance value that is substantially proportional to the potential difference between each gradation reference voltage.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、パーソナルコンピ
ュータ、ワークステーション等に用いる液晶表示装置に
関し、特に、多階調の表示が可能な液晶表示装置の階調
電圧生成回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device used for a personal computer, a workstation, etc., and more particularly to a grayscale voltage generation circuit for a liquid crystal display device capable of displaying a plurality of grayscales.
【0002】[0002]
【従来の技術】多色表示、例えば、64階調の多色表示
が可能なTFT液晶表示装置の一例が下記文献Iに記載
されている。2. Description of the Related Art An example of a TFT liquid crystal display device capable of multi-color display, for example, 64-gradation multi-color display is described in Document I below.
【0003】I 『Low−Power 6−bit C
olumn Driverfor AMLCDs』 (1994年6月発行 SID 94 DIJEST P.
351−354)。I "Low-Power 6-bit C"
"Olven Driver AMLCDs" (issued in June 1994, SID 94 DIJEST P.
351-354).
【0004】図8は、前記文献Iに記載されているTF
T液晶表示装置の概略構成を示すブロック図である。FIG. 8 shows the TF described in the above-mentioned document I.
It is a block diagram showing a schematic structure of a T liquid crystal display device.
【0005】図8において、液晶表示パネル(TFT−
LCD)は、800×3×600画素Pixから構成さ
れる。In FIG. 8, a liquid crystal display panel (TFT-
The LCD) is composed of 800 × 3 × 600 pixels Pix.
【0006】TFT液晶表示パネルの画素Pixの等価
回路を図9に示す。An equivalent circuit of the pixel Pix of the TFT liquid crystal display panel is shown in FIG.
【0007】ITOは画素電極、COMは対向電極で、
ITOとCOMと液晶層で液晶表示素子(図示せず)が
形成される。ITO is a pixel electrode, COM is a counter electrode,
A liquid crystal display element (not shown) is formed by ITO, COM, and a liquid crystal layer.
【0008】液晶表示素子は等価回路で示すと静電容量
CLCで表せる。The liquid crystal display element can be represented by an electrostatic capacitance CLC when represented by an equivalent circuit.
【0009】液晶表示素子は図14に示すようにITO
とCOMの間に印加する電圧により光の透過率が変化す
るので、画素電極ITOに、COMに印加する電圧を基
準として複数の表示階調毎に電圧が決められた、階調電
圧を印加することにより多階調表示ができる。The liquid crystal display element is made of ITO as shown in FIG.
Since the light transmissivity changes according to the voltage applied between COM and COM, a grayscale voltage is applied to the pixel electrode ITO, in which a voltage is determined for each of a plurality of display grayscales with reference to the voltage applied to COM. This allows multi-gradation display.
【0010】Dnはドレイン線あるいは映像信号線であ
り、階調電圧はドレインドライバ11から複数のドレイ
ン線Dnに印加される。Dn is a drain line or a video signal line, and a gradation voltage is applied from the drain driver 11 to a plurality of drain lines Dn.
【0011】TFTは薄膜トランジスタであり、ITO
に電気的に接続されるソースS、Dnに電気的に接続さ
れるドレインD及びゲートGを有し、ゲートGに加える
電圧によりDn、ITO間の電気的導通、非導通を制御
する。TFT is a thin film transistor, and ITO
It has a source S and a drain D electrically connected to Dn and a gate G, and the voltage applied to the gate G controls electrical conduction and non-conduction between Dn and ITO.
【0012】Gnはゲート線あるいは走査線であり、G
nは対応する画素PixのTFTのゲートGに接続され
ているので、Gnにより階調電圧を印加する画素電極I
TOを選択することが出来る。Gn is a gate line or a scanning line, and Gn
Since n is connected to the gate G of the TFT of the corresponding pixel Pix, the pixel electrode I that applies the gradation voltage by Gn
You can select TO.
【0013】Caddは保持容量、Cnは容量線で、C
addはITOに印加された階調電圧を、次に階調電圧
がITOに印加される迄の間、保持することが出来る。Cadd is a holding capacitance, Cn is a capacitance line, and C
add can hold the grayscale voltage applied to the ITO until the next grayscale voltage is applied to the ITO.
【0014】図10は図9に示す画素に印加される電圧
波形のタイミングを示す図である。FIG. 10 is a diagram showing the timing of the voltage waveform applied to the pixel shown in FIG.
【0015】同図で(1)はゲート線Gnの波形、
(2)は対向電極COM及び容量線Cnの波形、(3)
はドレイン線Dnの波形を示す。画素電極ITOに階調
電圧を印加する時はゲート電圧波形(1)が Gate
On レベルとなりTFTのソース、ドレイン間が導
通する。ドレイン電圧波形(3)と対向電極電圧波形
(2)は位相が反転した形になっており、ドレイン電圧
波形(3)と対向電極電圧波形(2)の差の電圧が液晶
表示素子CLCに印加される。液晶表示素子CLCに印加さ
れる電圧は、正極性で印加されるタイミングと負極性で
印加されるタイミングが交互に現れるように、ゲート電
圧波形(1)、対向電極電圧波形(2)、ドレイン電圧
波形(3)を設定しているので、液晶表示素子CLCには
直流成分が印加されず、TFT液晶表示パネルの寿命の
低下、画像の焼き付き及び残像の問題が無い。In the figure, (1) shows the waveform of the gate line Gn,
(2) is a waveform of the counter electrode COM and the capacitance line Cn, (3)
Shows the waveform of the drain line Dn. When applying the gradation voltage to the pixel electrode ITO, the gate voltage waveform (1) is Gate.
It is turned on and the TFT source and drain are electrically connected. The drain voltage waveform (3) and the counter electrode voltage waveform (2) have inverted phases, and the difference voltage between the drain voltage waveform (3) and the counter electrode voltage waveform (2) is applied to the liquid crystal display element CLC. To be done. The voltage applied to the liquid crystal display element CLC has a gate voltage waveform (1), a counter electrode voltage waveform (2), and a drain voltage such that the positive polarity application timing and the negative polarity application timing alternate. Since the waveform (3) is set, no direct current component is applied to the liquid crystal display element CLC, and there is no problem of shortening the life of the TFT liquid crystal display panel, image sticking, and afterimage.
【0016】TFTを用いた液晶表示装置の特徴は、T
FTというスイッチング素子を介して画素電極ITOに
階調電圧を印加する為各画素Pix間のクロストークが
無く、単純マトリックス形液晶表示装置のようにクロス
トークを防止する為の特殊な駆動方法を用いる必要が無
く、多階調表示が可能なことにある。The characteristic of the liquid crystal display device using the TFT is that T
Since a grayscale voltage is applied to the pixel electrode ITO through a switching element called FT, there is no crosstalk between the pixels Pix, and a special driving method for preventing crosstalk is used as in a simple matrix liquid crystal display device. There is no need, and it is possible to perform multi-gradation display.
【0017】また図8に示すように、液晶表示パネル
(TFT−LCD)の一方の側にドレインドライバ11
が配置され、このドレインドライバ11を薄膜トランジ
スタ(TFT)のドレイン線に接続し、薄膜トランジス
タ(TFT)に液晶を駆動するための電圧を供給する。Further, as shown in FIG. 8, the drain driver 11 is provided on one side of the liquid crystal display panel (TFT-LCD).
Is connected to the drain line of the thin film transistor (TFT) to supply a voltage for driving the liquid crystal to the thin film transistor (TFT).
【0018】また、液晶表示パネル(TFT−LCD)
の側面にはゲートドライバ12が配置され、薄膜トラン
ジスタ(TFT)のゲート線に接続し、1水平動作時間
(1H)薄膜トランジスタ(TFT)のゲートGにGa
te On電圧を供給する。A liquid crystal display panel (TFT-LCD)
A gate driver 12 is disposed on the side surface of the thin film transistor (TFT) and connected to the gate line of the thin film transistor (TFT).
te On voltage is supplied.
【0019】表示制御装置10は、インターフェースコ
ネクタから、本体コンピュータからの表示用データと表
示制御信号を受け取り、これを基にドレインドライバ1
1,ゲートドライバ12を駆動する。The display control device 10 receives the display data and the display control signal from the main body computer from the interface connector, and based on this, the drain driver 1
1, to drive the gate driver 12.
【0020】ここで、本体コンピュータからの表示用デ
ータは、各色毎6ビットの18ビットで構成されてい
る。The display data from the main computer is composed of 18 bits, 6 bits for each color.
【0021】ドレインドライバ11は、図11に示すよ
うに、1個の階調電圧生成回路を有し、前記階調電圧生
成回路は、内部電源回路13から入力される9値の階調
基準電圧(V0−V8)から64階調分の階調電圧を生
成する。As shown in FIG. 11, the drain driver 11 has one gradation voltage generation circuit, and the gradation voltage generation circuit is a nine-value gradation reference voltage input from the internal power supply circuit 13. A gradation voltage for 64 gradations is generated from (V0-V8).
【0022】また、ドレインドライバ11は、シフトレ
ジスタにより表示データラッチ用クロック信号CLK1
に同期して各色毎6ビットの表示用データを入力レジス
タ内に出力本数分だけ取り込む。次に、出力タイミング
制御用クロック信号CLK2に応じて、入力レジスタ内
の表示用データをストーレージレジスタに取り込み、出
力回路は前記階調電圧生成回路で生成された64階調分
の階調電圧の中から、表示用データに対応する階調電圧
を選択して各ドレイン線Dnに出力する。Further, the drain driver 11 uses a shift register to latch the display data latching clock signal CLK1.
In synchronism with the above, 6-bit display data for each color is fetched into the input register by the number of outputs. Next, in response to the output timing control clock signal CLK2, the display data in the input register is taken into the storage register, and the output circuit outputs the gradation voltage for 64 gradations generated by the gradation voltage generating circuit. The grayscale voltage corresponding to the display data is selected from the inside and output to each drain line Dn.
【0023】ドレインドライバ11の極性端子はドレイ
ン線Dnに出力する電圧の極性を制御する為に設けら
れ、キャリー入力、キャリー出力端子は液晶表示装置内
の複数のドレインドライバ11間の連携を取る為に設け
られている。The polarity terminal of the drain driver 11 is provided for controlling the polarity of the voltage output to the drain line Dn, and the carry input and carry output terminals are for coordinating between the plurality of drain drivers 11 in the liquid crystal display device. It is provided in.
【0024】図12は、前記図11に示すドレインドラ
イバ11の階調電圧生成回路を示す図である。FIG. 12 is a diagram showing a grayscale voltage generation circuit of the drain driver 11 shown in FIG.
【0025】図12の(a)に示すように、前記図11
に示すドレインドライバ11の階調電圧生成回路は、内
部電源回路13から入力された9値の階調基準電圧(V
0−V8)の各階調基準電圧間を、直列抵抗分圧回路1
により8等分してV00〜V63の64階調分の階調電
圧を生成するものである。As shown in FIG.
The gray scale voltage generation circuit of the drain driver 11 shown in FIG.
0-V8) between each gradation reference voltage, the series resistance voltage dividing circuit 1
Is used to generate a gradation voltage for 64 gradations of V00 to V63.
【0026】[0026]
【発明が解決しようとする課題】図14に示すように、
一般に液晶層に印加する電圧と透過率との関係は、リニ
アではなく、透過率の高いところ及び低いところでは、
液晶層に印加する電圧に対する透過率の変化は少なく、
その中間となるところで透過率の変化が大きい。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As shown in FIG.
Generally, the relationship between the voltage applied to the liquid crystal layer and the transmittance is not linear.
The change in transmittance with respect to the voltage applied to the liquid crystal layer is small,
There is a large change in transmittance at an intermediate point.
【0027】このため、64階調の多色表示が可能な液
晶表示装置において、64階調をリニアに表示するため
には、ドレインドライバ11の階調電圧生成回路に与え
る階調基準電圧値は、等間隔ではなく、中間調付近(V
2〜V6)で差が小さく、それ以外(V0〜V2,V6
〜V8)で大きくしなければならない。Therefore, in a liquid crystal display device capable of multi-color display of 64 gradations, in order to linearly display 64 gradations, the gradation reference voltage value given to the gradation voltage generating circuit of the drain driver 11 is , Not evenly spaced, near the halftone (V
2 to V6), the difference is small, and other than that (V0 to V2, V6
~ V8) must be increased.
【0028】ところが前記文献では、前記図12に示す
ドレインドライバ11の階調電圧生成回路の直列抵抗分
圧回路1の抵抗値をどのように設定するかは詳しく言及
していない。However, in the above-mentioned document, it is not mentioned in detail how to set the resistance value of the series resistance voltage dividing circuit 1 of the gradation voltage generating circuit of the drain driver 11 shown in FIG.
【0029】そのため、図12の(a)に示す階調電圧
生成回路の直列抵抗分圧回路1に、図14に示す等間隔
ではない階調基準電圧V0〜V8を印加すると、階調基
準電圧を供給する線に直流(DC)電流が流れ、消費電
力が増大する問題があった。Therefore, when the grayscale reference voltages V0 to V8 shown in FIG. 14 which are not evenly spaced are applied to the series resistance voltage dividing circuit 1 of the grayscale voltage generating circuit shown in FIG. There is a problem in that a direct current (DC) current flows through the line that supplies the power and the power consumption increases.
【0030】例えば図12の(b)は同図(a)を簡略
化したものであるが、階調電圧生成回路において直列抵
抗分圧回路1の各階調基準電圧印加端子間の抵抗値はそ
れぞれ100Ωで一定の値にすると、階調基準電圧V0
−V1間、V1−V2間、V6−V7間、V7−V8間
の階調基準電圧差が、階調基準電圧V2−V3間、V3
−V4間、V4−V5間、V5−V6間の階調基準電圧
差の2倍となる。For example, FIG. 12B is a simplified version of FIG. 12A, but the resistance values between the gradation reference voltage applying terminals of the series resistance voltage dividing circuit 1 in the gradation voltage generating circuit are different from each other. When a constant value of 100Ω is set, the gradation reference voltage V0
-V1, between V1-V2, between V6-V7, and between V7-V8 the gradation reference voltage differences between the gradation reference voltages V2-V3, V3.
It becomes twice the gradation reference voltage difference between V4, V4 and V5, and V5 and V6.
【0031】したがって、直列抵抗分圧回路1の階調基
準電圧V6,V7の階調基準電圧を印加する端子間、お
よび、階調基準電圧V1,V2の階調基準電圧を印加す
る端子間を流れる電流は、10mA(1.0V/100
Ω=10mA)であるのに対して、直列抵抗分圧回路1
の階調基準電圧V5,V6、および、階調基準電圧V
2,V3の階調基準電圧を印加する端子間を流れる電流
は、5mA(0.5V/100Ω=5mA)となる。Therefore, between the terminals of the series resistance voltage dividing circuit 1 to which the gradation reference voltages V6 and V7 are applied and between the terminals to which the gradation reference voltages V1 and V2 are applied. The flowing current is 10mA (1.0V / 100
Ω = 10 mA) while the series resistance voltage dividing circuit 1
Gradation reference voltages V5, V6 and gradation reference voltage V
The current flowing between the terminals to which the gradation reference voltages of 2 and V3 are applied is 5 mA (0.5 V / 100Ω = 5 mA).
【0032】そのため、電流値が不連続となる直列抵抗
分圧回路1の階調基準電圧V6を印加する端子、およ
び、階調基準電圧V2を印加する端子から電流が流入・
流出し、階調電圧生成回路に流れる電流が多くなる為、
ドレインドライバ11の消費電力が増大するという問題
があった。Therefore, current flows from the terminal to which the gradation reference voltage V6 is applied and the terminal to which the gradation reference voltage V2 is applied of the series resistance voltage dividing circuit 1 in which the current value is discontinuous.
Since the current flowing out and flowing to the gradation voltage generation circuit increases,
There is a problem that the power consumption of the drain driver 11 increases.
【0033】また階調基準電圧V1〜V7を供給する線
に電流が流入・流出すると電源回路13の内部抵抗によ
る消費電力の増加も問題であった。Further, when currents flow in and out of the lines supplying the gradation reference voltages V1 to V7, there is a problem that the power consumption increases due to the internal resistance of the power supply circuit 13.
【0034】図13は電源回路13の階調基準電圧V0
〜V8の生成部を示す図である。FIG. 13 shows the gradation reference voltage V0 of the power supply circuit 13.
It is a figure which shows the production | generation part of -V8.
【0035】同図(a)は階調基準電圧V0〜V8の生
成部を抵抗分圧回路で生成する例を示す。階調基準電圧
V0〜V8は抵抗RR0〜RR9の値の比により設定さ
れ、抵抗RR0〜RR9の分圧回路の出力は、バッファ
回路OP0〜OP9により、充分な電力に増幅されてド
レインドライバ11の直列抵抗分圧回路1に出力され
る。FIG. 9A shows an example in which the generation unit of the gradation reference voltages V0 to V8 is generated by a resistance voltage dividing circuit. The gradation reference voltages V0 to V8 are set by the ratio of the values of the resistors RR0 to RR9, and the output of the voltage dividing circuit of the resistors RR0 to RR9 is amplified to a sufficient electric power by the buffer circuits OP0 to OP9 and the drain driver 11 outputs the same. It is output to the series resistance voltage dividing circuit 1.
【0036】同図(b)は同図(a)の等価回路を示す
図である。電源回路13は直流電圧源v0〜v8と内部
抵抗r0〜r8で表すことが出来る。直流電圧源v0〜
v8は抵抗RR0〜RR9の分圧回路の出力により決ま
り、内部抵抗r0〜r8はバッファ回路OP0〜OP9
の出力インピーダンスにより決まると考えられる。FIG. 7B is a diagram showing an equivalent circuit of FIG. The power supply circuit 13 can be represented by DC voltage sources v0 to v8 and internal resistors r0 to r8. DC voltage source v0
v8 is determined by the output of the voltage dividing circuit of the resistors RR0 to RR9, and the internal resistors r0 to r8 are the buffer circuits OP0 to OP9.
It is considered to be determined by the output impedance of.
【0037】仮に内部抵抗r0〜r8を20Ωにしたと
すると、階調基準電圧V2の供給線に5mAの電流が流
れると0.5mWの電力が余分に電源回路13で消費さ
れることになる。また内部抵抗r2により0.2Vの電
圧降下を生じるので、ドレインドライバ11に出力する
階調基準電圧V2も0.2V降下し、目的とする階調電
圧を液晶表示パネルに出力出来ず、正しい表示階調が得
られない問題も生じる。Assuming that the internal resistances r0 to r8 are set to 20Ω, 0.5 mW of power will be additionally consumed by the power supply circuit 13 when a current of 5 mA flows through the supply line of the gradation reference voltage V2. Further, since the internal resistance r2 causes a voltage drop of 0.2V, the grayscale reference voltage V2 output to the drain driver 11 also drops by 0.2V, and the target grayscale voltage cannot be output to the liquid crystal display panel, resulting in a correct display. There is also a problem that gradation cannot be obtained.
【0038】またドレインドライバ11では、構成を簡
単にし集積回路のチップサイズを小さくする目的で、図
11に示すように、階調電圧生成回路の出力をドレイン
ドライバ11が駆動する全てのドレイン線で共用する
為、1つのドレインドライバ11内で同一階調電圧を選
択するドレイン信号線の本数が多くなると、階調基準電
圧生成回路1の抵抗R1〜R8に流れる電流が大きくな
り、各階調電圧がドレインドライバ11毎に変動し、特
に、印加電圧に対する液晶層の透過率の変化が大きい中
間調表示(V2〜V6)の表示画面上では、ドレインド
ライバ11が異なるドレイン線Dn,Dn+1に対応す
る画素Pixの境界で輝度差が発生し表示品質が低下す
るという問題点があった。Further, in the drain driver 11, for the purpose of simplifying the configuration and reducing the chip size of the integrated circuit, as shown in FIG. 11, the output of the gradation voltage generating circuit is applied to all drain lines driven by the drain driver 11. Since they are shared, when the number of drain signal lines that select the same gray scale voltage in one drain driver 11 increases, the current flowing through the resistors R1 to R8 of the gray scale reference voltage generation circuit 1 increases, and each gray scale voltage is changed. Pixels corresponding to different drain lines Dn and Dn + 1 are displayed on the display screen of the halftone display (V2 to V6) which varies depending on the drain driver 11 and in which the change of the transmittance of the liquid crystal layer with respect to the applied voltage is large. There is a problem in that there is a difference in brightness at the boundary of Pix and the display quality is degraded.
【0039】すなわち図12に示す例で見ると、階調基
準電圧差V3(2),V4(3),V5(4),V6
(5)はV1(0),V2(1),V7(6),V8
(7)よりも低いが、R3〜R6の値はR1,R2,R
7,R8の値と同じなので、V2〜V6間の抵抗分圧回
路から出力される階調電圧(V15〜V47)の出力線
には充分な電流を流すことが困難になる。That is, in the example shown in FIG. 12, the gradation reference voltage differences V3 (2), V4 (3), V5 (4), V6.
(5) is V1 (0), V2 (1), V7 (6), V8
Although lower than (7), the values of R3 to R6 are R1, R2, R
Since it is the same as the values of 7 and R8, it becomes difficult to flow a sufficient current through the output line of the gradation voltage (V15 to V47) output from the resistance voltage dividing circuit between V2 and V6.
【0040】本発明は、前記従来技術の問題点を解決す
るためになされたものであり、本発明の目的は、液晶表
示装置の階調電圧生成回路において、低消費電力と高画
質表示を可能とする液晶表示装置を提供することにあ
る。The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to enable low power consumption and high image quality display in a gradation voltage generating circuit of a liquid crystal display device. Another object of the present invention is to provide a liquid crystal display device.
【0041】本発明の前記目的並びにその他の目的及び
新規な特徴は、本明細書の記載及び添付図面によって明
らかにする。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
【0042】[0042]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記の通りである。Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.
【0043】(1)複数の階調基準電圧の各階調基準電
圧間を直列抵抗分圧回路により分圧して液晶層に印加す
る多階調の階調電圧を生成する液晶表示装置であって、
前記直列抵抗分圧回路の各階調基準電圧を印加する端子
間の抵抗値を、各階調基準電圧間の電位差にほぼ比例し
た抵抗値としたことを特徴とする。(1) A liquid crystal display device for generating a multi-gradation gray scale voltage applied to a liquid crystal layer by dividing a plurality of gray scale reference voltages between gray scale reference voltages by a series resistance voltage dividing circuit,
It is characterized in that a resistance value between terminals of the series resistance voltage dividing circuit to which each gradation reference voltage is applied is set to a resistance value substantially proportional to a potential difference between the gradation reference voltages.
【0044】(2)前記(1)の手段において、前記直
列抵抗分圧回路の各階調基準電圧を印加する端子間の抵
抗値を、各階調基準電圧間の電位差にほぼ比例した抵抗
値に変更するための切替手段を具備することを特徴とす
る。(2) In the means of (1) above, the resistance value between the terminals of the series resistance voltage dividing circuit to which each gradation reference voltage is applied is changed to a resistance value which is substantially proportional to the potential difference between the gradation reference voltages. It is characterized in that it is provided with a switching means for
【0045】(3)前記(1)の手段において、前記直
列抵抗分圧回路の各階調基準電圧を印加端する子間に複
数の直列抵抗回路を設け、前記複数の直列抵抗回路の中
から、各階調基準電圧間の電位差にほぼ比例した抵抗値
となる直列抵抗回路を選択するための選択手段を具備す
ることを特徴とする。(3) In the means of (1) above, a plurality of series resistance circuits are provided between the terminals of the series resistance voltage dividing circuit to which each gradation reference voltage is applied, and among the plurality of series resistance circuits, The present invention is characterized by including a selecting means for selecting a series resistance circuit having a resistance value substantially proportional to the potential difference between the gradation reference voltages.
【0046】前記各手段によれば、液晶層に印加する多
階調の階調電圧を生成する液晶表示装置の階調電圧生成
回路において、直列抵抗分圧回路の各階調基準電圧印加
端子間の抵抗値が、各階調基準電圧間の電圧差に比例し
ており、直列抵抗分圧回路の階調基準電圧印加端子のう
ちで、最大の階調基準電圧と最小の階調基準電圧電圧と
が印加される階調基準電圧印加端子以外からの電流の流
入、流出はほとんど0となり、ドレインドライバ11及
び電源回路13の消費電力を低減することが可能とな
り、液晶表示装置全体の消費電力を低減することが出来
る。According to each of the above means, in the gradation voltage generating circuit of the liquid crystal display device for generating the gradation voltages of multiple gradations to be applied to the liquid crystal layer, between the gradation reference voltage applying terminals of the series resistance voltage dividing circuit. The resistance value is proportional to the voltage difference between the gradation reference voltages, and the maximum gradation reference voltage and the minimum gradation reference voltage voltage among the gradation reference voltage application terminals of the series resistance voltage divider circuit are The inflow and outflow of current from other than the applied gradation reference voltage application terminal is almost zero, and the power consumption of the drain driver 11 and the power supply circuit 13 can be reduced, and the power consumption of the entire liquid crystal display device is reduced. You can
【0047】また、印加電圧に対する液晶層の透過率の
変化が大きい中間調表示の部分では、階調基準電圧印加
端子間の抵抗値を小さくするため、同一階調電圧を出力
するドレイン信号線の本数が多くなっても、階調電圧生
成回路の階調電圧の電圧変動が小さくなり、ドレインド
ライバ11が異なる、画素Pix間の境界で輝度差が発
生するのを抑えることが可能となり、液晶表示装置の表
示特性が向上する。Further, in the halftone display portion where the change in the transmittance of the liquid crystal layer with respect to the applied voltage is large, in order to reduce the resistance value between the gradation reference voltage application terminals, the drain signal lines that output the same gradation voltage are output. Even if the number of lines is large, the voltage variation of the gray scale voltage of the gray scale voltage generation circuit is small, and it is possible to suppress the occurrence of a brightness difference at the boundary between the pixels Pix with different drain drivers 11, and the liquid crystal display. The display characteristics of the device are improved.
【0048】[0048]
【発明の実施の形態】以下、本発明を適用したTFT液
晶表示装置の実施形態について図面を参照して詳細に説
明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a TFT liquid crystal display device to which the present invention is applied will be described below in detail with reference to the drawings.
【0049】なお、実施形態を説明するための全図にお
いて、同一機能を有するものは同一符号を付け、その繰
り返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.
【0050】以下、本発明が適用されるTFT液晶表示
装置構成は、前記図8に示すTFT液晶表示装置と同じ
であるので説明は省略する。The structure of the TFT liquid crystal display device to which the present invention is applied is the same as that of the TFT liquid crystal display device shown in FIG.
【0051】〔実施形態1〕図1は、本発明の一実施形
態(実施形態1)である液晶表示装置のドレインドライ
バ11の階調電圧生成回路を示す図である。[Embodiment 1] FIG. 1 is a diagram showing a gradation voltage generating circuit of a drain driver 11 of a liquid crystal display device which is an embodiment (Embodiment 1) of the present invention.
【0052】本実施例1の階調電圧生成回路は、前記図
12に示す階調電圧生成回路と同じく、内部電源回路1
3から入力された9値の階調基準電圧(V0−V8)の
各階調基準電圧間を、直列抵抗分圧回路1により8等分
して64階調分の階調電圧を生成するものである。The gray scale voltage generation circuit of the first embodiment is similar to the gray scale voltage generation circuit shown in FIG.
A series resistance voltage dividing circuit 1 divides each of the 9-valued gradation reference voltages (V0-V8) input from 3 into 8 equal parts to generate 64 gradation voltages. is there.
【0053】ここで、9値の階調基準電圧(V0−V
8)の階調基準電圧Vnと階調基準電圧Vn−1(n=
1〜8)の電圧差をVn(n−1)と表記し、直列抵抗
分圧回路1の階調基準電圧Vnと階調基準電圧Vn−1
(n=1〜8)の階調基準印加端子間の合成抵抗値をR
nと表記する。Here, a nine-value gradation reference voltage (V0-V
8) gradation reference voltage Vn and gradation reference voltage Vn-1 (n =
The voltage difference of 1 to 8) is expressed as Vn (n-1), and the gradation reference voltage Vn and the gradation reference voltage Vn-1 of the series resistance voltage dividing circuit 1 are represented.
The combined resistance value between the gradation reference application terminals (n = 1 to 8) is R
Notated as n.
【0054】本実施形態1の階調電圧生成回路では、R
8:R7:R6:R5:R4:R3:R2:R1=V8
(7):V7(6):V6(5):V5(4):V4
(3):V3(2):V2(1):V1(0)である。In the gradation voltage generating circuit of the first embodiment, R
8: R7: R6: R5: R4: R3: R2: R1 = V8
(7): V7 (6): V6 (5): V5 (4): V4
(3): V3 (2): V2 (1): V1 (0).
【0055】したがって、直列抵抗分圧回路1を流れる
電流は、一定の電流値(Vn(n−1)/Rn=一定の
電流値)となり、本実施形態1の階調電圧生成回路で
は、最大の階調基準電圧と最小の階調基準電圧電圧とが
印加される直列抵抗分圧回路1の階調基準電圧(V0お
よびV8)印加端子以外からの電流の流入、流出はほと
んど0となり、ドレインドライバの消費電力を低減する
ことが可能となり、それにより、液晶表示装置の消費電
力を低減することが可能となる。Therefore, the current flowing through the series resistance voltage dividing circuit 1 has a constant current value (Vn (n-1) / Rn = constant current value), and in the gradation voltage generating circuit of the first embodiment, the maximum value. The gradation reference voltage (V0 and V8) of the series resistance voltage dividing circuit 1 to which the gradation reference voltage and the minimum gradation reference voltage are applied is almost zero, and the current is almost 0. It is possible to reduce the power consumption of the driver, and thus it is possible to reduce the power consumption of the liquid crystal display device.
【0056】図2は図1に示す直列抵抗分圧回路1に具
体的な抵抗値を当てはめて本発明を実施した例を示す図
である。FIG. 2 is a diagram showing an example in which the present invention is implemented by applying a specific resistance value to the series resistance voltage dividing circuit 1 shown in FIG.
【0057】図2に記載の各抵抗の抵抗値は、図3に示
す、3Vで透過率がほぼ0になる液晶を用いた場合の電
圧透過率曲線に階調基準電圧V0〜V8を合わせた例で
ある。図3に記載のV0’〜V8’は図2の基準電圧V
0〜V8に対応している。The resistance values of the resistors shown in FIG. 2 are obtained by combining the gradation reference voltages V0 to V8 with the voltage transmittance curve shown in FIG. 3 when the liquid crystal having a transmittance of 0 at 3V is used. Here is an example. V0 ′ to V8 ′ shown in FIG. 3 are reference voltages V of FIG.
It corresponds to 0 to V8.
【0058】図2に示す具体的な実施例では各階調基準
電圧端子間の抵抗R1〜R8に流れる電流は何れも1.
3mAとなり、V0,V8以外の階調基準電圧を印加す
る端子には電流が流れず、直列抵抗分圧回路1で消費す
る電力は、1.3mAの電流に起因するもののみで、最
も低くなる。In the specific embodiment shown in FIG. 2, the currents flowing through the resistors R1 to R8 between the gradation reference voltage terminals are all 1.
3 mA, no current flows through the terminals to which the gradation reference voltage other than V0 and V8 is applied, and the power consumed by the series resistance voltage dividing circuit 1 is only due to the current of 1.3 mA and is the lowest. .
【0059】また図2に示す実施例においては、V6
2,V63の階調電圧を高く設定して黒の表示をより黒
くしてコントラストを高める為に、最高電圧V8の端子
に近い側の抵抗R8の内訳はR88,R87の値がその
他の抵抗R81〜R86の抵抗値よりも高く設定されて
いる。In the embodiment shown in FIG. 2, V6
In order to increase the contrast by setting the gradation voltages of V2 and V63 to be high and making the black display more black, the breakdown of the resistor R8 on the side closer to the terminal of the highest voltage V8 is that the values of R88 and R87 are other resistors R81. The resistance value is set to be higher than the resistance value of R86.
【0060】同様に図2に示す実施例においては、V0
0,V01の階調電圧を低く設定して白の表示をより白
くしてコントラストを高める為に、最低電圧V0の端子
に近い側の抵抗R1の内訳はR11,R12の値がその
他の抵抗R13〜R17の抵抗値よりも高く設定されて
いる。Similarly, in the embodiment shown in FIG. 2, V0
In order to set the gradation voltages of 0 and V01 low to make the white display whiter and increase the contrast, the breakdown of the resistance R1 on the side closer to the terminal of the lowest voltage V0 is that the values of R11 and R12 are other resistances R13. Is set higher than the resistance value of R17.
【0061】なお図3に記載のV0’〜V8’は、実際
の液晶層(図示せず)に加わる電圧で示している為、図
2の基準電圧V0〜V8に比べ変動分(0.8V)だけ
シフトしている。Since V0 'to V8' shown in FIG. 3 are indicated by the voltage applied to the actual liquid crystal layer (not shown), the variation (0.8 V) is different from the reference voltage V0 to V8 in FIG. ) Just shifted.
【0062】実際の液晶層に加わる電圧が図2の基準電
圧V0〜V8に比べシフトする理由としてはゲート電圧
波形の画素電極ITOへの飛込みが考えられる。実際の
画素には図9に示すようにゲートG、画素電極ITO間
には寄生容量Cgsがあり、図10に示す駆動方法でゲ
ート電圧波形がGate OnからGate Offに
変化すると、その変化に伴うパルスがCgsを介して画
素電極ITOに印加されるため液晶層に加わる電圧のシ
フトが起こる。The reason why the voltage actually applied to the liquid crystal layer shifts as compared with the reference voltages V0 to V8 in FIG. 2 is that the gate voltage waveform jumps into the pixel electrode ITO. As shown in FIG. 9, the actual pixel has a parasitic capacitance Cgs between the gate G and the pixel electrode ITO. When the gate voltage waveform changes from Gate On to Gate Off by the driving method shown in FIG. Since the pulse is applied to the pixel electrode ITO via Cgs, the voltage applied to the liquid crystal layer shifts.
【0063】従って電源回路13の階調基準電圧V0〜
V8を設定する場合は予め液晶層に加わる電圧のシフト
を考慮に入れる必要がある。Therefore, the gradation reference voltages V0 to V0 of the power supply circuit 13
When V8 is set, it is necessary to take into consideration the shift of the voltage applied to the liquid crystal layer in advance.
【0064】なお、図2、図3に示す実施例は液晶に印
加する電圧が負極性の場合を示したものであり、電圧の
シフト分を階調基準電圧に加える場合を示している。し
かし液晶に印加する電圧が正極性の場合は電圧のシフト
分を階調基準電圧から引いた値が実際の液晶層に印加さ
れる電圧になる為、図13に示す階調基準電圧生成回路
は正極性と負極性の2種類必要になる。The embodiments shown in FIGS. 2 and 3 show the case where the voltage applied to the liquid crystal has a negative polarity, and shows the case where the shift amount of the voltage is applied to the gradation reference voltage. However, when the voltage applied to the liquid crystal has a positive polarity, the value obtained by subtracting the shift amount of the voltage from the gradation reference voltage becomes the actual voltage applied to the liquid crystal layer, and therefore the gradation reference voltage generation circuit shown in FIG. Two types of positive polarity and negative polarity are required.
【0065】同様にドレインドライバ11内の階調電圧
生成回路も正極性と負極性の2種類の直列抵抗分圧回路
1を有し、極性信号に応じて切替ている。Similarly, the gradation voltage generating circuit in the drain driver 11 also has two kinds of series resistance voltage dividing circuits 1 of positive polarity and negative polarity, which are switched according to the polarity signal.
【0066】なお、本実施形態1の階調基準電圧生成回
路では、直列抵抗分圧回路1の各階調基準電圧印加端子
間の抵抗値を、各階調基準電圧間の電位差に完全に比例
した抵抗値としているが、完全に比例していなくても、
同様な効果を有する。In the gray scale reference voltage generating circuit of the first embodiment, the resistance value between the gray scale reference voltage applying terminals of the series resistance voltage dividing circuit 1 is a resistor which is completely proportional to the potential difference between the gray scale reference voltages. Although it is a value, even if it is not perfectly proportional,
Has a similar effect.
【0067】すなわちVn(n−1)/Rnの値が完全
に一致していなくとも、その値のばらつきが特定の範囲
内にあれば、特定の範囲外のものに比べ、余分な消費電
力の発生を抑えることが出来る。That is, even if the value of Vn (n-1) / Rn does not completely match, if the variation of the value is within the specific range, extra power consumption is required as compared with that outside the specific range. Occurrence can be suppressed.
【0068】直列抵抗分圧回路1は半導体集積回路の内
部に作られる。一般に半導体集積回路内に作られる抵抗
にはばらつきがあり、抵抗に半導体の拡散抵抗を用いた
場合、抵抗値は±20%のばらつきを生じる。なお出来
上がった半導体集積回路を選別して抵抗値を±10%の
ばらつきにすることも可能であるが、半導体集積回路の
歩留が下がるのでドレインドライバ11のコストが高く
なる。従って図1に示した直列抵抗分圧回路1を用いる
液晶表示装置で、Vn(n−1)/Rnの値を完全に一
致させるのは理想的であるが、実用的ではない。The series resistance voltage dividing circuit 1 is formed inside a semiconductor integrated circuit. Generally, there is a variation in resistance created in a semiconductor integrated circuit, and when a semiconductor diffused resistor is used as the resistance, the resistance value varies by ± 20%. Although it is possible to select the finished semiconductor integrated circuits and set the resistance values to have a variation of ± 10%, the cost of the drain driver 11 increases because the yield of the semiconductor integrated circuits decreases. Therefore, in the liquid crystal display device using the series resistance voltage dividing circuit 1 shown in FIG. 1, it is ideal that the values of Vn (n-1) / Rn are perfectly matched, but it is not practical.
【0069】図2に示す実施例で、最も階調表示に影響
を与える、抵抗R3が±20%ばらつくことを考える
と、Vn(n−1)/Rnの値即ちR3に流れる電流は
±0.3mA(±23%)変動する。R4もR3と同じ
抵抗値なのでR4に流れる電流も±0.3mA変動す
る。R3とR4に流れる電流値の差が最も大きくなった
場合を考えると、端子V3には±0.6mAの電流が流
れ直列抵抗分圧回路1及び電源回路13の消費電力が増
加する。In the embodiment shown in FIG. 2, considering that the resistance R3, which affects the gradation display most, varies by ± 20%, the value of Vn (n-1) / Rn, that is, the current flowing through R3 is ± 0. It fluctuates by 0.3 mA (± 23%). Since R4 has the same resistance value as R3, the current flowing through R4 also fluctuates by ± 0.3 mA. Considering the case where the difference between the current values flowing through R3 and R4 is the largest, a current of ± 0.6 mA flows through the terminal V3, and the power consumption of the series resistance voltage dividing circuit 1 and the power supply circuit 13 increases.
【0070】しかし直列抵抗分圧回路1の抵抗値に±2
0%のばらつきがあっても、本実施形態を適用すればV
1〜V7に流れる電流を±0.6mAの範囲内に抑える
ことが出来るので、ドレインドライバ11及び電源回路
13の消費電力を低く抑えることが出来、ドレインドラ
イバ11のコストが高くなく実用的である。However, the resistance value of the series resistance voltage dividing circuit 1 is ± 2
Even if there is a variation of 0%, if the present embodiment is applied, V
Since the current flowing from 1 to V7 can be suppressed within the range of ± 0.6 mA, the power consumption of the drain driver 11 and the power supply circuit 13 can be suppressed to be low, and the cost of the drain driver 11 is not high and is practical. .
【0071】さらに図2に示す実施例で直列抵抗分圧回
路1のばらつきを±10%にすると、R3、R4に流れ
る電流は±0.2mA(±15%)の変動に抑えること
が出来る。従ってR3とR4に流れる電流値の差が最大
の場合を考えると、端子V3には±0.4mAの電流が
流れ直列抵抗分圧回路1及び電源回路13の消費電力の
増加をさらに小さくすることが出来、最も好ましい。Further, in the embodiment shown in FIG. 2, if the variation of the series resistance voltage dividing circuit 1 is set to ± 10%, the current flowing through R3 and R4 can be suppressed to a fluctuation of ± 0.2 mA (± 15%). Therefore, considering the case where the difference between the current values flowing through R3 and R4 is the maximum, a current of ± 0.4 mA flows through the terminal V3 and the increase in power consumption of the series resistance voltage dividing circuit 1 and the power supply circuit 13 should be further reduced. Is possible and is most preferable.
【0072】なお本実施形態では電源回路のV1〜V7
の出力端子に流れる電流は低く抑えることが出来る為、
図13に示す構成の電源回路13を用いた場合には、V
1〜V7を出力するバッファ回路OP1〜OP7はV
0,V8を出力するバッファ回路OP0〜OP8に比べ
出力インピーダンスが高くても良く、安価なものが使用
出来、電源回路13のコストを下げることが出来る。In this embodiment, V1 to V7 of the power supply circuit
Since the current flowing through the output terminal of can be kept low,
When the power supply circuit 13 having the configuration shown in FIG. 13 is used, V
The buffer circuits OP1 to OP7 that output 1 to V7 are V
The output impedance may be higher than that of the buffer circuits OP0 to OP8 that output 0 and V8, an inexpensive one can be used, and the cost of the power supply circuit 13 can be reduced.
【0073】さらに本実施形態においては、バッファ回
路OP1〜OP7を除いて、V1〜V7の出力は直接抵
抗分圧回路から得ることも可能であり、電源回路13の
コストを更に下げることが出来る。Further, in the present embodiment, the outputs of V1 to V7 can be directly obtained from the resistance voltage dividing circuit except the buffer circuits OP1 to OP7, and the cost of the power supply circuit 13 can be further reduced.
【0074】また本実施形態によれば、図1に示すよう
に中間調を表示する階調基準電圧差V4(3)、V5
(4)は、電圧差が小さいため、直列抵抗分圧回路1の
階調基準電圧印加端子間の抵抗値R5、R4も小さくな
る。Further, according to the present embodiment, as shown in FIG. 1, the gradation reference voltage differences V4 (3) and V5 for displaying the halftone are displayed.
In (4), since the voltage difference is small, the resistance values R5 and R4 between the gradation reference voltage applying terminals of the series resistance voltage dividing circuit 1 are also small.
【0075】すなわち図2に示す具体的実施例で見る
と、階調基準電圧差V3(2),V4(3),V5
(4),V6(5)はV1(0),V2(1),V7
(6),V8(7)よりも低いが、R3〜R6の値はR
1,R2,R7,R8の値よりも充分低いので、V2〜
V6間の抵抗分圧回路から出力される階調電圧(V15
〜V47)の出力線には充分な電流を流すことが可能に
なる。That is, in the concrete example shown in FIG. 2, the gradation reference voltage differences V3 (2), V4 (3), V5.
(4), V6 (5) are V1 (0), V2 (1), V7
(6), lower than V8 (7), but the values of R3 to R6 are R
Since it is sufficiently lower than the values of 1, R2, R7 and R8, V2
The gradation voltage (V15
It is possible to pass a sufficient current through the output line of V47.
【0076】これにより、同一階調電圧を出力するドレ
イン線Dnの本数が多くなっても、階調電圧生成回路の
出力する階調電圧の電圧変動が小さくなり、ドレインド
ライバ11が異なる、画素間の輝度に差が発生するのを
抑えることが可能となる。As a result, even if the number of drain lines Dn that output the same gray scale voltage increases, the voltage variation of the gray scale voltage output by the gray scale voltage generation circuit becomes small, and the drain drivers 11 are different and inter-pixel. It is possible to suppress the occurrence of a difference in luminance.
【0077】したがって、本実施形態1の階調電圧生成
回路を使用するこにより、高画質で低消費電力の液晶表
示装置を構成することが可能となる。Therefore, by using the gradation voltage generating circuit of the first embodiment, it becomes possible to construct a liquid crystal display device with high image quality and low power consumption.
【0078】〔実施形態2〕図4、図5は、本発明の他
の実施形態(実施形態2)である液晶表示装置のドレイ
ンドライバの階調電圧生成回路を示す図である。[Embodiment 2] FIGS. 4 and 5 are diagrams showing a gray scale voltage generation circuit of a drain driver of a liquid crystal display device according to another embodiment (Embodiment 2) of the present invention.
【0079】一般に図14に示す電圧透過率特性は液晶
層の材料によって異なる。Generally, the voltage transmittance characteristics shown in FIG. 14 differ depending on the material of the liquid crystal layer.
【0080】従って電源回路13の階調基準電圧は液晶
層の電圧透過率特性に合わせて設定され、ドレインドラ
イバ11内の階調電圧生成回路も電圧透過率特性に合わ
せて設定しなければならないので、ドレインドライバ1
1の汎用性がなく、各液晶表示パネル毎に専用のドレイ
ンドライバ11を用いなければならず、液晶表示装置の
コストが高くなる問題がある。Therefore, the gradation reference voltage of the power supply circuit 13 is set in accordance with the voltage transmittance characteristic of the liquid crystal layer, and the gradation voltage generation circuit in the drain driver 11 must also be set in accordance with the voltage transmittance characteristic. , Drain driver 1
However, there is a problem that the cost of the liquid crystal display device is increased because the drain driver 11 must be used for each liquid crystal display panel.
【0081】本実施形態2は、前記実施形態1をより具
体的にした実施形態であり、液晶表示パネルに合わせて
容易にドレインドライバ11の階調電圧生成回路の階調
電圧の設定値を変更可能にした実施形態である。The second embodiment is a more specific embodiment of the first embodiment, and easily changes the set value of the grayscale voltage of the grayscale voltage generation circuit of the drain driver 11 according to the liquid crystal display panel. This is a possible embodiment.
【0082】本実施形態2の階調基準電圧生成回路で
は、半導体製造段階において図4に示すように、各階調
基準電圧(V1〜V7)の階調基準電圧印加端子を、直
列抵抗分圧回路1のいくつかの点(A、B、C)へヒュ
ーズ32を介して接続する。In the gray scale reference voltage generating circuit of the second embodiment, as shown in FIG. 4 in the semiconductor manufacturing stage, the gray scale reference voltage applying terminals of the respective gray scale reference voltages (V1 to V7) are connected to the series resistance voltage dividing circuit. 1 to several points (A, B, C) via a fuse 32.
【0083】この場合、A、B、Cの各点は、実際に使
用する可能性がある分圧値となるように選択する。In this case, the points A, B and C are selected so as to have the partial pressure values which may be actually used.
【0084】本実施形態2の階調基準電圧生成回路を、
実際に使用する時に、各階調基準電圧(V0〜V8)と
して所定の階調基準電圧を印加すると、各階調基準電圧
の電圧差に比例した抵抗値のところに接続されたヒュー
ズ32には電流が流れず、ヒューズ32は溶断されな
い。The gradation reference voltage generating circuit of the second embodiment is
When a predetermined gradation reference voltage is applied as each gradation reference voltage (V0 to V8) during actual use, a current is supplied to the fuse 32 connected to the resistance value proportional to the voltage difference between the gradation reference voltages. It does not flow and the fuse 32 is not blown.
【0085】しかしながら、それ以外のヒューズ32に
は電流が流れ、ヒューズ32が溶断され、これにより、
直列抵抗分圧回路1の各階調基準電圧印加端子間の抵抗
値は、各階調基準電圧の電圧差に比例した抵抗値とな
る。However, a current flows through the other fuses 32, and the fuses 32 are blown.
The resistance value between the gradation reference voltage applying terminals of the series resistance voltage dividing circuit 1 becomes a resistance value proportional to the voltage difference between the gradation reference voltages.
【0086】また、図5に示すように、直列抵抗分圧回
路1の出力スイッチ3が接続されている側にも、同様に
各階調電圧出力端子4をヒューズ2を介して、直列抵抗
分圧回路1のいくつかの点(D、E、F)へ接続する。Further, as shown in FIG. 5, on the side to which the output switch 3 of the series resistance voltage dividing circuit 1 is connected, similarly, each gradation voltage output terminal 4 is connected via the fuse 2 to the series resistance voltage dividing terminal 4. Connect to several points (D, E, F) of circuit 1.
【0087】表示用データに基づき、所定階調、例え
ば、階調V62を選択した後、階調基準電圧V8,V7
の階調基準電圧印加端子と階調電圧出力端子4に所定の
電圧を印加する。After selecting a predetermined gradation, for example, the gradation V62, based on the display data, the gradation reference voltages V8 and V7 are selected.
A predetermined voltage is applied to the gradation reference voltage applying terminal and the gradation voltage output terminal 4.
【0088】このとき、階調電圧出力端子4には溶断し
たくないヒューズ2が接続されている点の抵抗値、例え
ば、Eの点に対応した電圧(0.8×V8(7))を印
加する。At this time, the gradation voltage output terminal 4 is set to the resistance value at the point where the fuse 2 which is not desired to be blown is connected, for example, the voltage (0.8 × V8 (7)) corresponding to the point E. Apply.
【0089】このように、本実施形態2の階調電圧生成
回路では、出力スイッチ3が接続されている側のヒュー
ズ2を溶断するときには、各階調基準電圧の電圧差のみ
実使用時に対応した値とし、絶対値は実使用時より高い
電圧とする。As described above, in the grayscale voltage generation circuit of the second embodiment, when the fuse 2 on the side to which the output switch 3 is connected is blown, only the voltage difference between the grayscale reference voltages corresponds to the value in actual use. The absolute value shall be higher than that in actual use.
【0090】これにより、本実施形態2の階調電圧生成
回路では、実使用時にヒューズ2が溶断されない電流を
流すことができる。As a result, in the gradation voltage generating circuit of the second embodiment, it is possible to flow a current that does not blow the fuse 2 during actual use.
【0091】以上説明したように、本実施形態2では、
ドレインドライバ11に汎用性を持たせることが出来、
前記実施形態1と同様、高画質で低消費電力である液晶
表示装置を様々な液晶表示パネルの特性に対応して、容
易に実現することが可能となる。As described above, in the second embodiment,
It is possible to give the drain driver 11 versatility,
Similar to the first embodiment, it is possible to easily realize a liquid crystal display device having high image quality and low power consumption, corresponding to various characteristics of the liquid crystal display panel.
【0092】〔実施形態3〕図6は、本発明の他の実施
形態(実施形態3)である液晶表示装置のドレインドラ
イバの階調電圧生成回路を示す図である。[Third Embodiment] FIG. 6 is a diagram showing a gray scale voltage generation circuit of a drain driver of a liquid crystal display device according to another embodiment (third embodiment) of the present invention.
【0093】本実施形態3も、前記実施形態1をより具
体的にした実施形態であり、液晶表示パネルに合わせて
容易にドレインドライバ11の階調電圧生成回路の階調
電圧の設定値を変更可能にした実施形態である。The third embodiment is also a more specific embodiment of the first embodiment, and easily changes the set value of the grayscale voltage of the grayscale voltage generation circuit of the drain driver 11 according to the liquid crystal display panel. This is a possible embodiment.
【0094】本実施形態3の階調電圧生成回路は、直列
抵抗分圧回路1の各階調基準電圧(V0−V8)の階調
基準電圧印加端子間に、何種類かの複数の直列抵抗回路
(101,102,103)を設けておき、実使用時
に、各階調基準電圧の電圧差の比に近い抵抗比となる直
列抵抗回路(101,102,103)を、切替え信号
により選択する。The gradation voltage generating circuit according to the third embodiment includes several kinds of series resistance circuits between the gradation reference voltage application terminals of the gradation reference voltages (V0-V8) of the series resistance voltage dividing circuit 1. (101, 102, 103) are provided, and the series resistance circuit (101, 102, 103) having a resistance ratio close to the ratio of the voltage difference of each gradation reference voltage is selected by the switching signal in actual use.
【0095】また、同じく、切替え信号により切替えス
イッチ5を切り替えて、各直列抵抗回路(101,10
2,103)からの階調電圧を各階調電圧出力端子4に
出力するようにしたものである。Similarly, the changeover switch 5 is changed over by the changeover signal to change the series resistance circuits (101, 10).
2, 103) is output to each gradation voltage output terminal 4.
【0096】このとき切替え信号は、表示制御装置10
内のレジスタ、EPROM、あるいはコンピュータと接
続するインタフェースコネクタの専用の入力端子等から
各ドレインドライバ11に供給されるようにしておく。At this time, the switching signal is the display control device 10
Each drain driver 11 is supplied from the internal register, EPROM, or a dedicated input terminal of an interface connector connected to a computer.
【0097】これにより、実使用時の各階調基準電圧の
電圧差の比に近い抵抗比を有する直列抵抗分圧回路を容
易に実現でき、本実施形態3の階調電圧生成回路でも、
ドレインドライバ11に汎用性を持たせることが出来、
前記実施形態1と同様、高画質で低消費電力である液晶
表示装置を様々な液晶表示パネルの特性に対応して、容
易に実現することが可能となる。With this, it is possible to easily realize a series resistance voltage dividing circuit having a resistance ratio close to the ratio of the voltage difference between the gradation reference voltages in actual use, and the gradation voltage generating circuit of the third embodiment also
It is possible to give the drain driver 11 versatility,
Similar to the first embodiment, it is possible to easily realize a liquid crystal display device having high image quality and low power consumption, corresponding to various characteristics of the liquid crystal display panel.
【0098】〔実施形態4〕図7は、本発明の他の実施
形態(実施形態4)である液晶表示装置のドレインドラ
イバの階調電圧生成回路を示す図である。[Fourth Embodiment] FIG. 7 is a diagram showing a grayscale voltage generation circuit of a drain driver of a liquid crystal display device according to another embodiment (fourth embodiment) of the present invention.
【0099】本実施形態4も、前記実施形態1をより具
体的にした実施形態であり、液晶表示パネルに合わせて
容易にドレインドライバ11の階調電圧生成回路の階調
電圧の設定値を変更可能にした実施形態である。The fourth embodiment is also a more specific embodiment of the first embodiment, and easily changes the set value of the grayscale voltage of the grayscale voltage generation circuit of the drain driver 11 according to the liquid crystal display panel. This is a possible embodiment.
【0100】本実施形態4の階調電圧生成回路でも、前
記実施形態3と同様、直列抵抗分圧回路1の各階調基準
電圧(V0−V8)の階調基準電圧印加端子間に、何種
類かの複数の直列抵抗回路(101,102,103)
を設けておき、各階調基準電圧の電圧差の比に近い抵抗
比となる直列抵抗回路(101,102,103)を、
半導体製造工程中の金属配線層等のみの変更により選択
する。In the gray scale voltage generation circuit of the fourth embodiment, as in the third embodiment, any number of gray scale reference voltage application terminals of the gray scale reference voltages (V0-V8) of the series resistance voltage dividing circuit 1 can be used. A plurality of series resistance circuits (101, 102, 103)
And a series resistance circuit (101, 102, 103) having a resistance ratio close to the ratio of the voltage difference of each gradation reference voltage,
It is selected by changing only the metal wiring layer during the semiconductor manufacturing process.
【0101】また、同じく、半導体製造工程中の金属配
線層等のみの変更により切替え手段6を切り替えて、各
直列抵抗回路(101,102,103)からの階調電
圧を各階調電圧出力端子4に出力するようにしたもので
ある。Similarly, the switching means 6 is switched by changing only the metal wiring layer or the like during the semiconductor manufacturing process, and the grayscale voltage from each series resistance circuit (101, 102, 103) is output to each grayscale voltage output terminal 4. It is designed to be output to.
【0102】これにより、実使用時の各階調基準電圧の
電圧差の比に近い抵抗比を有する直列抵抗分圧回路を容
易に実現でき、本実施形態4の階調電圧生成回路でも、
ドレインドライバ11に汎用性を持たせることが出来、
前記実施形態1と同様、高画質で低消費電力である液晶
表示装置を様々な液晶表示パネルの特性に対応して、容
易に実現することが可能となる。With this, it is possible to easily realize the series resistance voltage dividing circuit having a resistance ratio close to the ratio of the voltage difference between the gradation reference voltages in actual use, and the gradation voltage generating circuit of the fourth embodiment also
It is possible to give the drain driver 11 versatility,
Similar to the first embodiment, it is possible to easily realize a liquid crystal display device having high image quality and low power consumption, corresponding to various characteristics of the liquid crystal display panel.
【0103】なお、前記各実施形態では、液晶表示装置
に本発明を適用した場合について説明したが、これに限
定されず、本発明は、液晶表示モジュール等のすべての
液晶表示装置に適用できることはいうまでもない。In each of the above embodiments, the case where the present invention is applied to a liquid crystal display device has been described, but the present invention is not limited to this, and the present invention can be applied to all liquid crystal display devices such as liquid crystal display modules. Needless to say.
【0104】以上、本発明を実施形態に基づき具体的に
説明したが、本発明は、前記実施形態に限定されるもの
ではなく、その要旨を逸脱しない範囲で種々変更し得る
ことは言うまでもない。The present invention has been specifically described above based on the embodiments. However, it goes without saying that the present invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention.
【0105】[0105]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば下記
の通りである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【0106】(1)本発明によれば、液晶層に印加する
多階調の階調電圧を生成する液晶表示装置の階調電圧生
成回路において、直列抵抗分圧回路1の各階調基準電圧
印加端子間の抵抗値が、各階調基準電圧間の電圧差に比
例しており、直列抵抗分圧回路の階調基準電圧印加端子
のうちで、最大の階調基準電圧と最小の階調基準電圧電
圧とが印加される階調基準電圧印加端子以外からの電流
の流入、流出はほとんど0となり、ドレインドレイバの
消費電力を低減することが可能となり、これにより、液
晶表示装置の消費電力を低減することが可能となる。(1) According to the present invention, in the gradation voltage generation circuit of the liquid crystal display device for generating the gradation voltages of multiple gradations applied to the liquid crystal layer, each gradation reference voltage of the series resistance voltage dividing circuit 1 is applied. The resistance value between the terminals is proportional to the voltage difference between the gradation reference voltages, and the maximum gradation reference voltage and the minimum gradation reference voltage among the gradation reference voltage application terminals of the series resistance voltage divider circuit. The inflow and outflow of the current from other than the gradation reference voltage applying terminal to which the voltage is applied becomes almost zero, and the power consumption of the drain driver can be reduced, thereby reducing the power consumption of the liquid crystal display device. It becomes possible to do.
【0107】(2)本発明によれば、印加電圧に対する
液晶層の透過率の変化が大きい中間調表示の部分では、
階調基準電圧印加端子間の抵抗値が小さいため、同一階
調電圧を出力するドレイン信号線の本数が多くなって
も、階調基準電圧生成回路の階調電圧の電圧変動が小さ
くなり、異なるドレインドライバ11間で表示画面の輝
度差の発生を抑えることが可能となる。(2) According to the present invention, in the halftone display portion where the change in the transmittance of the liquid crystal layer with respect to the applied voltage is large,
Since the resistance value between the gradation reference voltage applying terminals is small, even if the number of drain signal lines that output the same gradation voltage increases, the voltage fluctuation of the gradation voltage of the gradation reference voltage generation circuit becomes small, which is different. It is possible to suppress the occurrence of a brightness difference on the display screen between the drain drivers 11.
【図1】本発明の一実施形態(実施形態1)である液晶
表示装置のドレインドレイバの階調電圧生成回路を示す
図である。FIG. 1 is a diagram showing a grayscale voltage generation circuit of a drain driver of a liquid crystal display device which is an embodiment (first embodiment) of the present invention.
【図2】本発明の一実施形態(実施形態1)である液晶
表示装置のドレインドレイバの階調電圧生成回路に具体
的な抵抗値及び階調基準電圧値を当てはめた図である。FIG. 2 is a diagram in which specific resistance values and grayscale reference voltage values are applied to the grayscale voltage generation circuit of the drain driver of the liquid crystal display device according to one embodiment (first embodiment) of the present invention.
【図3】図2に示した階調基準電圧と液晶表示素子の透
過率との関係を示す図である。FIG. 3 is a diagram showing the relationship between the gray scale reference voltage shown in FIG. 2 and the transmittance of the liquid crystal display element.
【図4】本発明の他の実施形態(実施形態2)である液
晶表示装置のドレインドレイバの階調電圧生成回路を示
す図である。FIG. 4 is a diagram showing a grayscale voltage generation circuit of a drain driver of a liquid crystal display device according to another embodiment (second embodiment) of the present invention.
【図5】本発明の他の実施形態(実施形態2)である液
晶表示装置のドレインドレイバの階調電圧生成回路を示
す図である。FIG. 5 is a diagram showing a grayscale voltage generation circuit of a drain driver of a liquid crystal display device according to another embodiment (Embodiment 2) of the present invention.
【図6】本発明の他の実施形態(実施形態3)である液
晶表示装置のドレインドレイバの階調電圧生成回路を示
す図である。FIG. 6 is a diagram showing a grayscale voltage generation circuit of a drain driver of a liquid crystal display device according to another embodiment (Embodiment 3) of the present invention.
【図7】本発明の他の実施形態(実施形態4)である液
晶表示装置のドレインドレイバの階調電圧生成回路を示
す図である。FIG. 7 is a diagram showing a grayscale voltage generation circuit of a drain driver of a liquid crystal display device according to another embodiment (Embodiment 4) of the present invention.
【図8】TFT液晶表示装置の概略構成を示すブロック
図である。FIG. 8 is a block diagram showing a schematic configuration of a TFT liquid crystal display device.
【図9】TFT液晶表示装置の画素の等価回路を示す図
である。FIG. 9 is a diagram showing an equivalent circuit of a pixel of a TFT liquid crystal display device.
【図10】TFT液晶表示装置の画素に印加する電圧の
タイミング関係を示す図である。FIG. 10 is a diagram showing a timing relationship of voltages applied to pixels of a TFT liquid crystal display device.
【図11】ドレインドライバの概略構成を示すブロック
図である。FIG. 11 is a block diagram showing a schematic configuration of a drain driver.
【図12】従来のドレインドライバ11の階調電圧生成
回路を示す図である。FIG. 12 is a diagram showing a grayscale voltage generation circuit of a conventional drain driver 11.
【図13】電源回路の階調基準電圧生成部の回路図であ
る。FIG. 13 is a circuit diagram of a gradation reference voltage generation unit of a power supply circuit.
【図14】図11に示した、階調基準電圧と液晶表示素
子の透過率との関係を示す図である。14 is a diagram showing the relationship between the gray scale reference voltage and the transmittance of the liquid crystal display element shown in FIG.
TFT−LCD…TFT液晶表示パネル、1…直列抵抗
分圧回路、2,32…ヒューズ、3…スイッチ、4…階
調電圧出力端子、5…切替えスイッチ、6,7…切替え
手段、10…表示制御装置、11…ドレインドライバ、
12…ゲートドライバ、13…電源回路、101,10
2,103…直列抵抗回路。TFT-LCD ... TFT liquid crystal display panel, 1 ... Series resistance voltage dividing circuit, 2, 32 ... Fuse, 3 ... Switch, 4 ... Grayscale voltage output terminal, 5 ... Changeover switch, 6, 7 ... Changeover means, 10 ... Display Controller, 11 ... Drain driver,
12 ... Gate driver, 13 ... Power supply circuit, 101, 10
2, 103 ... Series resistance circuit.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 岩▲崎▼ 伸一 千葉県茂原市早野3681番地 日立デバイス エンジニアリング株式会社内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Iwa ▲ Saki ▼ Shinichi 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd.
Claims (7)
のソースに電気的に接続された画素電極とを有する画素
が複数配置された液晶表示パネルと、上記薄膜トランジ
スタのドレインに、複数の電位の階調電圧から選択し
た、電圧を出力するドレインドライバと、上記ドレイン
ドライバに複数の電位の階調基準電圧を出力する電源回
路と、上記薄膜トランジスタのゲートに、上記画素を選
択する、電圧を出力するゲートドライバとを有する液晶
表示装置であって、 上記ドレインドライバは階調電圧生成回路を有し、上記
階調電圧生成回路は、上記複数の階調基準電圧の電位間
を、抵抗を直列に接続した分圧回路により複数の電位に
分圧し、上記複数の電位の階調電圧を生成し、 上記分圧回路の各階調基準電圧の電位間の抵抗値を、各
階調基準電圧間の電位差にほぼ比例した抵抗値に設定し
たことを特徴とする液晶表示装置。1. A liquid crystal display panel in which a plurality of pixels each having a thin film transistor and a pixel electrode electrically connected to a source of the thin film transistor are arranged, and a drain of the thin film transistor is selected from grayscale voltages of a plurality of potentials. A liquid crystal having a drain driver that outputs a voltage, a power supply circuit that outputs a gray scale reference voltage of a plurality of potentials to the drain driver, and a gate driver that outputs a voltage to the gate of the thin film transistor to select the pixel In the display device, the drain driver has a grayscale voltage generation circuit, and the grayscale voltage generation circuit uses a voltage divider circuit in which resistors are connected in series between the potentials of the grayscale reference voltages. To generate the gradation voltages of the plurality of potentials, and the resistance value between the potentials of the gradation reference voltages of the voltage dividing circuit is divided into the gradation reference voltages. The liquid crystal display device, characterized in that set to approximately proportional to the resistance value to a potential difference between the 圧間.
の抵抗値を、各階調基準電圧間の電位差にほぼ比例した
抵抗値に変更するための切替手段を具備することを特徴
とする請求項1に記載された液晶表示装置。2. A switching means for changing the resistance value between the potentials of the gradation reference voltages of the voltage dividing circuit to a resistance value substantially proportional to the potential difference between the gradation reference voltages. The liquid crystal display device according to claim 1.
に複数の直列抵抗回路を設け、前記複数の直列抵抗回路
の中から、各階調基準電圧間の電位差にほぼ比例した抵
抗値となる直列抵抗回路を選択するための選択手段を具
備することを特徴とする請求項1に記載された液晶表示
装置。3. A plurality of series resistance circuits are provided between the potentials of the gradation reference voltages of the voltage dividing circuit, and a resistance value that is substantially proportional to the potential difference between the gradation reference voltages is selected from the plurality of series resistance circuits. 2. The liquid crystal display device according to claim 1, further comprising selection means for selecting the series resistance circuit.
のソースに電気的に接続された画素電極とを有する画素
が複数配置された液晶表示パネルと、上記薄膜トランジ
スタのドレインに、複数の電位の階調電圧から選択し
た、電圧を出力するドレインドライバと、上記ドレイン
ドライバに複数の電位の階調基準電圧を出力する電源回
路と、上記薄膜トランジスタのゲートに、上記画素を選
択する、電圧を出力するゲートドライバとを有する液晶
表示装置であって、 上記ドレインドライバは階調電圧生成回路を有し、上記
階調電圧生成回路は、上記複数の階調基準電圧の電位間
を、抵抗を直列に接続した分圧回路により複数の電位に
分圧し、上記複数の電位の階調電圧を生成し、 上記一つの階調基準電圧Vnと他の階調基準電圧Vn−
1との電位差をVn(n−1)とし、上記階調基準電圧
VnとVn−1の上記分圧回路の印加端子間の合成抵抗
値をRnとすると、全てのRnに対してVn(n−1)
/Rnの値が特定の変動の範囲内で一致するように上記
分圧回路の各抵抗の値を設定したことを特徴とする液晶
表示装置。4. A liquid crystal display panel in which a plurality of pixels each having a thin film transistor and a pixel electrode electrically connected to a source of the thin film transistor are arranged, and a drain of the thin film transistor is selected from gray scale voltages of a plurality of potentials. A liquid crystal having a drain driver that outputs a voltage, a power supply circuit that outputs a gray scale reference voltage of a plurality of potentials to the drain driver, and a gate driver that outputs a voltage to the gate of the thin film transistor to select the pixel In the display device, the drain driver has a grayscale voltage generation circuit, and the grayscale voltage generation circuit uses a voltage divider circuit in which resistors are connected in series between the potentials of the grayscale reference voltages. Of the plurality of potentials to generate the gray scale voltages of the plurality of potentials, and the one gray scale reference voltage Vn and the other gray scale reference voltage Vn-
1 is Vn (n-1), and the combined resistance value between the application terminals of the voltage dividing circuit for the gradation reference voltages Vn and Vn-1 is Rn, Vn (n -1)
A liquid crystal display device, wherein the value of each resistor of the voltage dividing circuit is set so that the value of / Rn is matched within a specific variation range.
1)/Rnの値が±23%の変動の範囲内で一致するよ
うに上記分圧回路の各抵抗の値を設定したことを特徴と
する請求項4に記載された液晶表示装置。5. The Vn (n- for all of the Rn.
5. The liquid crystal display device according to claim 4, wherein the values of the resistors of the voltage dividing circuit are set so that the values of 1) / Rn match within a range of fluctuation of ± 23%.
1)/Rnの値が±15%の変動の範囲内で一致するよ
うに上記分圧回路の各抵抗の値を設定したことを特徴と
する請求項4に記載された液晶表示装置。6. The above Vn (n-
5. The liquid crystal display device according to claim 4, wherein the values of the resistors of the voltage dividing circuit are set so that the values of 1) / Rn match within a range of fluctuation of ± 15%.
1)/Rnの値が完全に一致するように上記分圧回路の
各抵抗の値を設定したことを特徴とする請求項4に記載
された液晶表示装置。7. The Vn (n-
5. The liquid crystal display device according to claim 4, wherein the values of the resistors of the voltage dividing circuit are set so that the values of 1) / Rn completely match.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28954695A JP3784434B2 (en) | 1994-11-11 | 1995-11-08 | Liquid crystal display |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27735194 | 1994-11-11 | ||
| JP6-277351 | 1994-11-11 | ||
| JP28954695A JP3784434B2 (en) | 1994-11-11 | 1995-11-08 | Liquid crystal display |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003390585A Division JP3816480B2 (en) | 1994-11-11 | 2003-11-20 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08211367A true JPH08211367A (en) | 1996-08-20 |
| JP3784434B2 JP3784434B2 (en) | 2006-06-14 |
Family
ID=26552351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28954695A Expired - Lifetime JP3784434B2 (en) | 1994-11-11 | 1995-11-08 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3784434B2 (en) |
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| JP2006284979A (en) * | 2005-04-01 | 2006-10-19 | Hitachi Displays Ltd | Display device |
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| US9389477B2 (en) | 1997-01-20 | 2016-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US8723182B2 (en) | 1997-01-20 | 2014-05-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| JP2002055646A (en) * | 2000-07-27 | 2002-02-20 | Samsung Electronics Co Ltd | Flat panel display device |
| US7477227B2 (en) | 2001-01-16 | 2009-01-13 | Nec Electronics Corporation | Method and driving circuit for driving liquid crystal display, and portable electronic device |
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| JP2005269110A (en) * | 2004-03-17 | 2005-09-29 | Rohm Co Ltd | Gamma correction circuit, display panel, and display device including them |
| JP2005266154A (en) * | 2004-03-17 | 2005-09-29 | Rohm Co Ltd | Gamma correction circuit and display device including the same |
| WO2005088591A1 (en) * | 2004-03-17 | 2005-09-22 | Rohm Co., Ltd | Gamma correction circuit, display panel, and display having them |
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| CN101383118B (en) | 2007-07-06 | 2012-09-05 | 瑞萨电子株式会社 | Display unit and display panel driver |
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