JPH08214219A - Solid-state image sensor drive device - Google Patents

Abstract

(57) [Abstract] [Purpose] Outputs the optical black clamp signal (CPOB signal) together with the CCD optical black signal (OB signal) even if the reference signal has a longer cycle than the horizontal sync signal of the television standard. In addition, a solid-state image sensor driving device capable of measuring an optimum black reference signal is provided. The first counting circuit 32 counts the period from the rising of the reference signal 36 to the start and end points of the stop period of the horizontal drive signal, and the output is decoded by the first decoding circuit 34 and horizontally output. The drive signal 37 is output. The second counting circuit 33 counts the period from the rising of the reference signal 36 to the stop period of the horizontal drive signal 37 and the period corresponding to the OB signal portion beyond the effective pixel signal portion, and outputs this output as the second
By the decoding circuit 35 of FIG. 3 decoding and outputting the CPOB signal 38, the CPOB signal 38 can be output in accordance with the OB signal portion even if the reference signal 36 has a longer cycle than the horizontal synchronizing signal of the television standard.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device driving device.

[0002]

2. Description of the Related Art In recent years, the development of multimedia is remarkable,
Each company is focusing its efforts on market development in fields that had never existed before, with the integration of AV equipment and OA-related equipment at the top. Especially C
The development of an image input device for a computer such as a video camera or a still camera using a solid-state image pickup device such as a CD requires the development of a product with a content that has never been seen before.

A conventional video camera output signal is NTSC.
It is based on television standards such as PAL and PAL. As for the solid-state image sensor, most of them are horizontal synchronization signals (hereinafter referred to as “HD signal”) having a frequency defined by the television standard
Is abbreviated). However, in the case of image input to a computer, the image input device does not need to be restricted by the television standard, and conversely, a new input method that takes into account image processing time and the like is needed. For example, when it is necessary to input a moving image while processing each still image or input a still image while processing each horizontal line, the processing time is taken into consideration, It is necessary to input another reference signal of long.

As an example, a case where the horizontal pixel array of the CCD is composed of two types of effective pixels and optical black (hereinafter abbreviated as "OB") will be given. An effective pixel is a portion that photoelectrically converts an optical video signal into an electric signal by a photodiode, and OB is not a video signal,
This is a part that always outputs a black reference signal. The configuration and operation of a conventional solid-state image sensor driving device will be described with reference to FIGS.

FIG. 8 shows an example of the configuration of a conventional solid-state image pickup device driving device. In FIG. 8, 1 is a conventional solid-state imaging device driving device, 2 is a counting circuit, 3 is a first decoding circuit, 4 is a second decoding circuit, and 5 is a television standard input to the solid-state imaging device driving device 1. H with the frequency defined by
A reference signal having a longer cycle than the D signal, 6 is a horizontal drive signal of the CCD output from the solid-state image sensor driving device 1, and 7 is a CCD pixel signal by clamping the OB portion of the CCD output from the solid-state image sensor driving device 1. Signals for measuring the black reference signal (hereinafter abbreviated as "CPOB signal"), 8, 9 and 10 are count outputs from the rising edge of the reference signal 5 of the counting circuit 2, respectively.

FIG. 9 shows signal voltage waveforms of respective parts of the conventional solid-state image pickup device driving device of FIG. In FIG. 9, 11 is an HD signal having a frequency defined by the television standard. Further, 15 to 17 are counting periods in which the counting outputs 8 to 10 of the counting circuit 2 respectively count. 18-20 is CC
18 is a breakdown of the CCD output pixel signal transferred in the horizontal drive signal 6 of D, 18 is a drive signal portion (effective pixel portion) for transferring the effective pixel portion of the CCD, and 19 is the O of the CCD.
A drive signal portion (OB signal portion) for transferring the B signal portion,
Reference numeral 20 denotes a drive signal portion (idle feed portion) of no signal after all the CCD signals have been transferred. 21
Is a horizontal driving stop period in which the driving is stopped at the CCD horizontal driving signal 6 and no signal is transferred, and 22 is the next HD signal 11 after the driving is started at the CCD horizontal driving signal 6
Is the time required to start up.

In the circuit shown in FIG. 8, when a solid-state image pickup device compliant with the television standard is used and a still image is input while being processed for each horizontal line, that is, a processing time is added to the HD signal 11 to make a cycle. The operation of the solid-state image pickup device driving device when the reference signal 5 having a long period is input will be described. In the solid-state image sensor driving device 1, the counting circuit 2 starts counting from the rising of the reference signal 5. The counting circuit 2 starts counting from the rising edge of the reference signal 5 and stops at the transfer start point of the effective pixel portion 18 of the horizontal drive signal 6 of the CCD. It is necessary to stop when the counting circuit 2 operates during the transfer of the effective pixel portion 18, the waveform of the effective pixel portion 18 is affected by noise or the like due to uneven current consumption generated by the operation of the counting circuit 2. This is to prevent the occurrence of. The counting output 8 of the counting circuit 2 counts for a period 15 from the rising of the reference signal 5. The counting output 9 counts only the period 16. The first decoding circuit 3 decodes the count output 8 and outputs the horizontal drive signal 6 for the CCD.
The starting point of the horizontal drive stop period 21 is decoded and the counting output 9 is decoded to form the end point of the horizontal drive stop period 21. CC
The configuration of the horizontal drive signal 6 of D is the counting output 9 of the counting circuit 2.
Then, the horizontal driving of the CCD is started after a lapse of a period 16 from the rising of the reference signal 5 and the effective pixel signal portion 18 is first transferred. After that, the OB signal portion 19 is transferred.

Here, when an HD signal 11 having a frequency of the television standard is input instead of the reference signal 5, the next rising edge occurs during the transfer of the effective pixel portion 18 which is away from the horizontal drive stop period 21 by the period 22. Then, the counting circuit 2 starts counting again, the counting circuit 2 counts the period 15, and at the same time, the transfer of the OB signal portion 19 is finished, and the driving is stopped to enter the horizontal driving stop period 21. In this case, CPO
The B signal 7 rises after a period 17 during the transfer of the OB signal, and the OB signal portion is accurately clamped to measure the black reference signal of the video signal. There is a case where an OB signal portion is provided before the effective pixel signal portion 18 of the CCD, but since it is close to the CCD signal output portion and is easily affected by noise, etc., it is normally CC.
The OB signal portion 19 after the D effective pixel signal portion 18 is clamped. Therefore, a CP created by decoding the period 17 counted from the rising of the reference signal 5 in the counting circuit 2
The OB signal 7 actually clamps the OB signal in the previous horizontal period.

[0009]

However, according to the above-described conventional configuration, when the processing time of the computer is taken into consideration and the cycle becomes longer than the HD signal 11 as in the reference signal 5 of FIG. The horizontal drive signal 6 of the CCD is HD
The effective pixel signal portion 18 and the OB signal portion 19 are transferred after the period 16 from the rise of the reference signal 5 having a longer cycle than the signal 11, but since the horizontal period is longer than that of the HD signal 11, the OB signal portion 19 After the end of the transfer, the reference signal 5 does not rise yet, and the idling portion 20 which does not send any signal is continued. Therefore, the next rising edge of the reference signal 5 is input to the counting circuit 2 during the idle feed,
Even if the CPOB signal 7 rises after the period 17, the idle feed portion 20 is clamped, so that there is a problem that the optimum black reference signal cannot be measured.

According to the present invention, even if the reference signal has a longer cycle than the horizontal synchronizing signal (HD signal) of the television standard, the optical black clamp signal (CPOB signal) is C
It is an object of the present invention to provide a solid-state image sensor driving device that can output an optical black signal (OB signal) portion of a CD and can measure an optimum black reference signal.

[0011]

According to a first aspect of the present invention, there is provided a solid-state image pickup device driving apparatus, wherein a horizontal drive stop period of a horizontal drive signal of a solid-state image pickup device from a rise of a reference signal which is a reference for determining a timing of outputting a CPOB signal. And a first counting circuit that counts a period until the start point and the end point of the first counting circuit and a count output of the first counting circuit are output, and a horizontal driving signal in which a horizontal driving stop period is set is output. A decoding circuit, a second counting circuit for counting a horizontal driving stop period of the horizontal driving signal and a period beyond the effective pixel signal portion and corresponding to the OB signal portion from the rising edge of the reference signal; The count output is decoded and CPOB
A second decoding circuit for outputting a signal.

According to a second aspect of the present invention, there is provided a solid-state image pickup device driving apparatus according to the first aspect, wherein the second counting circuit has a plurality of counting stages and the number of simultaneous changes and load capacities of the respective counting stages are equal. And means for doing so. According to another aspect of the present invention, there is provided a solid-state image sensor driving device, wherein a horizontal drive start signal generating circuit that outputs a horizontal drive start signal corresponding to a drive start point of a horizontal drive signal of the solid-state image sensor and a predetermined period from the rising of the horizontal drive start signal. After a lapse of time, a reference signal generating circuit that outputs a reference signal serving as a reference for determining the output timing of the CPOB signal, and a first period from the rising of the reference signal to the end point of driving of the horizontal drive signal are counted. At the same time, the counting circuit counts the second period from the rise of the reference signal to the portion corresponding to the OB signal portion beyond the effective pixel signal portion of the horizontal driving signal, and the horizontal driving start signal and the first period of the counting circuit. The first decoding circuit that decodes the count output and outputs the horizontal drive signal in which the horizontal drive stop period is set, and the count output of the second period of the count circuit And de, and a second decoding circuit for outputting a CPOB signal.

According to a fourth aspect of the invention, in the solid-state image pickup device driving device,
Outputs a reference signal that serves as a reference for determining the output timing of the OB signal, and counts the period from the rising of the reference signal to the start point and end point of the horizontal drive stop period of the horizontal drive signal of the solid-state image sensor. And a first decoding circuit which decodes the count output of the first counting circuit and outputs a signal corresponding to the horizontal drive stop period, and a logical operation of the output signal of the first decoding circuit. A logic circuit for outputting a horizontal drive signal for which a horizontal drive stop period has been set, and a period from the rising of the reference signal of the first counting circuit to the portion corresponding to the OB signal portion beyond the effective pixel signal portion of the horizontal drive signal. And a second counting circuit for counting the
A second decoding circuit for outputting a signal.

[0014]

According to another aspect of the present invention, in the solid-state image pickup device driving apparatus, the first counting circuit counts the period from the rising of the reference signal to the start point and the end point of the horizontal drive stop period of the horizontal drive signal of the solid-state image pickup device. Then, the first decoding circuit decodes this count output, and outputs the horizontal drive signal in which the horizontal drive stop period is set. Then, the second counting circuit counts the period from the rising of the reference signal to the horizontal driving stop period of the horizontal driving signal and the period corresponding to the OB signal portion beyond the effective pixel signal portion, and the counted output is second decoded. By the circuit decoding and outputting the CPOB signal,
Even if the reference signal has a longer period than the horizontal synchronizing signal of the television standard or the frequency of the reference signal changes, the CP
The OB signal can be output according to the OB signal part of the CCD.
An optimum black reference signal can be measured.

Further, according to the second aspect of the invention, the second counting circuit, which also counts the period corresponding to the effective pixel signal portion, determines the plurality of counting stages, the number of simultaneous changes in each counting stage, and the load capacitance. The second counting circuit does not cause non-uniform power consumption and does not affect the effective pixel signal due to noise or the like. According to the structure of claim 3, the horizontal drive start signal generation circuit outputs the horizontal drive start signal corresponding to the drive start point of the horizontal drive signal of the solid-state image pickup device. Then, the reference signal generation circuit outputs the reference signal after a lapse of a predetermined period from the rising of the horizontal drive start signal. The counting circuit counts the first period from the rise of the reference signal to the driving end point of the horizontal drive signal, and corresponds to the OB signal portion beyond the effective pixel signal portion of the horizontal drive signal from the rise of the reference signal. Count the second period until. The first decoding circuit decodes the horizontal drive start signal and the count output of the counting circuit in the first period, and outputs the horizontal drive signal set in the horizontal drive stop period. Then, the second decoding circuit decodes the count output of the counting circuit in the second period and outputs the CPOB signal, so that even if the reference signal has a longer cycle than the horizontal synchronizing signal of the television standard, the CPOB signal is generated. Can be output according to the OB signal portion of the CCD, and the optimum black reference signal can be measured. Further, although the reference signal generation circuit outputs the reference signal after a lapse of a predetermined period from the rise of the horizontal drive start signal, the frequency of the reference signal can be freely set by changing the predetermined period.

According to the fourth aspect of the invention, the first counting circuit outputs the reference signal serving as a reference for determining the output timing of the CPOB signal, and the solid-state image sensor is driven horizontally from the rising edge of the reference signal. Count the period until the start and end points of the horizontal drive stop period of the signal,
The first decoding circuit decodes this count output and outputs a signal corresponding to the horizontal drive stop period. A logic circuit performs a logical operation on the output signal of the first decoding circuit and outputs a horizontal drive signal in which a horizontal drive stop period is set. Then, the second counting circuit counts the period from the rising of the reference signal of the first counting circuit to the period corresponding to the OB signal portion beyond the effective pixel signal portion of the horizontal drive signal.
Even if the reference signal output from the first counting circuit has a longer cycle than the horizontal synchronizing signal of the television standard, the second decoding circuit decodes the counting output of the counting circuit of The CPOB signal can be output according to the OB signal portion of the CCD regardless of the frequency of the reference signal, and the optimum black reference signal can be measured.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment of the present invention corresponding to claims 1 and 2 will be described with reference to FIGS. FIG. 1 is a block diagram showing the configuration of a solid-state image pickup device driving apparatus according to the first embodiment of the present invention. In FIG. 1, 31 is a solid-state imaging device driving device of this embodiment, 32 is a first counting circuit, 33 is a second counting circuit, 3
4 is a first decoding circuit, 35 is a second decoding circuit,
36 has a longer cycle than the HD signal of the television standard, and C
A reference signal serving as a reference for determining the output timing of the POB signal, 37 a horizontal drive signal for the CCD, and 38 a CP
OB signal, 39 is the first counting output of the first counting circuit 32, 40 is the second counting output of the first counting circuit 32, 41
Is the counting output of the second counting circuit 33.

FIG. 2 shows signal voltage waveforms at various parts of the solid-state image pickup device driving apparatus shown in FIG. In FIG. 2, 11 is a television standard HD signal. Reference numerals 46 to 48 denote counting circuit outputs of the first counting circuit 32 and the second counting circuit 33, which are counting periods from the rising of the reference signal 36, respectively. Four
6 is the counting period of the first counting output 39 of the first counting circuit 32, 47 is the counting period of the second counting output 40 of the first counting circuit 32, and 48 is the counting output of the second counting circuit 33. This is the counting period. 49 is a horizontal drive stop period in which the drive of the CCD horizontal drive signal 37 is stopped. 50-52 is CC
It is a breakdown of the CCD output pixel signal transferred by the horizontal drive signal 37 of D, 50 is a drive signal portion (effective pixel signal portion) for transferring the signal of the effective pixel portion of the CCD, and 51 is C
A drive signal portion (OB signal portion) for transferring the signal of the OB portion of the CD, and 52 is a drive signal portion for idle feeding (idle portion)
Is.

The first counting circuit 32 of the solid-state image pickup device driving device 31 starts counting from the rising edge of the reference signal 36. The count output 39 counts for a period 46 from the rise of the reference signal 36. The counting output 40 counts for a period 47 only. The first decoding circuit 34 decodes the count output 39 of the period 46 to create the start point of the horizontal drive stop period 49 of the horizontal drive signal 37 of the CCD, and decodes the count output 40 of the period 47 to stop the horizontal drive. Create the end point of period 49. The counting output 41 of the second counting circuit 33 starts counting from the rising edge of the reference signal 36, similarly to the first counting circuit 32, and the period 47 and the effective pixel signal portion 50 of the CCD.
The transfer period is continuously counted, and the period 48 is set in accordance with the OB signal portion 51. The second decoding circuit 35 decodes the count output 41 of the second counting circuit 33 to generate the CPOB signal 38.

According to this embodiment, unlike the conventional method,
Since the second counting circuit 33 counts only the sum of the horizontal drive start period 47 of the CCD, the period of the effective pixel signal portion 50 of the CCD and the period of the OB signal portion 51, the reference signal 36 is the HD signal 11 as shown in FIG. Even with a longer period, the CPOB signal 38 can be raised according to the OB signal portion 51. However, the second counting circuit 33 is operated during the transfer period of the effective pixel signal portion 50, so that the second counting circuit 33 does not cause uneven power consumption that causes noise. A gray code type counting circuit is used for 33. FIG. 3 shows a configuration example of a gray code type counting circuit.

In FIG. 3, 60 is a clock signal input,
Reference numerals 61 to 66 are JK for generating outputs as a counting circuit.
Counting stages of flip-flops, 67 to 82 are AND gates that make the number of simultaneous changes of the counting circuits uniform, 83 to 97 are AND gates that make the output load capacitances of the counting stages 61 to 66 uniform, and 98 is the counting output of the counting circuits. (See Japanese Patent Application No. 2-11943 for the detailed configuration and operation of this counting circuit).

The first counting circuit 32 starts counting from the rising edge of the reference signal 36 and stops so as not to reach the effective pixel signal portion 50 of the CCD, as in the conventional counting circuit 2 of FIG. Gray code type second counting circuit 3
3 continues to operate with uniform power consumption during the effective pixel signal portion 50. This gray code type counting circuit is the second
By using the counter circuit 33 of FIG. 3 to create a pixel transfer period including the OB of the CCD from the rise of the reference signal 36, the reference signal 36 is larger than the cycle of the HD signal 11 and the frequency (or cycle) changes. Even if it does, C that can clamp the OB signal portion 51 at the optimum position
It is possible to create the POB signal 38. Although the reference signal 36 is input from the outside in this embodiment, there is no problem even if the reference signal 36 is created inside the solid-state imaging device 31.

Further, the second counting circuit 33 may be used instead of the gray code type counting circuit as long as it does not affect the effective pixel signal portion 50 of the CCD by noise or the like, and the same effect can be obtained. Can be obtained. Next, a second embodiment of the present invention corresponding to claim 3 will be described with reference to FIGS. 4 and 5. FIG. 4 shows the configuration of a solid-state image sensor driving device according to the second embodiment of the present invention. It is a block diagram shown. The embodiment of FIG. 4 is different from the embodiment of FIG. 1 in that the gray code type counting circuit is not used, and a sync signal generating circuit (hereinafter abbreviated as “SSG”) for generating a reference signal and a CCD are driven. A solid-state image sensor drive circuit (hereinafter abbreviated as “CG”),
Since the SSG counts the effective pixel portion of the CCD and the CG stops counting in the effective pixel portion of the CCD as in the conventional case, no noise or the like is generated and it is not necessary to use a gray code type counting circuit. .

In FIG. 4, 100 is the SSG of the solid-state image pickup device driving device of this embodiment, 101 is the CG of the solid-state image pickup device driving device of this embodiment, and 102 is the first of the SSG 100.
Counting circuit (horizontal drive start signal generating circuit), 103 is S
The second counting circuit (reference signal generating circuit) of SG100, 1
Reference numeral 04 is a counting circuit of the CG 101, 105 is a first decoding circuit of the CG 101, 106 is a second decoding circuit of the CG 101, 107 is a first counting circuit 102 of the SSG 100.
Counting output (horizontal drive start signal), 108 is a reference signal having a longer cycle than the HD signal of the television standard, and 109 is C
Horizontal drive signal of CD, 110 is a CPOB signal, 111 is a first counting output of the counting circuit 104 of the CG 101, 112
Is a second counting output of the counting circuit 104 of the CG 101.

FIG. 5 shows the signal voltage waveform of each part of the solid-state image pickup device driving device of FIG. In FIG. 5, 11 is an HD signal of the television standard. 125 is a counting period (predetermined period) counted by the second counting circuit 103 of the SSG 100, and 126 and 127 are counting periods (first period, second period) from the rising of the reference signal 108 of the counting circuit 104 of the CG 101. ), 128 is the CCD horizontal drive signal 10
9 is a horizontal drive stop period. CCDs 129 and 130
Is a breakdown of the CCD output pixel signal transferred by the horizontal drive signal 109, and 129 is a drive signal portion (effective pixel signal portion) for transferring the signal of the effective pixel portion of the CCD, and 130.
Is a drive signal portion (O
B signal portion).

The solid-state image pickup device driving apparatus of this embodiment includes an SSG 100 having a first counting circuit 102 and a second counting circuit 103, a counting circuit 104, a first decoding circuit 105 and a second decoding circuit 106. Have CG
And 101. First counting circuit 10 of SSG 100
Reference numeral 2 divides the original oscillation clock of the circuit to create the driving start point of the horizontal driving signal of the CCD. In this case, the original oscillation clock frequency and the number of frequency division stages can be set freely. SSG
The second counting circuit 103 of 100 is the first counting circuit of the SSG 100.
The counting is started from the rising edge of the count output 107 of the counting circuit 102, and the CPOB signal 110 rises at an appropriate position of the OB signal portion 130 of the horizontal drive signal 109 of the CCD to clamp the OB level. The period 125 is counted to generate the horizontal reference signal 108.
The counting circuit 104 of the CG 101 starts counting from the rising edge of the reference signal 108, and causes the decoding circuit 105 to wait for the period 12
6 count output 111 is output, and CCD horizontal drive signal 1
It is used at the start point of the horizontal drive stop period 128 of 09. Next, as the end point of the horizontal drive stop period 128, that is, the drive start point of the horizontal drive signal 109, the first from the SSG 100
The counting output 107 of the counting circuit 102 of the
Input to the decoding circuit 105. Then, the horizontal driving signal 109 of the CCD is output from the first decoding circuit 105.

The CPOB signal 110 is the second signal of the CG 101.
In the decoding circuit 106 of the period 12 from the counting circuit 104
7 count output 112 is decoded and created.
Period 100 from the rising of the count output 107 of the first counting circuit 102 of 100 to the rising of the reference signal 108
5 is equal to the period 22 of FIG. 9 of the conventional example, the period 127
Is set to be the same as the counting period 17 of the CPOB signal 7 of the conventional example shown in FIG. 9, it is possible to create the CPOB signal 110 capable of clamping the OB signal portion 130 at the optimum position. Regarding the frequency of the reference signal 108, the SSG100
It can be set freely by changing the counting period of the first counting circuit 102.

Next, a third aspect of the present invention corresponding to claim 4
An example of the above will be described with reference to FIGS. 6 and 7. FIG. 6 is a block diagram showing the configuration of a solid-state image pickup device driving apparatus according to the third embodiment of the present invention. Similar to the embodiment of FIG. 4, the embodiment of FIG. 6 does not use the gray code type counting circuit, but is different from the embodiment of FIG. 4 in SSG and C.
The circuit configuration of G and the output signal are different.

In FIG. 6, reference numeral 140 is an SSG of the solid-state image pickup device driving device of this embodiment, 141 is a CG of the solid-state image pickup device driving device of this embodiment, 142 is a counting circuit (first counting circuit) of the SSG 140, and 143. Is a decoding circuit (first decoding circuit) of SSG140, 144 is CG141
Counting circuit (second counting circuit), 145 is a decoding circuit (second decoding circuit) of CG 141, and 146 is CG 1.
41 is a logic circuit, and 147 is a counting circuit 14 of the SSG 140.
The reference output signal is a count output of 2 and has a longer cycle than the HD signal of the television standard and serves as a reference for determining the output timing of the CPOB signal. The signals 151 and 1 which are the decode signals of the output of the decode circuit 143 and which generate the horizontal drive stop period of the horizontal drive signal 148.
Reference numeral 52 is a count output of the counting circuit 142 of the SSG 140. The count output 151 creates the rising edge of the signal 150 that is the basis for creating the horizontal drive stop period, and the count output 152 creates the falling edge of the signal 150. That is, it is a signal for generating the drive stop and start point of the horizontal drive signal 148, respectively. Reference numeral 153 is a count output of the counting circuit 144 of the CG 141.

FIG. 7 is a signal voltage waveform diagram of each part of the solid-state image pickup device driving apparatus of FIG. In FIG. 7, 11 is a television standard HD signal. Reference numeral 165 denotes a period 166 from the fall of the decode signal 150, which is the basis for creating the horizontal drive stop period, to the rise of the reference signal 147.
And 167 are the counting periods of the counting outputs 151 and 152 of the counting circuit 142 of the SSG 140, respectively.
The difference between 6 and 167 is the horizontal drive stop period of the CCD horizontal drive signal 148, that is, the rising period of the decode signal 150 that is the basis for creating the horizontal drive stop period.
168 is a count output 153 of the counting circuit 144 of the CG 141
CPO from the rising of the reference signal 147 in the counting period of
It counts up to the rising edge of the B signal 149. 169
Reference numerals 170 and 170 represent the details of the CCD output signal transferred by the CCD horizontal drive signal 148. Reference numeral 169 represents a drive signal portion (effective pixel signal portion) for transferring the signal of the effective pixel portion of the CCD, and 170 represents the OB portion of the CCD. Is a drive signal portion (OB signal portion) for transferring the signal of.

The solid-state image pickup device driving apparatus of this embodiment has an SSG having a counting circuit 142 and a decoding circuit 143.
140 and a CG 141 having a counting circuit 144, a decoding circuit 145 and a logic circuit 146. SSG
The counting circuit 142 of 140 is composed of a counter composed of an arbitrary counting stage, and produces a reference signal 147. Also, counting outputs 151 and 1 for generating the decoded signal 150
52 is output. The count output of the counting circuit 142 of the SSG 140 is input to the CG 141 as a reference signal 147, and the CPOB signal 14 is input by the counting circuit 144 and the decoding circuit 145.
9 is created. The counting circuit 142 of the SSG 140 outputs the counting outputs 151 and 152, and the decoding circuit 143 produces the signal 150 which is the basis for producing the horizontal drive stop period. The decode signal 150 is input to the CG 141 and is input to the logic circuit 146 such as an OR gate or an AND gate.
The CCD horizontal drive signal 14
Create 8. The period 165 is the period 22 of FIG.
If set to the same, the CPOB signal 1 that clamps the OB signal portion 170 at the optimum position regardless of the frequency of the reference signal 147 generated by the counting circuit 142 of the SSG 140.
It is possible to create 49.

In this embodiment, the logic circuit 146 is used to create the horizontal drive stop period of the horizontal drive signal 148. However, the decode signal 150 causes the circuit to be reset to stop the drive. If the circuit in which the horizontal drive stop period of the horizontal drive signal is created by using, the same effect can be obtained. As described above, according to the first to third embodiments, the CPOB signal is created in accordance with the OB signal portion of the CCD regardless of the length of the cycle of the reference signal, and the optimum black reference signal is measured. be able to. Therefore, the practical effect is extremely large.

In the first to third embodiments, CC
Although the case where the horizontal pixel configuration of D is composed of two effective pixel portions and the OB portion is described, even if a CCD having another pixel configuration is used, for example, in the first embodiment, If the counting period 48 (FIG. 2) of the counting output 41 of the second counting circuit 33 of FIG. 1 is changed and the CPOB signal 38 is set so as to match the OB signal portion 51 (FIG. 2), the CCD of another pixel configuration is obtained. Can be easily realized.
Similarly, the second and third embodiments can be easily realized by changing the counting period of the reference signal, the horizontal driving signal, and the counting circuit that creates the CPOB signal, and setting the CPOB signal to match the OB signal portion. It is possible.

[0034]

According to the solid-state image pickup device driving device of the present invention, the second counting circuit corresponds to the OB signal portion beyond the horizontal drive stop period of the horizontal drive signal and the effective pixel signal portion from the rise of the reference signal. The second decoding circuit decodes this count output and outputs the CPOB signal, so that even if the reference signal has a longer cycle than the horizontal synchronizing signal of the television standard, Even if the frequency changes, the CPOB signal can be output in accordance with the OB signal portion of the CCD, and the optimum black reference signal can be measured.

Further, in the solid-state image pickup device driving device according to the second aspect, the second period for counting the period corresponding to the effective pixel signal portion is also used.
Since the counting circuit of is composed of a plurality of counting stages and means for equalizing the number of simultaneous changes and the load capacitance of each counting stage, the second counting circuit does not cause uneven power consumption, and the effective pixel signal There is no influence of noise or the like. In the solid-state image sensor driving device according to claim 3, the reference signal generating circuit is
The reference signal is output after a lapse of a predetermined period from the rise of the horizontal drive start signal output from the horizontal drive start signal generation circuit, and the counting circuit passes the effective pixel signal portion of the horizontal drive signal from the rise of the reference signal to the OB signal portion. The reference signal has a longer cycle than the horizontal synchronizing signal of the television standard by counting the second period until the corresponding time, the second decoding circuit decoding the count output of the second period and outputting the CPOB signal. However, the CPOB signal can be output in accordance with the OB signal portion of the CCD, and the optimum black reference signal can be measured. Further, the reference signal generation circuit outputs the reference signal after a lapse of a predetermined period from the rising of the horizontal drive start signal, but the frequency of the reference signal can be freely set by changing the predetermined period.

According to a fourth aspect of the present invention, there is provided a solid-state image pickup device driving device comprising:
Counting circuit counts the period from the rise of the reference signal output from the first counting circuit to the period corresponding to the OB signal portion beyond the effective pixel signal portion of the horizontal drive signal.
Even if the reference signal output from the first counting circuit has a longer cycle than the horizontal synchronizing signal of the television standard, the second decoding circuit decodes the counting output of the counting circuit of The CPOB signal can be output according to the OB signal portion of the CCD regardless of the frequency of the reference signal, and the optimum black reference signal can be measured.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a solid-state image pickup device driving apparatus according to a first embodiment of the present invention.

FIG. 2 is a signal voltage waveform diagram of each part of the solid-state image pickup device driving apparatus according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of a second counting circuit in the first embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of a solid-state image pickup device driving apparatus according to a second embodiment of the present invention.

FIG. 5 is a signal voltage waveform diagram of each part of the solid-state image pickup device driving apparatus according to the second embodiment of the present invention.

FIG. 6 is a block diagram showing the configuration of a solid-state image sensor driving device according to a third embodiment of the present invention.

FIG. 7 is a signal voltage waveform diagram of each part of the solid-state image pickup device driving apparatus according to the third embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional solid-state image sensor driving device.

FIG. 9 is a signal voltage waveform diagram of each part of the conventional solid-state imaging device driving device.

[Explanation of symbols]

11 Television Standard HD Signal 31 Solid-State Imaging Device Driving Device 32 First Counting Circuit 33 Second Counting Circuit 34 First Decoding Circuit 35 Second Decoding Circuit 36 Reference Signal 37 CCD Horizontal Driving Signal 38 CPOB Signal 39 Counting output of first counting circuit 40 Counting output of first counting circuit 41 Counting output of second counting circuit 46 Counting period of counting output of first counting circuit 47 Counting period of counting output of first counting circuit 48 Counting period of count output of the second counting circuit 49 Horizontal drive stop period 50 Drive signal part for transferring signal of effective pixel part of CCD 51 Drive signal part for transferring signal of OB part of CCD 52 Drive signal for blank feed Partial 60 Clock signal input 61-66 JK flip-flop counting stage 67-82 AND for equalizing the number of simultaneous changes of the counting circuit
Gates 83 to 97 AND gates for equalizing the output load capacitances of the counting stages 61 to 66 98 Counting output of counting circuit 100 Synchronous signal generating circuit (SSG) 101 Solid-state image sensor driving circuit (CG) 102 First counting circuit of SSG100 103 Second Counting Circuit of SSG100 104 Counting Circuit of CG101 105 First Decoding Circuit of CG101 106 Second Decoding Circuit of CG101 107 Counting Output of First Counting Circuit 102 of SSG100 108 Reference Signal 109 Horizontal Driving Signal of CCD 110 CPOB signal 111 Counting output of counting circuit 104 of CG 101 112 Counting output of counting circuit 104 of CG 101 125 Counting period of counting by second counting circuit 103 of SSG 100 126 Counting period from rising edge of HD signal of counting circuit 104 127 Counting Times Counting period from rising edge of HD signal of 104 128 Horizontal drive stop period 129 Drive signal portion for transferring signal of CCD effective pixel portion 130 Drive signal portion for transferring signal of CCD OB portion 140 SSG 141 CG 142 SSG 140 counting Circuit 143 Decoding circuit of SSG140 144 Counting circuit of CG141 145 Decoding circuit of CG141 146 Logic circuit of CG141 147 Reference signal 148 CCD horizontal drive signal 149 CPOB signal 150 Decode signal 151 SSG140 horizontal drive stop period counting Count output of the circuit 142 152 Count output of the count circuit 142 of the SSG 140 153 Count output of the count circuit 144 of the CG 141 165 Standup of the decode signal 150 that is the basis for creating the horizontal drive stop period Count output of the counter circuit 144 counts the output 168 CG141 counting circuit 142 counts the output 167 SSG140 the counter circuit 142 of period 166 SSG140 from rising to rising edge of the reference signal 147 1
Counting period of 53 169 Drive signal portion for transferring signals of CCD effective pixel portion 170 Drive signal portion for transferring signals of CCD OB portion

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsumi Takeda 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Koji Matsumaru, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co. 72) Inventor Masayasu Miyashita 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] 1. A period from a rise of a reference signal, which is a reference for determining the output timing of an optical black clamp signal, to a start point and an end point of a horizontal drive stop period of a horizontal drive signal of a solid-state image sensor. A first counting circuit for counting; and a first counting circuit for decoding the count output of the first counting circuit and outputting a horizontal drive signal in which the horizontal drive stop period is set.
And a second counting circuit that counts a period from the rising of the reference signal to a period corresponding to an optical black signal portion beyond the horizontal drive stop period and the effective pixel signal portion of the horizontal drive signal, A solid-state imaging device driving device, comprising: a second decoding circuit that decodes a count output of a second counting circuit and outputs the optical black clamp signal. 2. The solid-state image pickup device driving device according to claim 1, wherein the second counting circuit comprises a plurality of counting stages and means for equalizing the number of simultaneous changes and load capacitance of each of the counting stages. apparatus. 3. A horizontal drive start signal generation circuit for outputting a horizontal drive start signal corresponding to a drive start point of a horizontal drive signal of a solid-state image pickup device, and an optical black after a lapse of a predetermined period from the rise of the horizontal drive start signal. A reference signal generating circuit that outputs a reference signal serving as a reference for determining the output timing of the clamp signal, and counts a first period from the rising of the reference signal to the end point of driving of the horizontal drive signal. At the same time, a counting circuit for counting a second period from the rise of the reference signal to the optical black signal portion beyond the effective pixel signal portion of the horizontal drive signal, and the horizontal drive start signal and the counting circuit A first decoding the count output in the first period and outputting a horizontal drive signal set in the horizontal drive stop period; And a second decoding circuit for decoding the count output of the counting circuit in the second period and outputting the optical black clamp signal. 4. A reference signal, which serves as a reference for determining the output timing of an optical black clamp signal, is output, and a horizontal drive stop period start point of a horizontal drive signal of a solid-state image sensor from the rising of the reference signal and A first counting circuit that counts a period until reaching an end point; a first decoding circuit that decodes a count output of the first counting circuit and outputs a signal corresponding to the horizontal drive stop period; A logic circuit that logically operates an output signal of the first decoding circuit to output a horizontal drive signal in which the horizontal drive stop period is set; and a horizontal drive signal from the rising of the reference signal of the first counting circuit. A second counting circuit for counting a period of time beyond the effective pixel signal portion and corresponding to the optical black signal portion; and counting by the second counting circuit Decodes the force, the solid-state image pickup device driving apparatus and a second decoding circuit for outputting the clamp signal of the optical black.