JPH08265603A - Video control signal output device between digital encoder and frame buffer - Google Patents

Abstract

(57) Abstract: By outputting a control signal output from a digital encoder in synchronism with a horizontal drive signal, an accurate operation can be performed without causing an error caused by a phase difference or a temperature change and a deviation between parts. To provide an image control signal output device between a digital encoder and a frame buffer, which can output a control signal to control input / output of image data stored in a frame memory. In a digital video processing system including a digital encoder that outputs a field signal, a vertical drive signal, and a horizontal drive signal for using video data stored in a frame memory, a field signal output from the digital encoder is Field signal processing means for outputting in synchronization with the input horizontal drive signal, and vertical blank signal output means for processing the vertical drive signal output from the digital encoder in synchronization with the horizontal drive signal and outputting a corresponding vertical blank signal. Consists of.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video control signal output device between a digital encoder and a frame, and more specifically, in a digital video signal processor, the video data stored in a frame buffer is output to a digital encoder. The present invention relates to a video control signal output device between a frame encoder and a digital encoder that outputs a video control signal for implementing a signal conforming to a signal standard of a video output device, a TV or a monitor.

[0002]

2. Description of the Related Art Generally, in a digital video signal processor, a digital encoder is used to reproduce digital video data on a TV or a monitor. This digital encoder outputs the input digital video signal to T
It is converted into a digital luminance signal and a color signal that conform to the V or monitor signal standard and output to a digital / analog converter and a signal circuit.

The signal output from the digital encoder is input to a digital / analog converter and a signal combination circuit, processed into a signal conforming to the signal standard of the TV or monitor, and output to reproduce the original image. .

FIG. 1 is a block diagram showing the configuration of a general video signal processing system.

In FIG. 1, the digital video data stored in the frame memory (10) is converted into a digital encoder (3
In order to be input to (0), it should be synchronized with the applied video synchronization signal, but the signal output from the commonly used digital encoder (30) is
It is in the form of a field signal and a vertical blank signal, which are signals out of synchronization for controlling (10).

Therefore, in order to input the image data stored in the frame memory (10) to the digital encoder (30), a signal output from the digital encoder (30) using a separate control signal converter. Must be converted and generated to match the signal required by the frame memory (10).

Conventionally, since this signal is generated, as shown in FIG.
As shown in FIG. 2, a signal conversion unit (20) including a multivibrator is used.

That is, the signal converter (20) comprises a first monostable multivibrator (21) which oscillates according to a control signal output from the digital encoder (30) and a second monostable multivibrator (22). Become.

The digital encoder (30) is a frame memory
When the signal (F2) for reading the video data stored in (10) for one field is output, the first monostable multivibrator (21) is charged by the output signal and the externally mounted resistor and capacitor.・ Adjust the discharge time,
As shown in FIG. 3, the 3HSYNC period of the horizontal drive signal is delayed and output.

The signal output here is output through the second monostable multivibrator (22) again adjusted by the time constant of the resistor and the capacitor.

[0011]

However, a conventional control signal output device for exchanging video data between a digital encoder and a frame buffer is to change the oscillation frequency by adjusting the time constant of the resistor and the capacitor, thereby changing the resistance of the resistor. Also, due to the characteristics of capacitor parts, the charging / discharging time changes depending on the temperature change.

Therefore, the frequency of the control signal output changes due to the temperature change of the resistor and the capacitor, which causes a problem that accurate control cannot be performed.

Further, the resistance and the capacitor have a drawback that it is necessary to adjust the resistance or the capacitor for each set produced by the deviation between the parts.

Therefore, in order to solve the above-mentioned conventional problems, an object of the present invention is to output a control signal output from a digital encoder in synchronism with a horizontal drive signal so as to output a phase difference or a temperature change. Video control signal output between digital encoder and frame buffer that can output input / output of video data stored in the frame memory and control input / output of video data without any adjustment work due to error caused by component and deviation between parts To provide a device.

[0015]

As a means for achieving the above object, the structure of the present invention has a field signal for using video data stored in a frame memory,
In a digital image processing system including a digital encoder that outputs a vertical drive signal and a horizontal drive signal, a field signal processing unit that processes and outputs a field signal output from the digital encoder in synchronization with an applied horizontal drive signal, And a vertical blank signal output means for processing a vertical drive signal output from the digital encoder in synchronization with the horizontal drive signal and outputting a vertical blank signal corresponding thereto.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention having the above-described structure will be described in detail below with reference to the accompanying drawings.

FIG. 4 is a waveform diagram of a control signal output from the digital encoder according to the embodiment of the present invention, and FIG. 5 shows a video control signal output device between the digital encoder and the frame buffer according to the embodiment of the present invention. FIG. 6 is a configuration diagram, and FIG. 6 is a waveform diagram of a control signal output from the video control signal output device according to the embodiment of the present invention.

As shown in FIG. 5, the structure of the video control signal output device between the digital encoder and the frame buffer according to the embodiment of the present invention is the same as the field signal (F2) output from the digital encoder (30). Field signal processing unit (2
4) and a vertical blank signal output unit (25) that processes the vertical drive signal output from the digital encoder (30) so as to match the synchronization signal and outputs a vertical blank signal.

The field signal processing unit (24) inverts the horizontal drive signal (AV) output from the digital encoder (30) and outputs the inverted signal, and the first inverter (211).
The horizontal drive signal that is inverted and output at the clock terminal (CLK) is counted and the digital encoder (3
The first counter (213) outputs the field signal (F2) output from the (0) after delaying it for a certain time.

The vertical blank signal output unit (25) inputs the second inverter (212) for inverting and outputting the vertical drive signal (VD) output from the digital encoder (30) and the input terminal (DATA). Clock pin (CLK) depending on the set value of the counter
Count the horizontal drive signal (AV) input to
A second counter (214) for changing the signal inverted by the second inverter (212) and input to the load terminal (LOAD) by a horizontal drive signal, and a clear terminal (CLR) for the second counter.
Clock terminal (CLK) connected to the output stage (OUT) of (214)
D flip-flop (21) which is driven by the vertical drive signal (VD) input to and outputs a vertical blank signal (MVBLK)
5) consists of and.

The operation of the video control signal output device between the digital encoder and the frame buffer according to the embodiment of the present invention having the above structure is as follows.

In the digital image processing system, a digital encoder (30) for separating and outputting a digital luminance signal and a chrominance signal which meet a signal standard of a TV or a monitor is output to a frame memory (10), that is, one frame. A signal for outputting video data is output to a memory (10) that stores a luminance signal and a color difference signal that are corresponding video data per frame.

A field signal (F2) for distinguishing whether the field to be scanned output from the digital encoder (30) is an odd field or an even field, and 1
Horizontal drive signal (AV) for outputting and processing valid video data during the horizontal synchronization period in the field, and vertical driving signal for outputting and processing valid video data during the vertical synchronization period. The signal (VD) is another synchronization signal, that is, in order to synchronize with a signal for reproducing an accurate image by matching the scanning of the transmitting side and the receiving side of the video signal, After being input to the video control signal output device according to the embodiment and converted, it is output to the frame memory (10).

The field signal (F2) output from the digital encoder (30) is input to the first counter (213) of the video control signal output device, and the digital encoder (30)
The horizontal drive signal (AV) output from the above is inverted and output through the first inverter (211), and then input to the clock terminal (CLK) of the first counter (213).

The horizontal synchronizing signal according to the embodiment of the present invention is 1 when the signal processing method is the NTSC method.
It is 5.73MHz, and it is 15.625KHz in the case of PAL system.

As shown in FIG. 6, the first counter (213) is set by counting the inverted horizontal synchronizing signal input to the clock terminal (CLK) according to the set counter value. The field signal (F2) input at the time of counting is output.

The counter value according to the embodiment of the present invention is 3, and as shown in FIG. 6, the field signal (F2) delayed three times by the horizontal drive signal (AV).
Is output through the output terminal (QC) of the second counter (213).

According to the embodiment of the present invention, the first counter (2
13) also has output terminals (QA to QF), and the counter value set by each of these output terminals (QA to QF) is configured differently.
A signal delayed once by the horizontal drive signal at the QA output terminal, a signal delayed twice at the QB output terminal, a signal delayed three times at the QC output terminal, and a signal delayed four times at the QD output terminal. However, the QE output terminal outputs a signal delayed five times.

The horizontal drive signal (AV) output from the digital encoder (30) is input to the clock terminal (CLK) of the second counter (214), and the vertical drive signal (VD) is input to the second inverter.
After being inverted output through (212), the second counter (214)
Input to the load terminal (LOAD) of.

The input terminal (DATA) of the second counter (214) is set so that the initial value "11" of the counter is input.

When the logical value of the vertical drive signal (VD) inverted and output by the second inverter (212) is low level, the input terminal
A signal corresponding to the initial value "11" is input to (DATA).

As shown in FIG. 6, when the vertical drive signal (VD) is input in the high level state, the second counter
(214) is operated.

The second counter (214) has a horizontal drive signal (A) input to the clock terminal (CLK) according to the set initial value.
V) is counted, and when the count reaches the set value, the state of the output signal is changed and output.

In other words, the high level vertical drive signal
When (VD) is input, the counter is changed to 11, 10, ..., 2, 1, 1,
After subtraction counting like 0, the counter value becomes 0.
The corresponding low level signal is output at the moment.

The output signal of the second counter (214) is input to the clear terminal (CLR) of the D flip-flop (215).

A high-level signal is always input to the input terminal (D) of the D flip-flop (215) according to the embodiment of the present invention, and a high-level signal is also input to the preset terminal (PR).

While the high level signal is being input to the clear terminal (CLR), the input high level signal is inverted through the inverting output terminal (/ Q) and output in the low level state. .

As shown in FIG. 6, the output value of the second counter (214) is output in the low state and the clear terminal (C
When input to LR), the D flip-flop (215) is cleared and a high level signal is output.

Therefore, the vertical drive signal (VD) output from the digital encoder (30) outputs data through the second counter (214) and the D flip-flop (215) during the period when valid data exists. It is converted to a vertical blank signal (MVBLK) for output and output to the frame memory (10).

The signal width of the vertical blank signal (MVBLK) is changed by the initial value input to the input terminal (DATA) of the second counter (214). That is, the input vertical drive signal (A
The portion corresponding to the sum of the horizontal drive signal (AV) counted according to the pulse width of V) and the set value of the second counter (214) is a period in which the vertical blank signal (MVBLK) is driven.

In the video control signal output device, when the field signal is output to the frame memory, the field video data corresponding to the input field signal is output to the digital encoder during the period in which the vertical blank signal is driven. It

The digital encoder processes the video data output from the frame memory, separates it into a color signal and a luminance signal for composing other composite sync signals to form a composite video signal, and a composite video signal processing unit ( (Not shown).

[0043]

As described above, in the digital video signal processing system according to the embodiment of the present invention, basically, in synchronization with the field signal, horizontal drive signal and vertical drive signal output from the digital encoder, By outputting a stable video control signal to the frame memory without changing the pulse width due to phase distortion or temperature change,
Accurate video can be reproduced by synchronizing signals.

Further, since the work for adjusting the deviation of the parts is not necessary, it is convenient to synchronize the control signals between the digital encoder and the frame memory, and the video control between the digital encoder and the frame memory is achieved. A signal output device can be provided.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing a general video signal processing system diagram.

FIG. 2 is a block diagram of a conventional video control signal output device between a digital encoder and a frame buffer.

FIG. 3 is an output waveform diagram of a video control signal between a conventional digital encoder and a frame buffer.

FIG. 4 is a waveform diagram of a control signal output from the digital encoder according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of a video control signal output device between a digital encoder and a frame buffer according to an embodiment of the present invention.

FIG. 6 is a waveform diagram of a control signal output from the video control signal output device according to the embodiment of the present invention.

[Explanation of symbols]

 10: frame memory 20: control signal conversion unit 24: field signal processing unit 25: vertical blank signal output unit 30: digital encoder 211: first inverter 212: second inverter 213: first counter 214: second counter 215 : D flip-flop AV: Horizontal drive signal VD: Vertical drive signal F2: Field signal MF2: Required field signal MVBLK: Vertical blank signal

Claims (6)

[Claims] 1. A field signal output from a digital encoder in a digital video processing system including a digital encoder that outputs a field signal, a vertical drive signal, and a horizontal drive signal for using video data stored in a frame memory. Field signal processing means for processing and outputting in synchronization with the applied horizontal drive signal, and vertical for outputting a vertical blank signal corresponding to the vertical drive signal output from the digital encoder in synchronization with the horizontal drive signal. An image control signal output device between a digital encoder and a frame buffer, comprising a blank signal output means. 2. The field signal processing means includes a first inverting means for inverting and outputting a horizontal drive signal output from the digital encoder, and a digital encoder using the signal output from the first inverting means as a clock signal. 2. A video control signal output device between a digital encoder and a frame buffer according to claim 1, further comprising: first counter means for delaying and outputting the field signal output from the device by a set counter value. 3. The first counter means comprises a large number of output terminals, different counter values are set for the respective output terminals, and the delay time of the output signal is different. Video control signal output device between digital encoder and buffer. 4. The vertical blank signal processing means includes second inverting means for inverting and outputting a vertical drive signal output from a digital encoder, and a vertical drive signal activated and output from the second inverting means. And a second counter means for counting the horizontal drive signal applied according to the set counter value and outputting a corresponding signal when the counting operation according to the set counter value is completed, and a vertical output from the digital encoder. 2. The digital encoder according to claim 1, further comprising a D flip-flop that is cleared by the state of the signal output from the second counter means and outputs a corresponding vertical blank signal using the drive signal as a clock signal. Video control signal output device between frame memories. 5. The second counter means, when the signal output from the second inverting means is activated and input, counts the clock signal input by the set counter value and then sets the clock signal. 5. The video control signal output device between the digital encoder and the frame memory according to claim 4, wherein a low level signal is output at a time corresponding to the counter value. 6. The digital encoder and frame according to claim 4, wherein the drive period of the vertical blank signal is set by the pulse width of the vertical drive signal output from the digital encoder and the set value of the second counter. Video control signal output device between memories.