JPH0821716B2 - Method for manufacturing notched insulated gate static induction transistor - Google Patents
Method for manufacturing notched insulated gate static induction transistorInfo
- Publication number
- JPH0821716B2 JPH0821716B2 JP3243140A JP24314091A JPH0821716B2 JP H0821716 B2 JPH0821716 B2 JP H0821716B2 JP 3243140 A JP3243140 A JP 3243140A JP 24314091 A JP24314091 A JP 24314091A JP H0821716 B2 JPH0821716 B2 JP H0821716B2
- Authority
- JP
- Japan
- Prior art keywords
- shaped groove
- insulated gate
- static induction
- induction transistor
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000006698 induction Effects 0.000 title claims description 14
- 230000003068 static effect Effects 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 title description 8
- 239000000758 substrate Substances 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 4
- 238000005036 potential barrier Methods 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子の製造方法に
関するもので、特に高速・低消費電力で動作する切り込
み型絶縁ゲート静電誘導トランジスタの製造方法の改良
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to an improvement of a method of manufacturing a notch type insulated gate static induction transistor which operates at high speed and low power consumption.
【０００２】[0002]
【従来の技術】本発明者の一人から、高速スイッチング
や、高速・低消費電力集積回路用の素子として優れた性
能を発揮する切り込み型絶縁ゲート静電誘導トランジス
タ（例えば、特願昭５２−１３７０７号）が提案されて
いる。2. Description of the Related Art One of the present inventors has proposed a slit type insulated gate static induction transistor (for example, Japanese Patent Application No. 52-13707) which exhibits excellent performance as an element for high speed switching and high speed / low power consumption integrated circuits. No.) is proposed.
【０００３】切り込み型絶縁ゲート静電誘導トランジス
タはドレイン電界の効果がソースにまで及ぶように設計
され、半導体・絶縁膜界面のみならず基板中をも電流が
流れるために不飽和型電流電圧特性を有し、駆動能力が
大きいなどの特徴を持つだけでなく、チャネルが半導体
基板の深さ方向に形成されるためにチャネル長やゲート
長の制御性が良く、短チャネル化に適している。The cut-type insulated gate static induction transistor is designed so that the effect of the drain electric field extends to the source, and since the current flows not only in the semiconductor-insulating film interface but also in the substrate, the unsaturated current-voltage characteristic is obtained. In addition to having characteristics such as a large driving capability, the channel is formed in the depth direction of the semiconductor substrate, so that the controllability of the channel length and the gate length is good, and it is suitable for shortening the channel.
【０００４】この切り込み型絶縁ゲート静電誘導トラン
ジスタの公知の構造を図２を参照して説明する。図２が
平面パターンである。シリコン基板に設けられたＵ字型
の溝の側壁１０にまたがるようにして、多結晶シリコン
のゲート電極１２が設けられている。領域１４がＵ字型
の溝の底部に接するｎ型で高不純物密度のソース領域、
領域１５がＵ字型の溝の上部に接するｎ型で高不純物密
度のドレイン領域をそれぞれ表している。領域１２´，
１４´及び１５´はそれぞれの領域のコンタクト開口部
を表している。A known structure of this notch type insulated gate static induction transistor will be described with reference to FIG. FIG. 2 is a plane pattern. A gate electrode 12 of polycrystalline silicon is provided so as to extend over the side wall 10 of the U-shaped groove provided in the silicon substrate. An n-type high impurity density source region in which the region 14 contacts the bottom of the U-shaped groove,
Regions 15 are n-type and high-impurity-density drain regions respectively contacting the upper portion of the U-shaped groove. Area 12 ',
14 'and 15' represent the contact openings of the respective regions.
【０００５】図中の破線Ａ−Ａ´に於ける断面構造が図
３である。チャネルとなる高抵抗のシリコン基板２０の
一主表面にＵ字型の溝２０´が設けられ、その溝２０´
の側壁には薄いゲート絶縁膜２１を介して多結晶シリコ
ンのゲート電極１２が形成されている。Ｕ字型の溝２０
´の底部に接する領域１４がｎ型で高不純物密度のソー
ス領域、Ｕ字型の溝２０´の上部に接する領域１５がｎ
型で高不純物密度のドレイン領域である。チャネルの導
電型は一方の導電型でも他方の導電型でもかまわない
が、少なくとも動作状態の一部において確実に空乏化す
べくその不純物密度が決定されている。このような動作
状態に於いては、ソース前面のチャネル中に電位障壁が
形成され、この電位障壁の高さによってキャリアの量が
制御されるので、ドレイン電流はゲート電圧のみならず
ドレイン電圧に対しても指数関数的に変化する。この電
位障壁は必ずしもシリコン基板２０とゲート絶縁膜２１
の界面に形成する必要はなく、シリコン基板２０の内部
に形成すれば良いから大きな駆動能力を得ることができ
る。FIG. 3 shows a sectional structure taken along a broken line AA 'in the figure. A U-shaped groove 20 ′ is provided on one main surface of the high-resistance silicon substrate 20 to be a channel, and the groove 20 ′ is formed.
A gate electrode 12 made of polycrystalline silicon is formed on the side wall of the via a thin gate insulating film 21. U-shaped groove 20
The region 14 in contact with the bottom of the ′ ′ is an n-type source region with high impurity density, and the region 15 in contact with the upper portion of the U-shaped groove 20 ′ is n
It is a drain region having a high impurity density in a mold. The conductivity type of the channel may be one conductivity type or the other conductivity type, but the impurity density thereof is determined so as to ensure depletion at least in a part of the operating state. In such an operating state, a potential barrier is formed in the channel on the front surface of the source, and the amount of carriers is controlled by the height of the potential barrier. But it changes exponentially. This potential barrier is not necessarily the silicon substrate 20 and the gate insulating film 21.
It is not necessary to form it at the interface of the above, and it is sufficient to form it inside the silicon substrate 20, so that a large driving capability can be obtained.
【０００６】従来の切り込み型絶縁ゲート静電誘導トラ
ンジスタのスイッチング時間と消費電力の関係（ｐ−τ
積）のＵ字型の溝２０´の深さに対する依存性を図５に
示す。図５において、ＡがＵ字型の溝２０´の深さ０．
８μｍの場合、ＢがＵ字型の溝２０´の深さ０．９μｍ
の場合である。Ｕ字型の溝２０´の深さが減少するに従
って、ｐ−τ積が改善されていることがわかる。Ｕ字型
の溝２０´の深さが０．５μｍのトランジスタに於いて
は既に４９ｐｓｅｃ／ｇａｔｅのスイッチング時間が消
費電力７ｍＷ／ｇａｔｅの時に得られている。（Ｊ．Ｎ
ishizawa et.al.ＩＥＥＥ Ｔran.on Ｅlectron Ｄ
evices, Ｖol. ＥＤ−３７，Ｎo.８，ＰＰ．１８７７〜
１８３３（１９９０））The relationship between the switching time and the power consumption of a conventional cut-type insulated gate static induction transistor (p-τ
FIG. 5 shows the dependence of (product) on the depth of the U-shaped groove 20 '. In FIG. 5, A is a depth of 0.
In the case of 8 μm, B has a U-shaped groove 20 ′ with a depth of 0.9 μm
Is the case. It can be seen that the p- [tau] product improves as the depth of the U-shaped groove 20 'decreases. In a transistor having a U-shaped groove 20 ′ having a depth of 0.5 μm, a switching time of 49 psec / gate is already obtained when the power consumption is 7 mW / gate. (JN
ishizawa et.al. IEEE Tran.on Electron D
evices, Vol. ED-37, No. 8, PP. From 1877
1833 (1990))
【０００７】[0007]
【発明が解決しようとする課題】このようにＵ字型の溝
２０´の深さを浅くすれば特性が改善されることは明ら
かであるが、Ｕ字型の溝２０´を浅くするのにあたって
は次のような問題点があった。図４が前述の図２の破線
Ｂ−Ｂ´に於ける断面構造図である。高抵抗のシリコン
基板２０の一主表面にＵ字型の溝２０´が設けられ、厚
いフィールド酸化膜３１に覆われたＵ字型の溝２０´の
側壁部分にゲートパッドと接続するための多結晶シリコ
ンのゲート電極１２が形成されている。選択酸化によっ
て形成するフィールド酸化膜３１の厚さに対してＵ字型
の溝２０´の深さが深い場合には問題無いが、Ｕ字型の
溝２０´が浅くなってくるにしたがって同図のＣで示し
たＵ字型の溝２０´の側壁の垂直部分が減少する。する
と、ゲート電極１２の多結晶シリコンは異方性エッチン
グで形成するために十分な膜厚が確保できなくなり、ひ
どい場合にはこの部分に於いて多結晶シリコンの剥離、
断線が生じて歩留まりの低下につながる。通常は約５０
０ｎｍ程度のフィールド酸化膜厚を用いるので、Ｕ字型
の溝２０´の深さが０．５μｍ以下になって来るとこの
問題は無視出来ない。It is apparent that the characteristics can be improved by making the depth of the U-shaped groove 20 'shallow as described above, but in making the U-shaped groove 20' shallow. Had the following problems. FIG. 4 is a sectional structural view taken along the broken line BB ′ in FIG. 2 described above. A U-shaped groove 20 ′ is provided on one main surface of the high-resistance silicon substrate 20, and a sidewall portion of the U-shaped groove 20 ′ covered with a thick field oxide film 31 is used for connecting to a gate pad. A gate electrode 12 of crystalline silicon is formed. There is no problem when the depth of the U-shaped groove 20 'is deeper than the thickness of the field oxide film 31 formed by selective oxidation, but as the U-shaped groove 20' becomes shallower, the same figure is shown. The vertical portion of the sidewall of the U-shaped groove 20 'indicated by C is reduced. Then, the polycrystalline silicon of the gate electrode 12 cannot secure a sufficient film thickness to be formed by anisotropic etching. In the worst case, the polycrystalline silicon peels off at this portion.
A wire break will occur, leading to a decrease in yield. Usually about 50
Since a field oxide film thickness of about 0 nm is used, this problem cannot be ignored when the depth of the U-shaped groove 20 'becomes 0.5 μm or less.
【０００８】本発明の目的は前述の欠点をなくし、フィ
ールド酸化膜の厚さと同程度かあるいはそれよりも浅い
Ｕ字型の溝に対しても垂直側壁を有したフィールド酸化
膜を形成せしめ、ゲート電極の多結晶シリコンを異方性
エッチングで形成する際に於いても、膜減りや断線の生
じる事がなく歩留まりが高い切り込み型絶縁ゲート静電
誘導トランジスタの製造方法を提供することにある。The object of the present invention is to eliminate the above-mentioned drawbacks and to form a field oxide film having vertical sidewalls even in a U-shaped groove having a thickness equal to or shallower than the thickness of the field oxide film. It is another object of the present invention to provide a method for manufacturing a cut-type insulated gate static induction transistor which has a high yield without causing film loss or disconnection even when polycrystalline silicon of an electrode is formed by anisotropic etching.
【０００９】[0009]
【課題を解決するための手段】本発明は上記課題を解決
するために、半導体基板の一主表面にＵ字型の溝を形成
する工程と、前記一主表面にシリコン窒化膜を堆積し、
パターニングした後、選択酸化により厚いフィールド酸
化膜を形成する工程を含んだ切り込み型絶縁ゲート静電
誘導トランジスタの製造方法において、厚いフィールド
酸化膜を形成する部分のＵ字型の溝の側壁に窒化膜を残
したままで、略Ｕ字型の溝の深さと同じ厚さの選択酸化
を行い、該Ｕ字型溝の側壁にも酸化膜を形成せしめたこ
とを特徴とするものである。In order to solve the above problems, the present invention provides a step of forming a U-shaped groove on one main surface of a semiconductor substrate, and depositing a silicon nitride film on the one main surface,
After patterning, a thick field acid is formed by selective oxidation.
In the manufacturing method of inclusive cut insulated gate static induction transistor forming a monolayer, thick field
Selective oxidation having the same thickness as the depth of the substantially U-shaped groove while leaving the nitride film on the sidewall of the U-shaped groove where the oxide film is to be formed.
Then, an oxide film is formed also on the side wall of the U-shaped groove .
【００１０】[0010]
【作用】本発明に於いては、選択酸化のマスク材となる
窒化膜をパターニングする際に異方性プラズマエッチン
グを用いて、Ｕ字型の溝の側壁に窒化膜を残したまま
で、選択酸化を行うという方法を取る。この方法によれ
ば、側壁の窒化膜の幅がＵ字型の溝の深さと同程度と狭
いため、酸素の拡散によって側壁にも酸化膜は形成され
るが（いわゆるバーズビークの侵入）、窒化膜の存在に
よって形状変化が抑制されて垂直に近い側壁を保つこと
が出来る。従って、その後に多結晶シリコンを堆積させ
て異方性エッチングを行っても、厚い酸化膜に覆われた
Ｕ字型の溝の側壁に十分な厚さの多結晶シリコンを残す
ことが出来る。In the present invention, anisotropic plasma etching is used when patterning a nitride film that serves as a mask material for selective oxidation, and the selective oxidation is performed while leaving the nitride film on the sidewall of the U-shaped groove. Take the method of doing. According to this method, since the width of the nitride film on the side wall is as narrow as the depth of the U-shaped groove, an oxide film is also formed on the side wall due to oxygen diffusion (so-called bird's beak penetration), but the nitride film Due to the presence of, the shape change can be suppressed and the side wall close to vertical can be maintained. Therefore, even if polycrystalline silicon is subsequently deposited and anisotropic etching is performed, the polycrystalline silicon having a sufficient thickness can be left on the sidewalls of the U-shaped groove covered with the thick oxide film.
【００１１】[0011]
【実施例】以下図面を参照して本発明の実施例を詳細に
説明する。図１は本発明切り込み型絶縁ゲート静電誘導
トランジスタの製造方法の製造工程のフローチャートで
ある。Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a flow chart of a manufacturing process of a method for manufacturing a notch type insulated gate static induction transistor of the present invention.
【００１２】（ａ） 高抵抗のシリコン基板４０の一主
表面に異方性プラズマエッチングによってＵ字型の溝４
０´を形成する。このようなエッチングは例えばＰＣｌ
3 を用いた、０．０５ Ｔｏｒｒ程度の圧力の高周波プ
ラズマ中で実現できる。(A) A U-shaped groove 4 is formed on one main surface of a high-resistance silicon substrate 40 by anisotropic plasma etching.
0'is formed. Such etching is performed by using, for example, PCl
It can be realized in a high-frequency plasma having a pressure of about 0.05 Torr using 3
【００１３】（ｂ）全面にシリコン窒化膜４３を堆積さ
せ、異方性プラズマエッチングによってＵ字型の溝４０
´の側壁にシリコン窒化膜４３を残すようにパターニン
グする。このようなエッチングは例えばＣ3 Ｆ8 を用
い、０．１ Ｔｏｒｒ程度の圧力で行えばよい。(B) A silicon nitride film 43 is deposited on the entire surface, and U-shaped groove 40 is formed by anisotropic plasma etching.
Patterning is performed so that the silicon nitride film 43 is left on the side wall of ‘′. Such etching may be performed using, for example, C 3 F 8 at a pressure of about 0.1 Torr.
【００１４】（ｃ）選択酸化法によってフィールド酸化
膜４１を形成する。このときＵ字型の溝４０´の側壁の
シリコン窒化膜４３の幅が狭いため、バーズビークの侵
入によって側壁にも十分な厚さのフィールド酸化膜４１
が成長する。その後、燐酸ボイル等によってシリコン窒
化膜４３を除去する。(C) The field oxide film 41 is formed by the selective oxidation method. At this time, since the width of the silicon nitride film 43 on the side wall of the U-shaped groove 40 'is narrow, the field oxide film 41 having a sufficient thickness is formed on the side wall due to the bird's beak.
Grows. After that, the silicon nitride film 43 is removed by boiling phosphoric acid or the like.
【００１５】（ｄ）全面に多結晶シリコン４２を堆積さ
せ、異方性プラズマエッチングによってＵ字型の溝４０
´の側壁に多結晶シリコン４２を残すようにパターニン
グする。このようなエッチングはＳＦ6 ＋Ｏ2 を用い、
０．１ Ｔｏｒｒ程度の圧力で行うことが出来る。(D) Polycrystalline silicon 42 is deposited on the entire surface, and U-shaped groove 40 is formed by anisotropic plasma etching.
Patterning is performed so that the polycrystalline silicon 42 is left on the side wall of '. For such etching, SF 6 + O 2 is used,
It can be performed at a pressure of about 0.1 Torr.
【００１６】このような工程によれば、選択酸化時に於
てＵ字型の溝４０´の側壁部にシリコン窒化膜４３が存
在することによりＵ字型の溝４０´の形状が丸くなるよ
うな変化が抑えられる。従って、フィールド酸化膜４１
の膜厚と同程度かあるいはそれ以下の深さのＵ字型の溝
４０´の場合でも、選択酸化後も比較的垂直に近い側壁
が得られる。According to such a process, the U-shaped groove 40 'is rounded due to the presence of the silicon nitride film 43 on the sidewall of the U-shaped groove 40' during the selective oxidation. Change is suppressed. Therefore, the field oxide film 41
Even in the case of the U-shaped groove 40 'having a depth of about the same as or less than the film thickness of, the side wall that is relatively vertical is obtained even after the selective oxidation.
【００１７】[0017]
【発明の効果】以上述べたように本発明によれば、深さ
と同程度かそれよりも厚いフィールド酸化膜に覆われた
Ｕ字型の溝においても垂直形状の側壁を実現でき、多結
晶シリコンのゲート電極の膜減りや断線を防ぐことが出
来る。従って、短チャネルで高速・低消費電力動作が可
能な切り込み型絶縁ゲート静電誘導トランジスタを製造
でき、その工業的価値は大きい。As described above, according to the present invention, a vertical sidewall can be realized even in a U-shaped groove covered with a field oxide film which is as thick as or thicker than the depth, and polycrystalline silicon can be realized. It is possible to prevent film loss and disconnection of the gate electrode. Therefore, it is possible to manufacture a slit type insulated gate static induction transistor capable of operating at high speed and low power consumption in a short channel, and its industrial value is great.
【図１】本発明の製造工程のプロセスフローチャートで
ある。FIG. 1 is a process flow chart of a manufacturing process of the present invention.
【図２】従来の切り込み型絶縁ゲート静電誘導トランジ
スタの平面パターン図である。FIG. 2 is a plan pattern view of a conventional cut-type insulated gate static induction transistor.
【図３】図２のＡ−Ａ´線断面図である。3 is a cross-sectional view taken along the line AA ′ of FIG.
【図４】図２のＢ−Ｂ´線断面図である。FIG. 4 is a sectional view taken along line BB ′ of FIG.
【図５】従来の切り込み型絶縁ゲート静電誘導トランジ
スタのスイッチング時間と消費電力の関係のＵ字型の溝
の深さ依存性を示す特性図である。FIG. 5 is a characteristic diagram showing the depth dependency of a U-shaped groove in the relationship between the switching time and the power consumption of a conventional cut-type insulated gate static induction transistor.
４０…シリコン基板、４０´…Ｕ字型の溝、４１…フィ
ールド酸化膜、４２…多結晶シリコン、４３…シリコン
窒化膜。40 ... Silicon substrate, 40 '... U-shaped groove, 41 ... Field oxide film, 42 ... Polycrystalline silicon, 43 ... Silicon nitride film.
Claims (1)
成する工程と、前記一主表面にシリコン窒化膜を堆積
し、パターニングした後、選択酸化により厚いフィール
ド酸化膜を形成する工程を含んだ切り込み型絶縁ゲート
静電誘導トランジスタの製造方法において、厚いフィー
ルド酸化膜を形成する部分のＵ字型の溝の側壁に窒化膜
を残したままで、略Ｕ字型の溝の深さと同じ厚さの選択
酸化を行い、該Ｕ字型溝の側壁にも酸化膜を形成せしめ
たことを特徴とする切り込み型絶縁ゲート静電誘導トラ
ンジスタの製造方法。1. A step of forming a U-shaped groove on one main surface of a semiconductor substrate, and a thick field by selective oxidation after depositing and patterning a silicon nitride film on the one main surface.
In the manufacturing method of inclusive cut insulated gate static induction transistor forming a de oxide film, thicker fee
Selection of the same thickness as the depth of the substantially U-shaped groove while leaving the nitride film on the sidewall of the U-shaped groove where the oxide film is formed.
Oxidize and form an oxide film on the sidewall of the U-shaped groove.
A method of manufacturing a notch type insulated gate static induction transistor characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3243140A JPH0821716B2 (en) | 1991-09-24 | 1991-09-24 | Method for manufacturing notched insulated gate static induction transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3243140A JPH0821716B2 (en) | 1991-09-24 | 1991-09-24 | Method for manufacturing notched insulated gate static induction transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05102486A JPH05102486A (en) | 1993-04-23 |
| JPH0821716B2 true JPH0821716B2 (en) | 1996-03-04 |
Family
ID=17099388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3243140A Expired - Lifetime JPH0821716B2 (en) | 1991-09-24 | 1991-09-24 | Method for manufacturing notched insulated gate static induction transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0821716B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63131583A (en) * | 1986-11-21 | 1988-06-03 | Res Dev Corp Of Japan | Manufacture of cut type insulated-gate electrostatic induction transistor |
-
1991
- 1991-09-24 JP JP3243140A patent/JPH0821716B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05102486A (en) | 1993-04-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2728671B2 (en) | Manufacturing method of bipolar transistor | |
| JP2503460B2 (en) | Bipolar transistor and manufacturing method thereof | |
| EP0076105B1 (en) | Method of producing a bipolar transistor | |
| JP3213549B2 (en) | Manufacturing method of super self-aligned bipolar transistor | |
| JPH08195433A (en) | Semiconductor device and manufacturing method thereof | |
| US7485534B2 (en) | Method of manufacture of a trench-gate semiconductor device | |
| JP3346348B2 (en) | Method for manufacturing semiconductor device | |
| US5882976A (en) | Method of fabricating a self-aligned double polysilicon NPN transistor with poly etch stop | |
| JPS63244775A (en) | Semiconductor device and manufacture of the same | |
| JP3002964B2 (en) | Manufacturing method of bipolar semiconductor device | |
| JPH05102486A (en) | Manufacture of notched insulated gate electrostatic induction transistor | |
| JPS62229880A (en) | Semiconductor device and manufacture thereof | |
| JP2001053276A (en) | Method of forming vertical semiconductor device having increased source contact area | |
| US6222249B1 (en) | Semiconductor device | |
| KR0161118B1 (en) | Semiconductor device manufacturing method | |
| JP3352941B2 (en) | Semiconductor device | |
| JPS5940571A (en) | Semiconductor device | |
| JP2531688B2 (en) | Method for manufacturing semiconductor device | |
| JPH05343440A (en) | Charge transfer element and manufacture thereof | |
| KR100286349B1 (en) | Method of fabricating a semiconductor device | |
| KR940006082B1 (en) | Semiconductor device isolation method | |
| JP2546651B2 (en) | Method of manufacturing bipolar transistor | |
| JPS5963762A (en) | Manufacture of semiconductor device | |
| JPH02304931A (en) | Semiconductor device and manufacture thereof | |
| JPH11289082A (en) | Semiconductor device and method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| R370 | Written measure of declining of transfer procedure |
Free format text: JAPANESE INTERMEDIATE CODE: R370 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080304 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090304 Year of fee payment: 13 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090304 Year of fee payment: 13 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090304 Year of fee payment: 13 |
|
| EXPY | Cancellation because of completion of term |