JPH0822400A - Microcomputer testability circuit - Google Patents

Abstract

(57) [Summary] [Purpose] Even if the number of external output terminals of a microcomputer is limited, it is possible to observe failures generated in a logic circuit from the external output terminals. [Configuration] A test pattern for verifying the operation of the microcomputer 8 has first and second external input terminals 10 and 11.
Is input to the first logic circuit block 1. A first circuit comprising signal lines 34 to 45 from the second logic circuit block 3
Internal bus 82 and a third internal bus 83 composed of signal lines 53 to 62 from the third logic circuit block are input to the first selector 90, and the first selector 90 is connected to the first internal bus 82. Alternatively, it outputs the third internal bus 83. The encoder 92 encodes the signal output from the signal line forming the internal bus output from the first selector 90 and outputs the encoded signal to the fourth internal bus 93. The second selector 94 outputs the fourth internal bus 93 from the encoder 92 or the second internal bus 68 including the signal lines 63 to 67 from the fourth logic circuit block 7 to the external output terminals 77 to 81. To do.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a testable circuit for a microcomputer, and more specifically, a microcomputer having a plurality of logic circuit blocks, which are composed of a plurality of logic circuits such as combinational circuits and sequential circuits, connected in series. By inputting a test pattern for operation verification from the external input terminal of the computer and comparing the signal value output from the external output terminal of the microcomputer at the time of fault generation and at the time of normal generation, it is generated in the plurality of logic circuits. The present invention relates to a testability circuit of a microcomputer for observing a failure that occurs.

[0002]

2. Description of the Related Art A conventional test facilitation circuit for a microcomputer will be described below with reference to the drawings.

FIG. 2 is a plan view of a conventional testability circuit. In FIG. 2, reference numerals 1, 3, 5, and 7 are first, second, third, and fourth logic circuit blocks which form the microcomputer 8, and are first to fourth logic circuit blocks 1 and 1.
Reference numerals 3, 5 and 7 each include a plurality of logic circuits such as combinational circuits and sequential circuits.

In FIG. 2, reference numerals 30, 31, and 32 denote first, second, and third logic circuits constituting the second logic circuit block 3, and the first to third logic circuits 30 to 32 are Each is composed of a plurality of logic circuits. Also, 33
Is a partial circuit forming the second logic circuit 31, and the partial circuit 33 is also formed of a plurality of logic circuits.
Reference numerals 50, 51, and 52 are first, second, and third logic circuits that form the third logic circuit block 5, and
Each of the third logic circuits 50 to 52 is also composed of a plurality of logic circuits. Reference numerals 70, 71, and 72 are first, second, and third logic circuits that form the fourth logic circuit block 7, and are the first, second, and third logic circuits 70 to 72.
Each is also composed of a plurality of logic circuits.

In FIG. 2, reference numerals 10 and 11 denote first and second external input terminals for inputting a test pattern for verifying the operation of the microcomputer 8, 12, 13, 14, 15, and 1, respectively.
Reference numerals 6, 17, 18, 19 denote the output signal of the first logic circuit block 1 and the first logic circuit 3 of the second logic circuit block 3.
Signal lines for transmitting 0, 20, 21, 22, 23 are signal lines for transmitting the output signal of the first logic circuit block 1 to the second logic circuit 31 of the second logic circuit block 3, 24, 2
Reference numerals 5, 26 and 27 are signal lines for transmitting the output signal of the first logic circuit block 1 to the third logic circuit 32 of the second logic circuit block 3.

In FIG. 2, reference numerals 34, 35, 36 and 37 transmit an output signal from the first logic circuit 30 of the second logic circuit block 3 to the first logic circuit 50 of the third logic circuit block 5. Signal lines 38, 39 for transmitting the output signal from the second logic circuit 31 of the second logic circuit block 3 to the second logic circuit 51 of the third logic circuit block 5, 40, 41 , 42, 43, 44, 45 are signal lines for transmitting the output signal from the third logic circuit 32 of the second logic circuit block 3 to the third logic circuit 52 of the third logic circuit block 5.

In FIG. 2, 53 and 54 are signal lines for transmitting an output signal from the first logic circuit 50 of the third logic circuit block 5 to the first logic circuit 70 of the fourth logic circuit block 7. 55 and 56 are signal lines for transmitting the output signal from the second logic circuit 51 of the third logic circuit block 5 to the second logic circuit 71 of the fourth logic circuit block 7, 57 and
Reference numerals 58, 59, 60, 61, and 62 are signal lines for transmitting an output signal from the third logic circuit 52 of the third logic circuit block 5 to the third logic circuit 72 of the fourth logic circuit block 7. . First logic circuit 3 of second logic circuit block 3
Signal lines 34 and 35 from 0, the second logic circuit block 3
Signal line 40 from the third logic circuit 32, the signal line 53 from the first logic circuit 50 of the third logic circuit block 5, and the signal from the third logic circuit 52 of the third logic circuit block 5. The line 57 constitutes the first internal bus 46.

In FIG. 2, 63, 64, 65, 66,
67 is provided from the third logic circuit 72 of the fourth logic circuit block 7 which outputs data and clocks from a communication function block (hereinafter referred to as serial) which is a peripheral function of the microcomputer 8 and a timer block. The signal lines 63 to 67 form a second internal bus 68. Further, 84 is a third external input terminal, 85 is a selector, and the selector 85 selects and outputs either one of the first internal bus 46 and the second internal bus 68. To do. Also, 77, 78, 79, 80, 8
Each of the external output terminals 1 is an external output terminal 7
7 to 81 output the signal value of the first internal bus 46 or the second internal bus 68 selected by the selector 85.

In FIG. 2, 73 is an external output terminal for observing the output signal of the first logic circuit 70 of the fourth logic circuit block 7, and 74 is a second logic circuit 71 of the fourth logic circuit block 7. External output terminal for observing output signal, 75,
Reference numeral 76 denotes the third logic circuit 72 of the fourth logic circuit block 7.
This is an external output terminal for observing the output signal of.

The operation of the test facilitation circuit of the microcomputer configured as described above will be described below.

First, a test pattern for verifying the operation of the microcomputer 8 is provided with first and second external input terminals 1.
Input from 0 and 11. The first logic circuit block 1 is
A logical operation is performed by the input signals from the first and second external input terminals 10 and 11, and the operation result is signal line 12
To 27. The first logic circuit 30 of the second logic circuit block 3 corresponds to the signal line 1 of the first logic circuit block 1.
A logical operation is performed using the logical values output from 2 to 19 and the operation result is output to the signal lines 34 to 37. Second
The second logic circuit 31 of the logic circuit block 3 performs logical operation using the logical values output from the signal lines 20 to 23 of the first logic circuit block 1 and outputs the operation result to the signal lines 38 and 39. Output to. The logic circuit 32 of the second logic circuit block 3 corresponds to the signal line 2 of the first logic circuit block 1.
A logical operation is performed using the logical values output from 4 to 27, and the operation result is output to the signal lines 40 to 45.

The first logic circuit 50 of the third logic circuit block 5 includes the signal lines 34 to 3 of the second logic circuit block 3.
A logical operation is performed using the logical value output from 7 and the operation result is output to the signal lines 53 and 54. The second logic circuit 51 of the third logic circuit block 5 performs a logic operation using the logic values output from the signal lines 38 and 39 of the second logic circuit block 3 and outputs the operation result to the signal line 5
Output to 5,56. Third of third logic circuit block 5
Of the second logic circuit block 3 is connected to the signal line 4 of the second logic circuit block 3.
A logical operation is performed using the logical values output from 0 to 45, and the operation result is output to the signal lines 57 to 62.

The first logic circuit 70 of the fourth logic circuit block 7 is connected to the signal lines 53, 5 of the third logic circuit block 5.
A logical operation is performed by using the logical value output from No. 4, and the operation result is output to the external output terminal 73. The second logic circuit 71 of the fourth logic circuit block 7 performs a logic operation using the logic values output from the signal lines 55 and 56 of the third logic circuit block 5, and outputs the operation result to the external output terminal. Output to 74. The third logic circuit 72 of the fourth logic circuit block 7 is connected to the signal line 5 of the third logic circuit block 5.
A logical operation is performed using the logical values output from 7 to 62, and the operation result is output to the external output terminals 75 and 76.

When the selector 85 selects the second internal bus 68 by the control signal input from the third external input terminal 84, the selector 85 supplies data and clock such as serial and timer which are peripheral function blocks of the microcomputer 8. To output to the external output terminals 77 to 81. At this time, the external output terminals 77 to 81 function as general-purpose ports.
Further, when the selector 85 selects the first internal bus 46 by the control signal input from the third external input terminal 84, the selector 85 outputs the logical value of the first internal bus 46 to the external output terminals 77 to 81. Output. At this time, the external output terminal 77
˜81 function as test terminals that allow the output signal of the logic circuit to be directly observed from the outside.

[0015]

[Table 1]

Table 1 shows the first part of the second logic circuit block 3.
Of the test patterns for detecting the faults generated on the input / output signal lines of the logic circuit 30, the first logic circuit 50 of the third logic circuit block 5, and the first logic circuit 70 of the fourth logic circuit block 7. The first logic circuit block 1 performs a logical operation on the test pattern input from the first and second external input terminals 10 and 11 and the second logic circuit block. 3 patterns of the signal lines 12 to 19 output to the first logic circuit 30;
According to the pattern, the first logic circuit 30 of the second logic circuit block 3 performs a logic operation and outputs the logic value to the signal lines 34 to 37, and the first logic circuit 50 of the third logic circuit block 5 The logical values output to the signal lines 53 and 54 are shown. The failure here means that the output signal is always Vdd (corresponding to a logical value of 1) or V, regardless of the input signal, due to the destruction of the transistors forming each logic circuit.
This is a case where the value is fixed to ss (corresponding to a logical value of 0) and a logical value different from the correct theoretical value is output.

When the test pattern is input to the microcomputer 8 from the first and second external input terminals 10 and 11 when the above-mentioned failure is generated, the output value of the microcomputer 8 becomes the expected output value at the normal time. May be different. Therefore, it is necessary to select a defective product that includes the above-described failure and a non-defective product that does not include the failure. Table 1 compares the signal values output from the first and second external input terminals 10 and 11 between the time when the fault is generated and the time when the fault is generated to detect the fault generated in the logic circuit. The test pattern for failure simulation is shown. By inputting 12 patterns of columns A to L of Table 1 to the first logic circuit 30 of the second logic circuit block 3, the first logic circuit 30 of the second logic circuit block 3 is turned on. The failure generated in the output signal line, the input / output signal line of the first logic circuit 50 of the third logic circuit block 5, and the input / output signal line of the first logic circuit 70 of the fourth logic circuit block 7 Can be detected.

However, since the test pattern for verifying the actual device is generally created by trial and error, it often includes a redundant pattern.

Therefore, conventionally, the output signal lines 34 and 3 of the first logic circuit 30 of the second logic circuit block 3 are used.
5 can be observed from the external output terminals 77 and 78 and the third
It is possible to provide the selector 85 so that the output signal line 53 of the first logic circuit 50 of the logic circuit block 5 can be observed from the external output terminal 79 and use the external output terminals 77, 78, 79 as test terminals. I have to. This allows
It suffices to consider the test pattern in the circuits up to immediately before the external output terminals 77, 78, 79, and it is possible to create the test pattern in a state where the circuit scale is apparently small. As a result, the test pattern is easily created, and the number of redundant test patterns is reduced. Therefore, the second
The patterns of the signal lines 12 to 19 input to the first logic circuit 30 of the logic circuit block 3 of FIG.
The failure can be detected by substituting the eight patterns up to the row.

[0020]

However, a large-scale microcomputer actually has one million or more transistors. For this reason, according to the conventional test facilitation circuit, it is difficult to increase the number of external output terminals that enable detection of a failure in a logic circuit in response to an increase in circuit scale because the total number of external output terminals is limited. is there. That is, in an actual microcomputer, the case where the test pattern can be created in the state where the circuit scale is small is very limited.

In the conventional test facilitation circuit, the operation verification of the microcomputer is performed by inputting the test pattern for the purpose of the operation verification from the external input terminal and observing the control result of the microcomputer from the external output terminal. I've done it.

Therefore, in the conventional test facilitation circuit, the test pattern for verifying the operation becomes longer and the test pattern for confirming each function increases as the function of the microcomputer increases and the circuit scale increases. There is a problem that the number of

Further, since a failure simulation for detecting a failure in a logic circuit of a microcomputer is often created based on a test pattern for checking a function, a test pattern for detecting a failure in a logic circuit forming a complicated microcomputer. Is difficult to create.

Further, in order to simplify the test pattern and reduce the number of test patterns, the output signal of the logic circuit forming the microcomputer may be output from the external output terminal. Is limited, the number of output signals of the logic circuit that can be output to the outside is limited. Therefore, when the above method is adopted, there is a problem that sufficient operation verification cannot be performed.

The present invention solves the above-mentioned conventional problems, and even when the number of external output terminals of a microcomputer is limited, it is possible to observe a fault generated in a logic circuit from the external output terminals. The purpose is to be able to.

[0026]

In order to achieve the above object, the invention of claim 1 is such that a plurality of logic circuit blocks including a plurality of logic circuits such as combination circuits and sequential circuits are connected in series. The test pattern for operation verification is input from the external input terminal of the microcomputer, and the signal value output from the external output terminal of the microcomputer is compared to the plurality of logic circuits at the time of failure generation and at the time of normal operation. Targeting a test facilitating circuit of a microcomputer for observing a generated fault, each output signal output from a plurality of logic circuits forming one logic circuit block is input and corresponds to each output signal. This is a configuration including an encoder that outputs a combined signal.

According to a second aspect of the present invention, a test for operation verification is performed from an external input terminal of a microcomputer in which a plurality of logic circuit blocks including a plurality of logic circuits such as combination circuits and sequential circuits are connected in series. A test of a microcomputer for observing a failure generated in the plurality of logic circuits by inputting a pattern and comparing a signal value output from an external output terminal of the microcomputer between a failure generation time and a normal time Targeting the facilitation circuit, one output signal group consisting of each output signal output from the plurality of logic circuits forming one logic block and each output output from the plurality of logic circuits forming another logic block The other output signal group consisting of signals is input and one of the output signal group and the other output signal group is output. And 択器, a configuration in which the output signal constituting the output signal group output from the selector is provided with an encoder for outputting a combination signal corresponding to the inputted respective output signal.

[0028]

According to the structure of claim 1, a code for inputting each output signal output from a plurality of logic circuits constituting one logic circuit block and outputting a combination signal corresponding to each output signal to an external output terminal Since each output signal output from a plurality of logic circuits is encoded into a combined signal and output to the external output terminal, the output signal from the encoder is output from the encoder more than the number of signals input to the encoder. Since the number of signals output is smaller, the number of signals output to the external output terminal is reduced. This reduces the number of output signals of the logic circuit that are not output to the outside.

According to the second aspect of the invention, one output signal group consisting of the output signals output from the plurality of logic circuits forming one logic block and the plurality of logic circuits forming the other logic blocks are output. When a selector that outputs one of the output signal groups of the other output signal groups consisting of the respective output signals and each output signal that constitutes the output signal group output from the selector are input, An encoder that outputs a combined signal corresponding to each output signal to an external output terminal is provided, so that each output signal that constitutes one or another output signal group is selectively output from each selector. Since the output signals are encoded by the encoder and output as a combined signal to the external output terminal, the output signals output from the logic circuits forming one and other logic blocks are output by the selector and the encoder. It is reduced in two stages. This allows
The number of output signals of the logic circuit which is not output to the outside is significantly reduced.

[0030]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of a test facilitation circuit according to an embodiment of the present invention. 1, the first to fourth logic circuit blocks 1, 3, 5, and 7, the microcomputer 8, the first and second external input terminals 10 and 11, and the signal line 1
2 to 27, the first to third logic circuits 30 to 32 of the second logic circuit block 3, and the partial circuit 3 of the third logic circuit 32.
3, the signal lines 34 to 45, the first to third logic circuits 50 to 52 of the third logic circuit block 5, the signal lines 53 to 62, the second internal bus 68, and the fourth logic circuit block 7 1 to
Third logic circuits 70-72, external output terminals 73-76,
The third external input terminal 84 and the external output terminals 77 to 81 have the same configurations as those of the conventional example shown in FIG.

In FIG. 1, reference numeral 82 designates a plurality of signal lines 34-.
A first internal bus from the second logic circuit block 3 consisting of 45, and a third internal bus from the third logic circuit block 5 consisting of a plurality of signal lines 53 to 62. Further, 90 is a first selector as a selector, and the first selector 90 selects and outputs either one of the first internal bus 82 and the third internal bus 83. Also, 91
Is a selection controller for controlling the first selector 90.

In FIG. 1, reference numeral 92 designates an encoder, which is an output signal of a signal line constituting the first internal bus 82 or the third internal bus 83 selected by the first selector 90. Is encoded and a combination signal corresponding to the output signal is output. Further, 93 is a fourth internal bus encoded by the encoder 92.

In FIG. 1, reference numeral 94 is a second selector, and the second selector 94 is a fourth internal bus 93 and a second selector.
And outputs one of the internal buses 68. The second selector 94 is also controlled by the selection controller 91.

Hereinafter, the operation of the test facilitation circuit according to the present embodiment having the above-described configuration will be described with reference to the first and second external input terminals 10 and 11, the first logic circuit block 1 and the first logic. Signal lines 12 to 19 from the circuit block 1, first logic circuits 30 of the second logic circuit block 3, and signal lines 34 from the first logic circuit 30 of the second logic circuit block 3 to
37, the first logic circuit 5 of the third logic circuit block 5
0, the signal lines 53 and 54 from the first logic circuit 50 of the third logic circuit block 5, the first logic circuit 70 of the fourth logic circuit block 7, and the first logic circuit block 7 of the fourth logic circuit block 7.
Output terminal 73 for outputting a signal from the logic circuit 70 of
Will be explained.

First, a test pattern for verifying the operation of the microcomputer 8 is provided with the first and second external input terminals 1.
Input from 0 and 11. The first logic circuit block 1 is
A logical operation is performed by the input signals from the first and second external input terminals 10 and 11, and the operation result is signal line 12
To ~ 19. The logic values output from the signal lines 12 to 19 of the first logic circuit block 1 are input to the first logic circuit 30 of the second logic circuit block 3. The first logic circuit 30 of the second logic circuit block 3 includes the signal lines 12 to
A logical operation is performed using the logical value of 19, and the operation result is output to the signal lines 34 to 37. The signal lines 34 to 37 from the first logic circuit 30 of the second logic circuit block 3 are 2
One of them is input to the first logic circuit 50 of the third logic circuit block 5, and the other is the first of four of the 12 signal lines forming the first internal bus 82. It is input to the selector 90.

Similarly, the first of the third logic circuit block 5
Logic circuit 50 performs logical operation using the logic values output from the signal lines 34 to 37 from the first logic circuit 30 of the first logic circuit block 3 and outputs the operation result to the signal lines 53 and 54. Output to. The signal lines 53 and 54 from the first logic circuit 50 of the third logic circuit block 5 are branched into two, one of which is input to the first logic circuit 70 of the fourth logic circuit 7 and the other of which is It is input to the first selector 90 as two of the 10 signal lines forming the third internal bus 83.

The first logic circuit 70 of the fourth logic circuit block 7 performs a logic operation using the logic values of the signal lines 53 and 54 from the logic circuit 50 of the third logic circuit block 5, and the operation is performed. The result is output to the external output terminal 73.

The selection controller 91 has a third external input terminal 8
4 by using the signal value input from
And a third internal bus 83 to generate and output a control signal for selecting one of them, and the first selector 90 uses the control signal output by the selection controller 91 to output the first internal bus 82 or The third internal bus 83 is selected, and the selected internal bus is input to the encoder 92. Here, by using the first selector 90, the second logic circuit block 3
Signal lines 34 to 37 output from the first logic circuit 30 of
It becomes possible to compress the 6-bit signal of the signal lines 53 and 54 output from the first logic circuit 50 of the third logic circuit block 5 into a 4-bit signal, that is, the number of signals to 2/3. .

The encoder 92 encodes the internal bus selected by the first selector 90 and outputs the encoded signal to the fourth internal bus 93. At this time, the encoder 92
Can compress the signal width. The test pattern for verifying the operation of the microcomputer 8 is
There are 12 patterns of columns to L columns, but the signal line 34 output from the first logic circuit 30 of the second logic circuit block 3
The values of ˜37 have 6 patterns of rows A to F shown in Table 2 because there are overlapping values. Similarly, the values of the signal lines 53 and 54 output from the first logic circuit 50 of the third logic circuit block 5 are three patterns A to C shown in Table 2 because there are overlapping values. Thus, the 4-bit signal output from the first selector 90 is
As shown in FIG. 3, it can be represented by a 3-bit signal line, and the signal line width can be compressed.

[0041]

[Table 2]

When the signal output from the first selector 90 has a pattern other than those shown in Table 2,
An error signal from the encoder 92 (Table 2 in this embodiment)
In, all bits become Vdd, as shown in the item of the pattern not set. ) Is output.

The second selector 94 is one of the fourth internal bus 93 and the second internal bus 68 encoded by the encoder 92 according to the control signal input from the third external input terminal 84. One of them is selected and the signal value of the selected internal bus is output to the external output terminals 77-81. When the second selector 94 selects the fourth internal bus 93 and outputs its signal value to the external output terminals 77 to 81,
The external input terminals 77 to 81 function as test terminals, and the second
When the selector 94 of 1 selects the second internal bus 68 and outputs the signal value thereof to the external output terminals 77 to 81, the external input terminals 77 to 81 function as general-purpose ports.

As described above, according to this embodiment, the signal line width can be reduced in two steps by using the first selector 90 and the encoder 92. As the circuit becomes more sophisticated and the circuit scale increases in the future, the functions of the first selector 90 and the encoder 92 can be further expected. That is, when the circuit becomes large-scale, the number of output signals of the logic circuit also increases in comparison, but the number of external output terminals for outputting to the outside is limited, so that the output of the logic circuit that cannot be output to the outside is limited. The number of signals increases, and it becomes difficult to show the effect in operation verification. However, when the present embodiment is used, the output signals of the logic circuits can be compressed in two stages by using the first selector 90 and the encoder 92, as described above, so that the output signals of the plurality of logic circuits can be obtained. Can be observed from the external output terminal.

In other words, it is worth increasing the number of test terminals of the logic circuit while keeping the number of external output terminals unchanged. Then, as described above, the output signals from the first logic circuit 30 of the second logic circuit block 3 and the first logic circuit 50 of the third logic circuit block 5 are observed from the external output terminals 77 to 81. By
It becomes possible to detect a failure occurring in the first logic circuit 30 of the second logic circuit block 3 and the first logic circuit 50 of the third logic circuit block 5 by using a relatively simple test pattern. . In addition, the number of test patterns can be reduced, and as shown in Table 3, the failure simulation can be performed with 5 patterns of the columns A to E. This also makes it possible to shorten the test time.

[0046]

[Table 3]

It is also assumed that a fault that is difficult to detect is generated in the logic circuit in the microcomputer 8 because it is very complicated and difficult to control from the outside. For example, the third
Signal line 5 of the second logic circuit 51 of the logic circuit block 5 of
Since the output value from 5 is always fixed to 0, the output signal of the second partial circuit 71 of the fourth logic circuit block 7 is always 1 and is input from the first and second input terminals 10 and 11. This is the case where 1 is output from the output terminal 74 regardless of the test pattern that is set. In this case, according to the conventional test facilitation circuit, the signal line 39 of the second logic circuit 31 of the second logic circuit block 3 and the signal line 39 of the second logic circuit 51 of the third logic circuit block 5 are used. It is not possible to detect the fault generated at 56.

However, according to this embodiment, the signal line 39 of the second logic circuit 31 of the second logic circuit block 3 is used.
And the signal output from the signal line 56 of the second logic circuit 51 of the third logic circuit block 5 is observed from the external output terminal, so that the signal of the second logic circuit 31 of the second logic circuit block 3 is detected. Line 39 and third logic circuit block 5
It is possible to detect a failure generated in the signal line 56 of the second logic circuit 51 of (1), and it is possible to improve the failure detection rate.

As described above, according to the present embodiment, it is possible to detect a fault which cannot be detected by the conventional test facilitation circuit. It is particularly effective when there are many logic circuits that cannot be detected by the digitizing circuit.

[0050]

According to the test facilitation circuit of the microcomputer of the first aspect of the present invention, each output signal output from the plurality of logic circuits is encoded and output as a combination signal to the external output terminal. Since the number of signals output to the external output terminal is reduced, the number of output signals of the logic circuit not output to the outside is reduced. Therefore, even if the number of external output terminals of the microcomputer is limited, it is possible to suppress the reduction in the number of output signals output from the logic circuits that configure one logic circuit block, and thus configure one logic circuit block. It becomes possible to reliably observe the fault generated in the logic circuit that operates from the external output terminal.

According to the test facilitation circuit of the microcomputer of the second aspect of the present invention, each output signal forming one or another output signal group is selectively output from the selector,
Since each output signal output from the selector is encoded by the encoder to be a combined signal and output to the external output terminal, the output signal output from the logic circuit forming one or another logic block is the selector. And the encoder reduces the number of output signals from the logic circuits constituting one and the other logic circuit blocks even if the number of external output terminals of the microcomputer is limited. It is possible to further suppress, and thereby, it becomes possible to more reliably observe the failure generated in the logic circuit forming one or another logic circuit block from the external output terminal.

Therefore, according to the first or second aspect of the present invention, it is possible to reliably detect the fault generated in the logic circuit forming the logic circuit block by the short test pattern, which is very effective in verifying the operation of the logic circuit. Bring

[Brief description of drawings]

FIG. 1 is a plan view of a test facilitation circuit of a microcomputer according to an embodiment of the present invention.

FIG. 2 is a plan view of a conventional testability circuit of a microcomputer.

[Explanation of symbols]

 1 1st logic circuit block 3 2nd logic circuit block 5 3rd logic circuit block 7 4th logic circuit block 8 Microcomputer 10 1st external input terminal 11 2nd external input terminal 12-27 Signal line 30 1st logic circuit 31 2nd logic circuit 32 3rd logic circuit 33 Partial circuit 34-45 Signal line 50 1st logic circuit 51 2nd logic circuit 52 3rd logic circuit 53-62 Signal line 68 Second internal bus 70 First logic circuit 71 Second logic circuit 72 Third logic circuit 77 to 81 External output terminal 82 First internal bus 83 Third internal bus 84 Third external input terminal 90th 1 selector (selector) 91 selection controller 92 encoder 93 fourth internal bus 94 second selector

Claims (2)

[Claims] 1. A test pattern for operation verification is input from an external input terminal of a microcomputer in which a plurality of logic circuit blocks including a plurality of logic circuits such as a combinational circuit and a sequential circuit are connected in series, and the microcomputer is operated. A test facilitation circuit of a microcomputer for observing a failure generated in the plurality of logic circuits by comparing a signal value output from an external output terminal of the computer at the time of failure generation and a normal time, Each output signal output from a plurality of logic circuits forming one logic circuit block is input, and an encoder is provided for outputting a combination signal corresponding to each output signal to the external output terminal. Microcomputer testability circuit. 2. A test pattern for operation verification is input from an external input terminal of a microcomputer in which a plurality of logic circuit blocks including a plurality of logic circuits such as a combinational circuit and a sequential circuit are connected in series, and the microcomputer is operated. A test facilitation circuit of a microcomputer for observing a failure generated in the plurality of logic circuits by comparing a signal value output from an external output terminal of the computer at the time of failure generation and a normal time, One output signal group composed of output signals output from a plurality of logic circuits forming one logic block and another output signal composed of output signals output from a plurality of logic circuits forming another logic block And a selector for outputting one of the output signal group of the one output signal group and the other output signal group, and the selector. An easy test of a microcomputer, comprising: an encoder that inputs each output signal that constitutes an output signal group to be output and outputs a combination signal corresponding to each output signal to the external output terminal. Circuit.