JPH08228128A - Sampling frequency converter - Google Patents

Abstract

(57) [Abstract] [Purpose] A high-precision time-varying coefficient filter that does not require a PLL circuit and has a relatively simple configuration with little signal deterioration regardless of whether the input and output clock frequencies are synchronous or asynchronous. There is provided a sampling frequency conversion device using. An input data clock generator 6, a switch circuit 2, a time-varying coefficient filter reference clock generator 12, a frequency dividing circuit 11, a counter circuit 8, and a first latch circuit 1 are provided.
0, the time-varying coefficient filter circuit 3, and the switch circuit 4, in the sampling frequency converter, the input data clock signal from the input data clock generator 6 and the reference clock signal from the time-varying coefficient filter reference clock generator 12. And a second latch circuit 7 that outputs a sampling clock signal, and a sampling clock signal from a unit that outputs the sampling clock signal,
It has a third latch circuit 9 which receives the count value from the counter circuit as an input and outputs a reset value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly accurate sampling frequency converter that can be used in a wide range of equipment such as communication equipment, broadcasting equipment, and transmission equipment that performs digital signal processing, and a communication equipment using the sampling frequency conversion equipment. It is about.

[0002]

2. Description of the Related Art As one of the conventional digital filter conversions of sampling frequencies of digital signals, there is a sampling frequency conversion device using a time-varying coefficient filter shown in FIG. Note that the technique relating to the time-varying coefficient filter is disclosed in JP-A-4-332214.
No. 6,086,045. In FIG. 2, 1 is a data input terminal, 6 is an input data clock generator, 2 is a switch circuit for sampling input data by a clock signal from the input data clock generator 6, and 13 is a time-varying coefficient filter reference clock generator. (Voltage controlled oscillator), 14
Is a phase loop control circuit that controls the synchronization of the time-varying coefficient filter reference clock generator 13 to form a phase-locked loop circuit (PLL circuit); and 8 is a clock signal from the time-varying coefficient filter reference clock generator 13. A counter circuit 11 that divides the clock signal from the time-varying coefficient filter reference clock generator 13 by N,
Reference numeral 10 is a latch circuit, 15 is a time-varying coefficient filter circuit to which the sampled data from the switch circuit 2 and the counter value from the latch circuit are input, and 4 is time-varying by the clock signal from the N frequency dividing circuit 11. Coefficient filter circuit 1
A switch circuit 5 for sampling the output from 5 indicates a data output terminal.

FIG. 2 shows an input data clock generator 6 and
1 shows a configuration of a sampling frequency conversion device using a time-varying coefficient filter circuit when the time-varying coefficient reference clock generator 13 which is a voltage controlled oscillator of a PLL circuit is used in synchronization. Input data such as a sampled digital audio signal input from the data input terminal 1 is input to the input data clock generator 6.
Is input to the switch circuit 2 that performs sampling operation at the cycle of the clock signal generated in step S1, and is sampled and output to the time-varying coefficient filter circuit 15. The time-varying coefficient filter circuit 15 receives the sampled data and outputs the internal data. Update the data.

The time-varying coefficient filter circuit 15 has a sampling rate of output data from the N frequency dividing circuit 11, that is,
The reference clock signal generated by the time-varying coefficient filter reference clock generator 13 is frequency-divided by the N frequency dividing circuit 11, and data is held until a clock signal having a period of 1 / N is input.
On the other hand, the reference clock signal generated by the time-varying coefficient filter reference clock generator 13 is also output to the counter circuit 8, and the counter circuit 8 updates the counter value with the input reference clock signal. When the clock signal from the data clock generator 6 is input, it is reset, and immediately after the reset, counting is started again.

Further, the latch circuit 10 includes an N frequency dividing circuit 11
Output data sampling rate, that is, the counter circuit at the time when a clock signal having a 1 / N cycle obtained by dividing the reference clock signal generated by the time-varying coefficient filter reference clock generator 13 by the N divider circuit 11 is input. The counter value from 8 is held, and the held counter value is output as an address to the memory that stores the interpolation coefficient inside the time-varying coefficient filter circuit 15. The counter value output as an address from the counter circuit 8 to the memory in which the interpolation coefficient inside the time-varying coefficient filter circuit 15 is stored is
It corresponds to the time from the input of data to the time-varying coefficient filter circuit 15 to the first output, the interpolation coefficient adapted at the time of data output is read from the memory, and the filter operation is performed using the read interpolation coefficient. After that, the calculation result is output from the data output terminal 5 through the switch circuit 4 with the sampling frequency converted.

In this case, if the clock frequency of the clock signal output from the input data clock generator 6 and the clock frequency of the reference clock signal output from the time-varying coefficient filter reference clock generator 13 are asynchronous, the input data clock is generated. The counter circuit 8 to which the clock signal output by the device 6 and the reference clock signal output by the time-varying coefficient filter reference clock generator 13 are input cannot perform the reset operation at regular intervals. In this way, if the reset of the counter circuit 8 is indefinite, the counter value is also indefinite, and if the interpolation coefficient is determined by the counter value held by the latch circuit 10, a calculation error occurs, so that the input data clock generator 6 Based on the clock of, the PLL circuit composed of the phase loop control circuit 14 and the time-varying coefficient filter reference clock generator 13 is synchronized, and the counter circuit 8 is reset at a constant interval to obtain a correct interpolation coefficient. I am allowed to do so.

[0007]

In the sampling frequency converter according to the prior art, in order to reset the counter circuit at regular intervals and obtain the correct interpolation coefficient, the input data clock generator, which is an independent clock generator, and the time-varying clock generator are used. It is necessary to synchronize with the coefficient filter reference clock generator, and the time-varying coefficient filter reference clock generator was used as the voltage controlled oscillator of the PLL circuit in order to synchronize the two clock generators. However, the PLL circuit is highly accurate. , Highly stable VCO
Since the (voltage controlled oscillator) is required, there is a problem that the circuit becomes complicated and expensive. The present invention solves the above-mentioned problems, does not require a PLL circuit, and is highly accurate and time-varying with little signal deterioration with a relatively simple configuration regardless of whether the clock frequencies of input and output are synchronous or asynchronous. An object of the present invention is to provide a sampling frequency converter using a coefficient filter and a stereo FM broadcaster using the sampling frequency converter according to the present invention.

[0008]

To achieve the above object, a sampling frequency converter of the present invention comprises an input data clock generator for generating an input data clock signal, a switch circuit for sampling the input data, and a reference. A time-varying coefficient filter reference clock generator that generates a clock signal, and a frequency dividing circuit that divides the reference clock signal,
A counter circuit which is reset by a sampling clock signal and counts a reference clock signal and outputs a count value, and a first latch circuit which inputs a divided reference clock signal and the count value from the counter circuit and outputs an interpolation time A sampling frequency conversion device having a time-varying coefficient filter circuit having a filter coefficient determined by an input count value, and a switch circuit sampling the output of the time-varying coefficient filter circuit. Means for outputting the sampling clock signal by inputting the input data clock signal from and the reference clock signal from the time-varying coefficient filter reference clock generator, and the sampling clock from the means for outputting the sampling clock signal. Signal and said coun Means for outputting a reset value by inputting the count value from the circuit, a divided reference clock signal from the frequency dividing circuit, and the count value from the counter circuit, and outputting an interpolation time. And means.

More specifically, in the sampling frequency converter of the present invention, the time-varying coefficient filter circuit has a first k-stage shift register to which a reset value is input, and an output of the first k-stage shift register. A switch circuit connected to, an adder having an input of the interpolation time and the output of the switch circuit, and a coefficient memory having the output of the adder as an input,
A second k-stage shift register that receives sampling data and a k + 1-stage multiplication that is connected to the input and output of the second k-stage shift register and receives the coefficient output from the coefficient memory as each stage input. And an adder for adding the outputs of the k + 1 stage multipliers.

The stereo FM broadcaster of the present invention comprises a digital audio signal source, a sampling frequency conversion device of the present invention for converting the sampling frequency of a digital audio signal from the digital audio signal source, and the sampling frequency conversion device. A digital stereo modulator for stereo-modulating the digital audio signal that has undergone the sampling frequency conversion, a digital FM modulator for FM-modulating the stereo modulated signal from the digital stereo modulator, and an FM-modulated signal for the digital FM modulator. A stereo FM broadcast modulation section having a DA converter for converting into an analog and a stereo FM broadcast transmission section to which a modulated wave output signal output from the stereo FM broadcast modulation section is input. .

[0011]

The sampling frequency converter of the present invention comprises an input data clock generator for generating an input data clock signal, a switch circuit for sampling the input data,
A time-varying coefficient filter reference clock generator that generates the reference clock signal, a divider circuit that divides the reference clock signal, a counter circuit that is reset by the sampling clock signal, counts the reference clock signal, and outputs a count value. A first latch circuit that inputs a divided reference clock signal and the count value from the counter circuit and outputs an interpolation time; a time-varying coefficient filter circuit having a filter coefficient determined by the input count value; A sampling frequency conversion device having a switch circuit for sampling the output of the time-varying coefficient filter circuit, wherein the input data clock signal from the input data clock generator and the input data clock signal from the time-varying coefficient filter reference clock generator. A second latch circuit that inputs the reference clock signal Outputs the clock signal to output said sampling clock signal from the first latch circuit for outputting a sampling clock signal, a reset value in a third latch circuit for inputting said count value from said counter circuit.

Further, the stereo FM broadcasting apparatus of the present invention outputs a digital audio signal sampled from a digital audio signal source which constitutes a stereo FM broadcasting modulation section, and outputs the digital audio signal from the digital audio signal source of the present invention. The sampling frequency converter converts the sampling frequency, and the sampling frequency converter converts the sampling frequency to digitally modulate the stereo audio signal in the digital stereo modulation section, and the stereo modulation signal from the digital stereo modulation section in the digital FM modulation section. FM modulation is performed by a digital FM modulator, the FM modulation signal of the digital FM modulator is converted into an analog signal by a DA converter, and a stereo F is output as a modulated wave output signal.
It outputs to the M broadcast transmitter and sends out a stereo broadcast wave.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit block diagram of a sampling frequency converter using a time-varying coefficient filter according to the present invention, and FIG. 3 is a circuit block diagram of an improved time-varying coefficient filter used in a sampling frequency converter. FIG.
1 is a data input terminal, 6 is an input data clock generator, 7 is a latch circuit for latching the clock signal from the input data clock generator 6, and 2 is an input data clock output via the latch circuit 7. A switch circuit for sampling the input data by the clock signal from the generator 6, 12 is a time-varying coefficient filter reference clock generator, 8 is a counter circuit for counting the clock signal from the time-varying coefficient filter reference clock generator, 11
Is an N divider circuit for dividing the clock signal from the time-varying coefficient filter reference clock generator 12 by N, 9 and 10 are latch circuits for latching the counter value from the counter circuit 8,
Reference numeral 3 is a time-varying coefficient filter circuit that receives the sampling data from the switch circuit 2 and the counter values from the latch circuits 9 and 10, and 4 is a time-varying coefficient filter circuit 3 according to the clock signal from the N frequency dividing circuit 11. A switch circuit 5 for sampling the output from the device is a data output terminal.

Next, the internal structure of the improved time-varying coefficient filter 3 will be described with reference to FIG. In FIG. 3, 3
Reference numeral 1 denotes an input terminal to which a counter value (hereinafter, referred to as a reset value) immediately before resetting the counter 8 from the latch circuit 9 (see FIG. 1) is input, 32-a denotes a k-stage shift register, and 34 denotes a shift register. Is a switch circuit connected to the output side of each stage shift register of the k stage shift register 32-a, and 33 is indicated by the value of the counter at the time of data output from the latch circuit 10 (see FIG. 1). An input terminal to which the interpolation time τ is input, 35 is an adder for adding the interpolation time τ from the input terminal 33 and the output of the shift register from the switch circuit 34, and 36 is an output from the adder 35 as a coefficient. A coefficient memory for storing, 40 is a switch circuit 2
(See FIG. 1) Data input terminal, 32-b is a k-stage shift register, 37 is a k-stage shift register 32-
connected to the input / output of b and the output of the coefficient memory 36 (k
+1) multipliers, 38 is an adder connected to each output of the (k + 1) multipliers, and 39 is an interpolation data output terminal.

The operation will be described below. FIG.
2, the input data clock generator 6 and the time-varying coefficient filter reference clock generator 12 are independent clock generators, and the clock frequency of the time-varying coefficient filter reference clock generator 12 is the input data. It is assumed that it is sufficiently higher than the clock frequency of the clock generator 6. The clock signal fin output from the input data clock generator 6 is input to the latch input of the latch circuit 7, and the reference clock signal fb output from the time varying coefficient filter reference clock generator 12 is the clock input of the latch circuit 7. Is input to the counter circuit 8 and the N frequency dividing circuit 11. In the latch circuit 7, the clock signal fin is latched by the reference clock signal fb, and the latched clock signal is output to the reset input of the counter circuit 8, the clock input of the latch circuit 9, and the switch circuit 2. The counter circuit 8 is reset by the clock signal output from the latch circuit 7, its cycle is counted with the resolution of the reference clock signal fb from the time-varying coefficient filter reference clock generator 12, and the counter value is output.

Here, for example, if the cycle of the clock signal fin is approximately M times the cycle of the reference clock fb,
The reset value of the counter circuit 8 can take values from (M-2) to M. The latch circuit 9 holds this input reset value,
This reset value is transferred to the k-stage shift register 3 via the reset value input terminal 31 (see FIG. 3) of the time-varying coefficient filter 3.
Output to the first stage of 2-a. k-stage shift register 32-
In a, the input reset value is output to the next stage in each stage of the k-stage shift register 32-a, and the reset value is shifted. On the other hand, the latch circuit 10 holds the counter value from the counter circuit 8 for each clock signal obtained by dividing the reference clock fb from the time-varying coefficient filter reference clock generator 12 by N, that is, for each output data sampling clock signal fout. , And outputs this counter value to the adder 35 via the interpolation time τ input terminal 33 (see FIG. 3) of the time-varying coefficient filter 3. In the time-varying coefficient filter 3, the counter value (interpolation time τ) output from the latch circuit 10
The k-stage shift register 32-a that has been input until then
The k reset values Nrs which are the outputs of the
Is added and output to the coefficient memory 36, and the interpolation coefficient αn (τ) required for the calculation is sequentially read from the coefficient memory 36.

The operation at this time will be further described with reference to the operation explanatory view shown in FIG. In addition, in FIG.
For simplicity, the time-varying coefficient filter is set to the reference clock signal f
Replaced with a FIR (Finite Impulse Response) filter that operates at b, and the reference clock signal fb = 912 kHz
z, input data clock signal fin = 48 kHz, output data clock signal fout = 76 kHz, and the input and output clock signals are synchronized. The input data input to the data input terminal 41 is input to the FIR filter once at 48 kHz of the input data clock signal fin, and zero is interpolated otherwise.

The FIR filter uses the reference clock signal fb.
Shift register 42-b of k stages for every 912 kHz,
Data shifting and sum-of-products calculation are performed by the k + 1-stage multiplier 47 and the adder 48. By outputting the calculation result every 76 kHz of the output data clock signal fout, the output data clock is changed from 48 kHz of the input data clock signal fin. A conversion of the sampling frequency of the signal fout to 76 kHz is performed. At this time, if the input and output clock signals are synchronized, the register 42 of the FIR filter
-B has data every fb / fin = 19,
Since zeros are contained in the other registers, it is sufficient to perform the calculation only for the registers in which data exists. On the other hand, the counter value is 0 to 1.
19 values up to 8 are counted in order, and if data is output at a certain time, for example, when the counter value τ is 3, the coefficient value actually required for the calculation is a3,
a22, ..., A (3+ (m × 19)) (m:
Positive integer).

As can be understood from the above description, the coefficient necessary for performing the calculation and outputting the data is a
(Τ + (m + Nrs)) should be read from the coefficient memory 36 and the product-sum operation should be performed. Even if the input data clock signal fin and the reference clock signal fb are not synchronized, from the same idea, the coefficient a (τ + ΣNr)
Since it is only necessary to read s), if the reset value Nrs immediately before the data is input to the time-varying coefficient filter 3 is input and stored, the data exists as in the case of replacing with the FIR filter. It becomes possible to read the coefficient corresponding to the register. The input data sampled at the cycle of the clock signal of the input data clock generator 6 and input to the data input terminal 40 (see FIG. 3) of the time-varying coefficient filter 3 is input to the k-stage shift register 32-b. The data input in the past is sequentially shifted, the applicable coefficient is selected by the above-described method, the product-sum operation is performed for each cycle of the output data clock signal fout, and the operation result is output.

An application example of a stereo FM broadcasting apparatus using the sampling frequency conversion device according to the present invention will be described with reference to FIG. FIG. 5 is a block diagram of a modulation unit of a stereo FM broadcast apparatus using the sampling frequency conversion device according to the present invention. The digital audio signal source 51 is connected to the digital stereo modulator 53 via the sampling frequency converter 52 according to the present invention. Further, the digital stereo modulation unit 53 uses the digital FM
It is connected to the modulated wave output terminal 56 via the modulator 54 and the DA converter 55, and further connected to the transmitter (not shown).

The operation will be described below. As the digital audio signal source 51, for example, DAT
(Digital Audio Tape Recorder), CD (Compact Disc), etc., but the sampling frequencies of these signal sources differ depending on the type. on the other hand,
In the digital stereo modulator 53, for example, in the FM stereo broadcasting system adopted in Japan, the L (left) signal and the R (right) signal of the input audio signal are converted into the L + R signal and the L signal.
-R signal is generated, a pilot signal of 19 kHz is inserted, balanced modulation of 38 kHz is performed so that the L + R signal becomes the main signal and the L-R signal becomes the sub-signal, so the processing is n × 19 kHz. It is desirable that the sampling frequency is Therefore, the sampling frequency of the digital audio signal source 51 is converted into a sampling frequency of n × 19 kHz in the sampling frequency conversion device 52 according to the present invention, and the digital stereo modulation section 53.
That is stereo-modulated by the digital FM modulator 54 and then processed by the DA converter 55 into an analog signal, and the FM-modulated modulated wave is output from the modulated wave output terminal 56 to the transmitter. Is.

[0022]

According to the present invention, a PLL circuit is not required, and furthermore, regardless of whether the clock frequencies of the input and output are synchronous or asynchronous, a highly simple and highly accurate time-varying signal with little signal deterioration. A sampling frequency converter using a coefficient filter and a stereo FM broadcaster using the sampling frequency converter according to the present invention can be provided. Further, by using the present invention, it becomes possible to improve the accuracy and the cost of all the voice, image transmission communication devices and data transmission communication devices that require digital signal processing. As specific application examples of the present invention, in addition to the application examples described above, digitalization is currently in progress, or is being digitized in the future, such as commercial radios, wireless communication devices such as digital cellular, and wired communication devices such as modems. It is applicable to all promoted communication devices.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a sampling frequency conversion device according to the present invention.

FIG. 2 is a circuit block diagram showing a sampling frequency conversion device according to a conventional technique.

FIG. 3 is a circuit block diagram showing a configuration of a time-varying coefficient filter according to the present invention.

FIG. 4 is an operation explanatory diagram when the sampling frequency conversion device is configured by an FIR filter.

FIG. 5 is a block diagram of a modulation unit of a stereo FM broadcast using a sampling frequency conversion device showing an application example of the present invention.

[Explanation of symbols]

1, 41 ... Data input terminals, 2, 4, 34 ... Switch circuits, 3 ... Time-varying coefficient filter circuits, 5, 45 ... Data output terminals, 6 ... Input data clock generators, 7, 9, 10, ...
Latch circuit, 8 ... Counter circuit, 11 ... N frequency divider circuit, 1
2 ... Time-varying coefficient filter reference clock generator, 13 ... Time-varying coefficient filter reference clock generator, 14 ... Phase loop control circuit, 15 ... Time-varying coefficient filter circuit, 31 ... Reset value input terminal, 32-a, 32-- b, 42-b ... shift register, 33 ... interpolation time input terminal, 35, 38, 48 ...
Adder, 36 ... Coefficient memory, 37, 47 ... Multiplier, 39
... Interpolation data output terminal, 51 ... Digital audio signal source, 52 ... Sampling frequency conversion device, 53 ... Digital stereo modulation section, 54 ... Digital FM modulation section,
55 ... DA converter, 56 ... Output terminal of modulated wave.

Claims (3)

[Claims] 1. An input data clock generator for generating an input data clock signal, a switch circuit for sampling the input data, a time-varying coefficient filter reference clock generator for generating a reference clock signal, and a reference clock signal divider. A frequency dividing circuit, a counter circuit that is reset by a sampling clock signal, counts a reference clock signal, and outputs a count value, and inputs a divided reference clock signal and the count value from the counter circuit, and outputs an interpolation time. In a sampling frequency conversion device having a first latch circuit, a time-varying coefficient filter circuit having a filter coefficient determined by an input count value, and a switch circuit sampling the output of the time-varying coefficient filter circuit, The input data from the input data clock generator A second latch circuit that inputs a lock signal and the reference clock signal from the time-varying coefficient filter reference clock generator and outputs a sampling clock signal; and the sampling clock signal from a means that outputs the sampling clock signal. And a third latch circuit for inputting the count value from the counter circuit and outputting a reset value. 2. The time-varying coefficient filter circuit according to claim 1, wherein the time-varying coefficient filter circuit is connected to a first k-stage shift register that receives a reset value and an output of the first k-stage shift register. A switch circuit, an adder that receives the interpolation time and the output of the switch circuit, a coefficient memory that receives the output of the adder, and a second k-stage shift register that receives the sampling data. A k + 1 stage multiplier connected to the input / output of the second k stage shift register and having the coefficient output from the coefficient memory as an input of each stage, and an adder for adding the output of the k + 1 stage multiplier And a sampling frequency conversion device. 3. A sampling frequency conversion device according to claim 1, which converts a sampling frequency of a digital audio signal source and a digital audio signal from the digital audio signal source, and a sampling frequency conversion from the sampling frequency conversion device. A digital stereo modulation section for stereo-modulating a digital audio signal, a digital FM modulation section for FM-modulating a stereo modulation signal from the digital stereo modulation section, and a DA converter for converting the FM-modulated signal of the digital FM modulation section to analog A stereo FM broadcast modulator having
A stereo FM broadcast transmitter, comprising: a stereo FM broadcast transmitter that receives a modulated wave output signal output from the stereo FM broadcast modulator.