JPH0823031A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To semiconductor device allowing simultaneous built-in of two kinds of a transistor for input/output impressing high voltage on the same element and a transistor for the core realizing high driving capacity at low voltage and manufacture thereof. CONSTITUTION:This semiconductor device consists of an in-and output part A being defined by an element separation field oxide film 12 to be formed on a silicon substrate 11 for forming a gate electrode and a core part B being defined by this in-and output part A and the field oxide film 12 and the size between an LDD layer of the gate and a source/drain diffusion layer is largely formed in the in-and-output part A and being small formed in the core part B while parasitic resistance is made large in the in-and-output part A so as to withstand applied high-voltage and parasitic resistance is made small in the core part B so as to have high-driving capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOSFET and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, the following MOSFETs have been known as such MOSFETs. FIG. 3 is a sectional view of such a conventional MOSFET, and FIG. 4 is a sectional view of the manufacturing process of the MOSFET. Note that an Nch (N channel) type transistor will be described as an example here.

First, as shown in FIG. 4 (a), wells and element isolations are formed in the silicon substrate 1 as required, and about 1
A 50 Å gate insulating film 2 and a polycrystal silicon film of about 2500 Å are formed. After that, the gate electrode 3 is formed by usual gate photolithography and etching. Then, for the purpose of reducing the generation of hot carriers, the LDD (N ⁻ ) layer 4
To form the ³¹ P
⁺ Is ion-implanted at 30 KeV under the condition of about 4 × 10 ¹³ ions / cm ² .

Next, as shown in FIG.
An insulating film 5 of 00Å is formed. Next, as shown in FIG. 4C, the insulating film 5 is formed with a sidewall 5a having a sidewall length of about 2000 Å only on the sidewall of the gate of the transistor by etching. After that, the insulating film 7 is used as an ion implantation mask for the source / drain layer 6 with about 200
Å About generated on the active area. Using the gate electrode 3 and the sidewall 5a as a mask, the source / drain layer 6 is formed of ⁷⁵ As ⁺ at 40 KeV and 5 × 10 ¹⁵ ions.
Ion implantation is performed under the condition of about / cm ² .

After that, in order to properly diffuse the source / drain layers 6 by heat, the substrate is heat-treated at 850 ° C., and although not shown, an insulating film is formed and contact holes are formed.
Wiring such as aluminum.

[0006]

However, in the above-described MOSFET manufacturing method, the LDD (N ⁻ ) layer is formed, so that electric field relaxation in the transistor is realized and hot carrier resistance is improved. However, due to the parasitic resistance generated by the LDD (N ⁻ ) layer, the driving capability of the transistor is reduced. Therefore, in order to secure sufficient performance, it is necessary to increase the power supply to some extent, which results in a large power consumption.

In recent years, a reduction in power consumption has been demanded, and a reduction in power supply voltage of semiconductor elements has been required. Even in this case, in order to secure sufficient driving ability, the above-mentioned L
Parasitic resistance due to the DD (N ⁻ ) layer must be reduced. Further, when the power supply voltage is lowered, the electric field in the transistor is weakened, so that hot carriers are less likely to be generated. Therefore, it is necessary to improve the ion implantation conditions or shorten the sidewall length so as to increase the concentration of the LDD (N ⁻ ) layer.

The present invention improves the inconvenience of using the elements in the system, such as the improvement of the transistor structure that is required in accordance with the decrease of the power source voltage and the elements must be used properly according to the power source voltage. And a transistor for input and output that applies a high voltage on the same element,
An object of the present invention is to provide a semiconductor device capable of simultaneously forming two types of a transistor for a core which realizes a high driving capability at a low voltage and a manufacturing method thereof.

[0009]

In order to achieve the above object, the present invention provides: (A) In a semiconductor device, an input / output portion defined by an element isolation field oxide film formed on a semiconductor substrate and having a gate formed therein. A core portion defined by the input / output portion and the field oxide film to form a gate; and an LDD (Lightly Doped Dra) of the gate.
The size between the (in) layer and the source / drain diffusion layer is large in the input / output part and small in the core part, and the parasitic resistance is increased in the input / output part to withstand high voltage application.
In the core part, the parasitic resistance is reduced to provide high driving capability.

That is, in a semiconductor device, an input / output portion defined by an element isolation field oxide film formed on a semiconductor substrate and formed with a gate insulating film, and a core portion defined by the input / output portion and the field oxide film. And a gate electrode, an LDD (N ⁻ ) layer formed using the gate electrode as a mask, and first and second sidewall films formed on both sides of the gate electrode. And a source / drain layer formed using the sidewall as a mask. On the other hand, a gate electrode, an LDD (N ⁻ ) layer formed using the gate electrode as a mask, the gate electrode and a first sidewall film formed on the gate electrode are used as a mask in the core portion. The source / drain layers to be formed are provided.

Further, in the semiconductor device, an input / output portion defined by an element isolation field oxide film formed on a semiconductor substrate and formed with a gate insulating film, and a core portion defined by the input / output portion and the field oxide film. And a gate electrode in the input / output portion, and the LDD is ion-implanted with an inclination angle so that the gate electrode is further implanted toward the center of the lower portion of the gate electrode using the gate electrode as a mask.
An (N ⁻ ) layer, sidewalls formed on both sides of the gate electrode, and source / drain layers formed using the sidewalls as a mask are provided. On the other hand, the core portion is formed with a gate electrode, an LDD (N ⁻ ) layer formed using the gate electrode as a mask, sidewalls formed on both sides of the gate electrode, and the sidewall as a mask. A source / drain layer is provided.

(B) In the method of manufacturing a semiconductor device, a step of forming an element isolation field oxide film on a semiconductor substrate, then forming a gate insulating film, and forming an input / output portion and a core portion, and the input / output portion. And LDD by ion implantation
A step of forming an (N ⁻ ) layer, a step of forming a first sidewall film, a step of forming a first resist on the input / output portion, and ion implantation of a first source /
Forming a drain layer, removing the first resist to form a second sidewall film, and forming sidewalls of the first and second sidewall films on a side portion of the gate electrode. And a second resist is applied to the core part and a second resist is ion-implanted into the input / output part.
The step of forming the source / drain layer is performed.

(C) In the method of manufacturing a semiconductor device, a step of forming an element isolation field oxide film on a semiconductor substrate, then forming a gate insulating film, and forming an input / output portion and a core portion, and the input / output portion. And forming a gate electrode in the core portion, applying a first resist to the input / output portion, and forming a first LDD (N ⁻ ) layer in the core portion by ion implantation, after the resist removal, a second resist applied to the core portion, wherein the ion implantation obliquely with an inclination angle so that it can be deeply implanted under the gate electrode, a second LDD (N ^-) forming a layer And a step of forming a sidewall film after removing the second resist and forming a sidewall on the side portion of the gate electrode, and ion implantation into both the input / output portion and the core portion at the same time. More it is obtained by so applying and forming a source / drain layer.

[0014]

According to the present invention, an input / output portion defined by an element isolation field oxide film formed on a semiconductor substrate and having a gate formed, and a gate defined by the input / output portion and the field oxide film are formed. A core portion is provided, and the dimension between the LDD layer of the gate and the source / drain diffusion layer is made large in the input / output portion and small in the core portion, and the parasitic resistance is increased in the input / output portion to withstand the application of high voltage. , In the core part, the parasitic resistance is reduced to provide high driving capability.

Therefore, two types of transistors can be formed on the same element: a transistor excellent in hot carrier resistance capable of supporting a high power supply voltage and a transistor having a small parasitic resistance capable of realizing high driving capability.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a sectional view of a semiconductor device showing a first embodiment of the present invention, and FIG. 2 is a sectional view of a manufacturing process of the semiconductor device. Hereinafter, a method for manufacturing the semiconductor device of the present invention will be described.

First, as shown in FIG. 2A, a well and a field oxide film 12 for element isolation are formed on a silicon substrate 11 if necessary, and then a gate insulating film 13 and a polycrystalline silicon film are formed. Then, the gate electrode 14 is simultaneously formed in the input / output portion A and the core portion (the portion that is the center of the main operation surrounded by the input / output portion) B by the normal gate photolithography etching, and the LD is formed by ion implantation.
The D (N ⁻ ) layer 15 is formed. That is, ³¹ P ⁺ is 30
Ion implantation is performed at about 4 × 10 ¹³ ions / cm ^{2 with} KeV.

Next, as shown in FIG. 2B, LP-TE having excellent film thickness controllability as the first sidewall film.
OS (Liquid Phase-Tetra Etyl Ortho Si
lycate) The film 16 is produced by about 700Å. afterwards,
By photolithography, the resist 17 is left only in the input / output portion A, and as the first source / drain layer ion implantation, ⁷⁵ As ⁺ is applied at 110 KeV and 5 × 10 ¹⁵ ions / c.
Ions are implanted only into the core portion B at a m ² level to form the first source / drain layer 18.

Next, as shown in FIG. 2 (c), after removing the resist 17, a PSG film 19 as a first sidewall film is formed by the CVD method by about 2000 liters. Then, as shown in FIG. 2 (d), the first side wall with a length of about 2000 Å is formed by normal side wall etching.
A side wall film 16a and a side wall film including the second side wall film 19a are formed. LP-T with little thermal diffusion as an active ion implantation mask
The EOS film 20 is formed at about 200Å. By Photoriso,
The resist 21 is left only in the core portion B, and ⁷⁵ As ⁺ is added to 40 as ion implantation for the second source / drain layer.
In 5 × 10 ¹⁵ ions / cm ² about at KeV, is ion-implanted only to the input and output portions A, the second source / drain layer 2
Form 2

Here, the LP-TEOS film 20 having a small thermal diffusion is used as an ion implantation mask on the active layer to about 2 nm.
By generating 00Å, the LD that was previously ion-implanted
It is possible to suppress the unnecessary diffusion of the D (N ⁻ ) layer 15 and the first source / drain layer 18 due to oxidation to form a diffusion layer having a dimension as designed. In this way,
As shown in FIG. 1, the sidewalls 16a and 19a are
By adopting a double structure, the N ^- layer parasitic resistance portion a of the input / output portion A (which can be used for both high power supply and low power supply) is increased, while the N ^- layer parasitic resistance of the core portion B (used only for low voltage) is used. The part b can be made small.

Here, the N ⁻ layer parasitic resistance portion a of the input / output portion A is, for example, 0.75 μm, and the N ⁻ layer parasitic resistance portion b of the core portion B (used only at a low voltage) is, for example, 0. 0
It can be formed to 5 μm. As a result, the input / output portion A can simultaneously realize a transistor structure excellent in hot carrier resistance even when used with a high power supply, and the core portion B can simultaneously realize a transistor structure having high driving capability.

Next, a second embodiment of the present invention will be described.
I do. FIG. 5 shows a semiconductor device according to the second embodiment of the present invention.
FIG. 6 is a sectional view of the manufacturing process of the semiconductor device.
It The manufacturing method of the semiconductor device will be described below.
It First, as shown in FIG. 6A, the silicon substrate 31
Wells and field acids for device isolation as necessary
After forming the oxide film 32, the gate insulating film 33 and the polycrystalline silicon film are formed.
Generates a con film and can be used for normal gate photolithography and etching.
Therefore, both the input / output part A and the core part B are simultaneously gated.
After forming the electrode 34, the input / output portion A is formed by photolithography.
So that the resist 35 remains only on³¹P⁺30 Ke
4 × 10 with V ¹³ions / cm²Ion implantation at a degree,
The first LDD (N^-) Form layer 36.

Next, as shown in FIG. 6B, the resist
On the contrary, after removing 35, the resist 37 remains only in the core portion B.
Do the photolithography again,³¹P⁺6 × at 70 KeV
10 ¹³ions / cm²The tilt angle θ is about 45 °
(Note that θ may be 30 ° to 45 °)
The second LDD (N^-) Form layer 38
It

Next, as shown in FIG. 6C, after removing the resist 37, a normal sidewall film 39 is formed. Next, as shown in FIG. 6D, by etching the sidewall film 39, the sidewall length is about 100.
After forming the 0Å side wall 39a, the ion implantation mask film 40 is formed, and ⁷⁵ As ⁺ is common to both the input / output part A and the core part B at 5 × 10 ¹⁵ ions at 40 KeV.
/ Cm implanted with ² mm, the source / drain layer 41
To form.

In this way, as shown in FIG.
The extension length of the D (N ⁻ ) layer below the gate is N of the input / output portion A.
^{Since the-} layer parasitic resistance portion a'is large and the N ^- layer parasitic resistance portion b'of the core portion B is small, the same effect as that of the first embodiment can be obtained. The present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0026]

As described above in detail, according to the present invention, it is possible to form two types of transistors having different LDD (N ⁻ ) layer parasitic resistances on the same element. The input / output portion to which a voltage is applied can be made a transistor having a large parasitic resistance to improve the hot carrier resistance, and the core portion can be made a transistor having a small parasitic resistance to provide a high driving capability.

Further, this makes it possible to realize an element that can be used with two types of power supply voltages, a high power supply voltage and a low power supply voltage.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device showing a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device in the manufacturing process showing the first embodiment of the present invention.

FIG. 3 is a sectional view of a conventional MOSFET.

FIG. 4 is a sectional view of a conventional MOSFET manufacturing process.

FIG. 5 is a cross-sectional view of a semiconductor device showing a second embodiment of the present invention.

FIG. 6 is a cross-sectional view of a manufacturing process of a semiconductor device showing a second embodiment of the present invention.

[Explanation of symbols]

11, 31 Silicon substrate 12, 32 Field oxide film 13, 33 Gate insulating film A Input / output portion B Core portion 14, 34 Gate electrode 15 LDD (N ⁻ ) layer 16, 20 LP-TEOS film (first sidewall film ) 16a, 19a, 39a Side wall 17, 21, 35, 37 Resist 18 First source / drain layer 19 PSG film (second side wall film) 22 Second source / drain layer 36 First LDD (N ^-) layer 38 second LDD (N ^-) layer 39 side wall film 40 ion implantation mask layer 41 source / drain layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/336

Claims (4)

[Claims] 1. An (a) input / output portion defined by an element isolation field oxide film formed on a semiconductor substrate to form a gate, and (b) a gate defined by the input / output portion and the field oxide film. (C)
The size between the LDD layer of the gate and the source / drain diffusion layer is large in the input / output portion and small in the core portion, and the parasitic resistance is increased in the input / output portion to withstand the application of a high voltage, and the core portion is parasitic. A semiconductor device characterized in that the resistance is reduced to provide high driving capability. 2. A step of: (a) forming an element isolation field oxide film on a semiconductor substrate, then forming a gate insulating film, and forming an input / output portion and a core portion respectively; and (b) the input / output portion and the core. Forming a gate electrode in each part, (c) forming an LDD (N ⁻ ) layer by ion implantation, (d) forming a first sidewall film, and (e) the input / output Apply the first resist to the part,
Forming a first source / drain layer in the core portion by ion implantation; (f) removing the first resist to form a second sidewall film, and forming a second sidewall film on the side portion of the gate electrode. A step of forming sidewalls of the first and second sidewall films; and (g) applying a second resist to the core portion and forming second source / drain layers by ion implantation in the input / output portions. A method of manufacturing a semiconductor device, which comprises performing steps. 3. LP-TEOS having a small thermal diffusion as an ion implantation mask on the surface of the gate insulating film after forming the sidewalls of the first and second sidewall films.
The method for manufacturing a semiconductor device according to claim 2, wherein a film is formed. 4. A step of: (a) forming an element isolation field oxide film on a semiconductor substrate, then forming a gate insulating film, and forming an input / output portion and a core portion respectively; and (b) the input / output portion and the core. Forming a gate electrode on each of the portions, and (c) applying a first resist to the input / output portion and forming a first LDD (N ⁻ ) layer on the core portion by ion implantation. ) After removing the first resist, a second resist is applied to the core portion, and ions are obliquely implanted with an inclination angle so that deep implantation into the lower portion of the gate electrode is possible, and a second LDD (N ⁻ ) layer is formed. And (e) a step of forming a sidewall film after removing the second resist and forming a sidewall on a side portion of the gate electrode, and (f) the input / output portion and the core portion. And ion implantation at the same time More, the manufacturing method of a semiconductor device characterized by performing the step of forming a source / drain layer.