JPH08236932A - Manufacture of multilayered ceramic wiring board - Google Patents
Manufacture of multilayered ceramic wiring boardInfo
- Publication number
- JPH08236932A JPH08236932A JP3827595A JP3827595A JPH08236932A JP H08236932 A JPH08236932 A JP H08236932A JP 3827595 A JP3827595 A JP 3827595A JP 3827595 A JP3827595 A JP 3827595A JP H08236932 A JPH08236932 A JP H08236932A
- Authority
- JP
- Japan
- Prior art keywords
- organic insulating
- insulating layer
- wiring board
- resin
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229920005989 resin Polymers 0.000 claims abstract description 23
- 239000011347 resin Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 8
- 238000007747 plating Methods 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000005498 polishing Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、例えば電子部品として
利用されるセラミック多層配線板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a ceramic multilayer wiring board used as an electronic component, for example.
【０００２】[0002]
【従来の技術】近年、プリント配線板の高性能化が望ま
れる中、セラミック配線板についても多層化が進展して
いる。セラミック多層配線板の製造方法しては、次の２
種類の方法が知られている。 グリーンシート多層法 厚膜多層（積み上げ多層）法 従来の厚膜多層法で得られるセラミック多層配線板は、
断面図を図３に示すように、セラミック基板１上に樹脂
よりなる有機絶縁層２と金属導体よりなる回路部３を積
み上げて形成して製造する。このときの有機絶縁層２の
形成方法としては、感光性樹脂をスピンコーターで塗布
し、次いでフォトリソグラフィー法（以下フォトリソ法
という）でバイアホールを形成する方法が一般的であ
る。また、回路部３の形成方法としては、メッキ法、ス
パッタリング法等により金属導体層を形成し、次いでフ
ォトリソ法で回路部３を形成する方法等がある。しか
し、上記の方法では、有機絶縁層２を形成する必要がな
い部分にも高価な感光性樹脂を塗布することから、製造
コストが高くなるという問題点があった。また、有機絶
縁層２と回路部３を積み上げて形成するため、多層化す
るほど基板表面の有機絶縁層２に凹凸が生じ、チップ部
品の実装が困難になるという問題が生じていた。2. Description of the Related Art In recent years, as printed wiring boards have been desired to have higher performance, ceramic wiring boards are also becoming multi-layered. Regarding the method of manufacturing a ceramic multilayer wiring board, the following 2
Types of methods are known. Green sheet multi-layer method Thick film multi-layer (stacked multi-layer) method
As shown in the sectional view of FIG. 3, an organic insulating layer 2 made of a resin and a circuit portion 3 made of a metal conductor are stacked on a ceramic substrate 1 to be manufactured. As a method of forming the organic insulating layer 2 at this time, a method of applying a photosensitive resin with a spin coater and then forming a via hole by a photolithography method (hereinafter referred to as a photolithography method) is generally used. As a method of forming the circuit portion 3, there is a method of forming a metal conductor layer by a plating method, a sputtering method, or the like, and then forming the circuit portion 3 by a photolithography method. However, the above method has a problem that the manufacturing cost is increased because the expensive photosensitive resin is applied to the portion where the organic insulating layer 2 is not required to be formed. Further, since the organic insulating layer 2 and the circuit portion 3 are stacked and formed, the more the number of layers is increased, the more uneven the organic insulating layer 2 on the surface of the substrate becomes, which makes it difficult to mount the chip component.
【０００３】上記の多層化することで基板表面の有機絶
縁層に凹凸が生じるという問題を解消する手段として、
図４に示すめっき柱法が知られている。この方法は、図
４（ａ）に示すように、セラミック基板１の表面に形成
された平滑な回路部３上にフォトレジスト層４を形成
し、露光、現像してレジストホール５を形成し、次いで
図４（ｂ）に示すように、このレジストホール５内に電
気めっきによりめっき柱６を形成した後、フォトレジス
トを除去する。次いで、図４（ｃ）に示すように、めっ
き柱６を覆って有機絶縁層２を形成し、さらに、図４
（ｄ）に示すように、めっき柱６より上部の有機絶縁層
２を研磨により除去して平坦化する。得られた平坦な面
にめっき法やスパッタリング法を用いて金属導体層（図
示せず）を形成し、フォトリソ法で回路部（図示せず）
を形成する。この手順を繰り返すことで多層配線板が製
造できる。このめっき柱法では、多層化により基板表面
の有機絶縁層に凹凸が生じるという問題は解消するが、
有機絶縁層を研磨して平坦化するという工程が加わり、
工程が複雑になるという欠点があった。As a means for solving the above-mentioned problem that the organic insulating layer on the surface of the substrate has irregularities due to the multilayer structure,
The plating pillar method shown in FIG. 4 is known. In this method, as shown in FIG. 4A, a photoresist layer 4 is formed on a smooth circuit portion 3 formed on the surface of a ceramic substrate 1 and exposed and developed to form a resist hole 5, Next, as shown in FIG. 4B, after the plating pillar 6 is formed in the resist hole 5 by electroplating, the photoresist is removed. Next, as shown in FIG. 4C, the organic insulating layer 2 is formed so as to cover the plated pillars 6, and further, as shown in FIG.
As shown in (d), the organic insulating layer 2 above the plated column 6 is removed by polishing to be planarized. A metal conductor layer (not shown) is formed on the obtained flat surface by a plating method or a sputtering method, and a circuit portion (not shown) is formed by a photolithography method.
To form. A multilayer wiring board can be manufactured by repeating this procedure. This plating pillar method solves the problem of unevenness in the organic insulating layer on the substrate surface due to the multilayer structure,
A step of polishing and flattening the organic insulating layer is added,
There is a drawback that the process becomes complicated.
【０００４】[0004]
【発明が解決しようとする課題】上記の事情に鑑み、本
発明は、セラミック基板上に、樹脂よりなる有機絶縁層
と金属導体よりなる回路部を積み上げて形成するセラミ
ック多層配線板の製造方法であって、有機絶縁層を形成
する必要のある部分に、選択的に有機絶縁層形成のため
の樹脂を配設できる方法を開発することを第１の課題と
し、また、第一の課題に加えて、多層化しても基板表面
の有機絶縁層に凹凸が生じにくい方法を開発することを
第２の課題としている。In view of the above circumstances, the present invention provides a method for manufacturing a ceramic multilayer wiring board, which comprises stacking an organic insulating layer made of resin and a circuit section made of metal conductor on a ceramic substrate. Therefore, the first problem is to develop a method capable of selectively disposing a resin for forming the organic insulating layer in a portion where the organic insulating layer needs to be formed, and in addition to the first problem, A second problem is to develop a method in which unevenness is less likely to occur in the organic insulating layer on the substrate surface even when the number of layers is increased.
【０００５】[0005]
【課題を解決するための手段】請求項１に係る発明のセ
ラミック多層配線板の製造方法は、セラミック基板上
に、樹脂よりなる有機絶縁層と金属導体よりなる回路部
を積み上げて形成するセラミック多層配線板の製造方法
において、有機絶縁層を形成する部分の周囲に枠を形成
し、この枠内に樹脂を配設して有機絶縁層を形成するこ
とを特徴としている。According to a first aspect of the present invention, there is provided a ceramic multilayer wiring board manufacturing method, wherein a ceramic multi-layer wiring board is formed by stacking an organic insulating layer made of a resin and a circuit portion made of a metal conductor on a ceramic substrate. A method of manufacturing a wiring board is characterized in that a frame is formed around a portion where an organic insulating layer is formed, and a resin is disposed in the frame to form the organic insulating layer.
【０００６】請求項２に係る発明のセラミック多層配線
板の製造方法は、請求項１記載のセラミック多層配線板
の製造方法において、上記枠の高さを均一な高さとし、
この枠の高さまで樹脂を充填して有機絶縁層を形成する
ことを特徴としている。According to a second aspect of the present invention, there is provided a method of manufacturing a ceramic multilayer wiring board according to the first aspect, wherein the frame has a uniform height.
It is characterized in that the organic insulating layer is formed by filling the resin up to the height of the frame.
【０００７】[0007]
【作用】請求項１に係る発明において、有機絶縁層を形
成する部分の周囲に枠を形成し、この枠内に樹脂を配設
して有機絶縁層を形成することは、有機絶縁層を形成す
る必要のある部分に、選択的に有機絶縁層形成のための
樹脂を配設することができるように作用する。In the invention according to claim 1, a frame is formed around a portion where the organic insulating layer is formed, and the resin is disposed in the frame to form the organic insulating layer. It acts so that the resin for forming the organic insulating layer can be selectively disposed on the portion that needs to be formed.
【０００８】請求項２に係る発明において、枠の高さを
均一な高さとし、この枠の高さまで樹脂を充填して有機
絶縁層を形成することは、有機絶縁層と回路部を積み上
げて形成して多層化しても、基板表面の有機絶縁層に凹
凸が生じないように作用する。In the invention according to claim 2, the height of the frame is made uniform and the resin is filled up to the height of the frame to form the organic insulating layer, which is formed by stacking the organic insulating layer and the circuit portion. Even if it is made into a multi-layered structure, the organic insulating layer on the surface of the substrate does not have irregularities.
【０００９】[0009]
【実施例】以下、本発明の実施例を図面を参照して説明
する。Embodiments of the present invention will be described below with reference to the drawings.
【００１０】図１の断面図に示すように、セラミック基
板１の表面上に平滑な第１層目の回路部３ａを形成す
る。この平滑な回路部３ａは、めっき法やスパッタリン
グ法を用いて金属導体層を形成し、次いでフォトリソ法
で回路形成して作製できる。次いで、第１段目の有機絶
縁層２ａの形成を予定する部分の周囲に第１段目の枠７
ａを形成する。この枠７ａの形成は、例えば、熱硬化性
エポキシ樹脂をスクリーン印刷法で印刷、乾燥して形成
する方法や、予め樹脂製の枠を成型等により作製してお
き、それを接着剤を用いて固定する方法等によって行う
ことができる。次いで、枠７ａの内側にディスペンサー
を用いて感光性ポリイミドよりなる樹脂を流し込む。本
実施例では、枠７ａの高さを均一な高さとし、流し込ま
れた樹脂を枠７ａの高さまでブレードを用いて充填し、
第１段目の有機絶縁層２ａを形成する。このようにして
得られる第１段目の有機絶縁層２ａの表面は平坦な面と
なる。次いで、この有機絶縁層２ａを露光、現像するこ
とにより、ビアホールとするためのホール８を形成す
る。次いで、ホール８が形成された有機絶縁層２ａの上
に第２層目の回路部３ｂを形成する。この第２層目の回
路部３ｂの形成は、第１層目の回路部３ａの場合と同様
に、めっき法やスパッタリング法を用いて金属導体層を
形成し、次いでフォトリソ法で回路形成して作製でき
る。次いで、第１段目の枠７ａの上に、第２段目の枠７
ｂを形成する。以降は上記と同様の手順で第２段目の有
機絶縁層２ｂ及び第３層目の回路部３ｃを形成して３層
の回路層を備えるセラミック多層配線板を製造すること
ができる。As shown in the sectional view of FIG. 1, a smooth first layer circuit portion 3a is formed on the surface of the ceramic substrate 1. The smooth circuit portion 3a can be manufactured by forming a metal conductor layer using a plating method or a sputtering method and then forming a circuit by a photolithography method. Next, the first-stage frame 7 is formed around the portion where the first-stage organic insulating layer 2a is to be formed.
a is formed. The frame 7a can be formed by, for example, printing a thermosetting epoxy resin by screen printing and drying it, or by forming a resin frame in advance by molding or the like and using an adhesive. It can be performed by a fixing method or the like. Next, a resin made of photosensitive polyimide is poured into the inside of the frame 7a using a dispenser. In the present embodiment, the height of the frame 7a is made uniform, and the poured resin is filled up to the height of the frame 7a using a blade,
The first-stage organic insulating layer 2a is formed. The surface of the first-stage organic insulating layer 2a thus obtained is a flat surface. Next, the organic insulating layer 2a is exposed and developed to form a hole 8 to be a via hole. Then, the second-layer circuit portion 3b is formed on the organic insulating layer 2a in which the holes 8 are formed. The formation of the circuit portion 3b of the second layer is performed by forming a metal conductor layer by using a plating method or a sputtering method and then forming a circuit by a photolithography method as in the case of the circuit portion 3a of the first layer. Can be made. Then, on the first-stage frame 7a, the second-stage frame 7a
b is formed. After that, the organic insulating layer 2b of the second stage and the circuit portion 3c of the third layer are formed in the same procedure as described above to manufacture a ceramic multilayer wiring board including three circuit layers.
【００１１】本発明の対象とするセラミック多層配線板
の一例としては、１枚のセラミック基板を用いて複数の
セラミック多層配線板を一括して作製した後、分割して
個々のセラミック多層配線板を製造する分割可能なセラ
ミック多層配線板がある。この分割可能なセラミック多
層配線板は、図２に平面図を示すセラミック基板１のよ
うに基板分割用ブレークライン９を備えていて、多層配
線板に加工をした後、ブレークライン９により分割でき
るようになっている。このような分割可能なセラミック
多層配線板の場合には、一般に分割後の基板の周辺部に
は有機絶縁層を形成しておく必要がないので、必要な部
分のみに選択的に有機絶縁層を形成できる本発明の方法
は非常に有効である。As an example of the ceramic multilayer wiring board to which the present invention is applied, a plurality of ceramic multilayer wiring boards are collectively manufactured using one ceramic substrate and then divided into individual ceramic multilayer wiring boards. There are divisible ceramic multilayer wiring boards that are manufactured. This dividable ceramic multilayer wiring board is provided with a substrate dividing break line 9 like the ceramic substrate 1 whose plan view is shown in FIG. 2 so that it can be divided by the break line 9 after processing the multilayer wiring board. It has become. In the case of such a divisible ceramic multilayer wiring board, generally, it is not necessary to form an organic insulating layer on the peripheral portion of the substrate after the division, so that the organic insulating layer is selectively formed only in a necessary portion. The method of the present invention that can be formed is very effective.
【００１２】[0012]
【発明の効果】請求項１に係る発明のセラミック多層配
線板の製造方法によれば、有機絶縁層を形成する必要の
ある部分に、選択的に有機絶縁層形成のための樹脂を配
設することができるので、有機絶縁層形成に使用する樹
脂のロスがなくなり、従って、製造コストの削減が可能
となる。According to the method of manufacturing a ceramic multilayer wiring board of the first aspect of the present invention, the resin for forming the organic insulating layer is selectively disposed in the portion where the organic insulating layer needs to be formed. Therefore, the loss of the resin used for forming the organic insulating layer is eliminated, so that the manufacturing cost can be reduced.
【００１３】請求項２に係る発明のセラミック多層配線
板の製造方法によれば、有機絶縁層と回路部を積み上げ
て形成して多層化しても、有機絶縁層の平坦性が確保さ
れるので、チップ部品の実装が容易になる。According to the method for manufacturing a ceramic multilayer wiring board of the second aspect of the present invention, the flatness of the organic insulating layer is ensured even when the organic insulating layer and the circuit portion are stacked to form a multilayer structure. Mounting of chip parts becomes easy.
【図１】本発明の製造方法を説明する断面図である。FIG. 1 is a cross-sectional view illustrating a manufacturing method of the present invention.
【図２】基板分割用ブレークラインを備えるセラミック
基板の平面図である。FIG. 2 is a plan view of a ceramic substrate having a break line for substrate division.
【図３】従来の厚膜多層法で得られるセラミック多層配
線板の断面図である。FIG. 3 is a sectional view of a ceramic multilayer wiring board obtained by a conventional thick film multilayer method.
【図４】従来の製造方法であるめっき柱法を説明する断
面図である。FIG. 4 is a cross-sectional view illustrating a plated column method that is a conventional manufacturing method.
１ セラミック基板 ２，２ａ，２ｂ 有機絶縁層 ３，３ａ，３ｂ，３ｃ 回路部 ４ フォトレジスト層 ５ レジストホール ６ めっき柱 ７，７ａ，７ｂ 枠 ８ ホール ９ ブレークライン 1 Ceramic Substrate 2, 2a, 2b Organic Insulation Layer 3, 3a, 3b, 3c Circuit Section 4 Photoresist Layer 5 Resist Hole 6 Plating Pillar 7, 7a, 7b Frame 8 Hole 9 Breakline
Claims (2)
絶縁層と金属導体よりなる回路部を積み上げて形成する
セラミック多層配線板の製造方法において、有機絶縁層
を形成する部分の周囲に枠を形成し、この枠内に樹脂を
配設して有機絶縁層を形成することを特徴とするセラミ
ック多層配線板の製造方法。1. In a method for manufacturing a ceramic multilayer wiring board, which comprises stacking an organic insulating layer made of a resin and a circuit section made of a metal conductor on a ceramic substrate to form a frame around a portion where the organic insulating layer is formed. Then, a method for manufacturing a ceramic multilayer wiring board is characterized in that a resin is disposed in this frame to form an organic insulating layer.
の高さまで樹脂を充填して有機絶縁層を形成することを
特徴とする請求項１記載のセラミック多層配線板の製造
方法。2. The method for producing a ceramic multilayer wiring board according to claim 1, wherein the height of the frame is made uniform and a resin is filled up to the height of the frame to form an organic insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3827595A JPH08236932A (en) | 1995-02-27 | 1995-02-27 | Manufacture of multilayered ceramic wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3827595A JPH08236932A (en) | 1995-02-27 | 1995-02-27 | Manufacture of multilayered ceramic wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08236932A true JPH08236932A (en) | 1996-09-13 |
Family
ID=12520767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3827595A Withdrawn JPH08236932A (en) | 1995-02-27 | 1995-02-27 | Manufacture of multilayered ceramic wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08236932A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2025118657A (en) * | 2020-08-11 | 2025-08-13 | アプライド マテリアルズ インコーポレイテッド | Method for forming reduced diameter microvias |
-
1995
- 1995-02-27 JP JP3827595A patent/JPH08236932A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2025118657A (en) * | 2020-08-11 | 2025-08-13 | アプライド マテリアルズ インコーポレイテッド | Method for forming reduced diameter microvias |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20020507 |