JPH08237754A - Receiving and transmitting method in remote monitoring device and its circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to reduce the circuit scale and power consumption of a receiving and transmitting method and a circuit thereof in a remote monitoring device. A parallel reception monitoring data rd of high speed bit rate is converted into serial reception monitoring data rd ′ of low speed bit rate by a speed / serial conversion unit 12 and processed. On the other hand, the serial transmission monitor data sd ′ processed at the low bit rate is converted to the high bit rate transmission monitor data sd by the parallel conversion unit 26 and the monitor information insertion unit 27. As the processing clock at this time, the clock CL2 having a low bit rate is controlled by the clock control unit 13 and the like, and is supplied as the clock CL2 'only when necessary. Further, the transparency processing units 14 and 25 are configured such that a plurality of data bit strings sequentially shifted by 1 bit are prepared in parallel and one of them is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving and transmitting method in a remote monitoring device and a circuit therefor, such as a receiving and transmitting method in a remote monitoring device for remotely monitoring a digital transmission device in an SDH (Synchronous Digital Hierarchy) transmission system. And its circuit.

In an SDH transmission system, for example, SO
H (Section Overhead), POH (P
The overhead such as ath Overhead) is added to the original digital information data and transmitted. In this case, the overhead is a data portion for transmitting the monitoring information and is used for the above-mentioned remote monitoring and the like. For example, various types of data such as transmission quality monitoring data, transmission line monitoring data, digital transmission device failure notification data, etc. It includes the monitoring data of.

As the overhead, for example, the above-mentioned SOH
As an example, this SOH has a data structure mapped in a matrix of 9 rows × 9 columns, and the above-mentioned monitoring information is mapped in a monitoring data area called D4, D5 ... D12 in this matrix. Be accommodated. D4
Each of D5 ... D12 has a 1-byte = 8-bit configuration (8 × 9 = 72-bit configuration as a whole).

Since the monitoring data area of this overhead is a data area for transmitting the monitoring information as described above, if the data itself has an error, it cannot fulfill the role of monitoring. For this reason, error monitoring processing including "transparency processing" is also performed on both the reception system and the transmission system in the remote monitoring device.

[0005]

2. Description of the Related Art FIG. 18 is a diagram showing an example of a transmission system to which the present invention is applied. In the figure, reference numeral 1 indicates a remote monitoring device to which the present invention is applied. The remote monitoring device 1 is provided in the interface board 2 and is further connected to a network terminating device (for example, NT1) 4.

The information handled by the remote monitoring device 1 is an overhead (for example, SOH), and a well-known data structure example thereof is shown in the lower part of this figure. Handles monitoring information mapped to. This monitoring information consists of one received from the network terminating device 4 and one transmitted to the network terminating device 4, and the monitoring control unit 3 is responsible for analyzing the received monitoring information and inputting data to be added to the monitoring information to be transmitted. Do it.

By the way, the reception monitoring data received by the remote monitoring device 1 via the interface board 2 and the transmission monitoring data transmitted from the remote monitoring device 1 are 8-bit parallel data, such as D4 → D5 → D6 →. Are sequentially received and transmitted in 8-bit units. Moreover, these 8-bit parallel data are received and transmitted at a high bit rate of, for example, 19.44 MHz.

[0008]

The remote monitoring device 1 that receives and transmits parallel data (monitoring data) in 8-bit units at a high bit rate has a problem that its circuit scale becomes large. Moreover, there is a problem that power consumption becomes large because large-scale hardware is driven at a high bit rate.

In view of the above problems, it is an object of the present invention to realize a remote monitoring device that can be configured with a small-scale circuit and can reduce power consumption.

[0010]

FIG. 1 is a diagram showing a basic configuration of a remote monitoring apparatus according to the present invention (No. 1), and FIG. 2 is a diagram showing a basic configuration of a remote monitoring apparatus according to the present invention (No. 2). Is. In these figures, reference numeral 1 represents the whole remote monitoring device, and comprises a receiving circuit 10 and a transmitting circuit 20.

The parallel received data RD having a high bit rate input to the receiving circuit 10 is sent to the monitoring information extraction unit 11
By the parallel reception monitoring data rd in the RD
Only the data is extracted, and in the speed / serial conversion unit 12,
It is converted into serial reception monitoring data rd 'at a low bit rate. This reception monitoring data rd ′ is input to the clock control unit 13 on the one hand and to the transparency processing unit 14 on the other hand. The clock control unit 13
A processing clock CL2 'having a low bit rate, which is supplied only when necessary, is generated. The transparency processing unit 14 detects the five consecutive logical "1" bits described above and deletes the logical "0" added immediately after that.

The error detecting section 15 detects a data error by a frame check sequence (FCS), for example. Based on the determination result of the error detection unit 15, the data determination unit 16 determines whether the currently received data is valid or invalid. This determination and the error detection result obtained by the transparency processing unit 14 are input to the data notification unit 17. The data notification unit 17 notifies the monitoring information collection processing unit 18 whether the data currently received is normal or abnormal.

On the other hand, looking at the transmission circuit 20, the monitoring information from the monitoring information collection processing unit 18, for example, which address of the remotely monitored object is to be viewed, or how much is a judgment criterion (threshold value) in various monitoring. Information such as whether or not to set is input to the data generation unit 23 as serial data d ′, converted into a predetermined format here, and output.

The serial data d'output from the data generation unit 23 is input to the error detection code addition unit 24, where the error detection code, for example, the remainder when the data d'is divided by a predetermined generator polynomial. It is added to the data d '. Further, when the transparency processing unit 25 detects 5 consecutive logical "1" bits in the bit string (d ') to which the error detection code is added, it inserts a logical "0" into the bit immediately after that, Send out a bit string.

Thus, serial transmission monitoring data sd '
Is input to the parallel conversion unit 26 and becomes the parallel transmission monitoring data sd. Further, the monitoring information insertion unit 27 maps the sd in the parallel transmission data SD of the high speed bit rate (CL1) and transmits it to the remote monitoring target. The transmission data SD has a high bit rate (CL1), whereas the serial transmission monitoring data d'and sd 'has a low bit rate (CL2). The speed conversion unit 21 generates the clock of the low bit rate.

Further, the clock control unit 22 is provided with a processing clock CL of a low bit rate which is supplied only when necessary.
2'is generated. The above is the basic configuration of the remote monitoring apparatus according to the present invention. However, since the conventional circuit elements or method elements are also included, the present method elements and circuit elements particularly characteristic of the present invention will be clarified below.

(1) In the first aspect of the present invention, the following receiving method is provided. i) The parallel reception monitoring data rd consisting of a plurality of bits in the parallel reception data RD input at the high speed bit rate (CL1) is transferred to each of the bits before the next reception monitoring data rd arrives. Ii) the reception monitoring data r for each of the latched bits
d is converted into serial reception monitoring data at a low speed bit rate (CL2) lower than the high speed bit rate (CL1), and processing is performed using the serial reception monitoring data rd '.

(2) The second aspect of the present invention provides the following transmission method. i) processing of the monitoring information is performed by serial data d'having a bit rate lower than the high-speed bit rate of the parallel transmission data SD, ii) parallel conversion of the serial transmission monitoring data sd 'after the processing, Further, the bit rate is converted to parallel transmission data SD.

(3) In the above aspect (1), when the serial reception monitoring data rd has a predetermined fixed continuous bit length and is periodically generated, it is supplied to perform the above processing. The low speed bit rate processing clock CL2 is selectively enabled only during the period corresponding to each fixed continuous bit length, and the processing clock C2 is activated during the other periods.
Stop the supply of L2.

(4) Similarly, in the above aspect (2), the high bit rate (C
When the serial data d'having a low bit rate (CL2) lower than L1) is generated with a predetermined fixed continuous bit length and periodically, it is supplied for performing the above-mentioned processing. Low bit rate processing clock C
L2 is selectively validated only during the period corresponding to each fixed continuous bit length, and during the other periods, the processing clock C
Stop the supply of L2.

(5) The receiving circuit 10 provided in the fifth aspect of the present invention comprises a parallel reception monitor inserted as monitoring information for remote monitoring in parallel reception data RD having a high bit rate (CL1). After processing the data rd,
In the remote monitoring device 1 that is input to the monitoring information collection processing unit 18, as one of the processes, a logic "1" is inserted into a bit immediately after a predetermined number of consecutive bits of a logic "1" from a bit string that forms the reception monitoring data. Each time a "0" is detected, a transparent process for deleting the logical "0" is included, and the process including the transparent process is performed at a low bit rate (CL
2) The receiving circuit is configured to perform the reception monitoring data rd ′ converted into serial data.

The transparency processing unit 14 for performing the transparency processing receives i) serially converted reception monitoring data rd 'and sequentially shifts bit by bit a plurality of serial reception monitoring data strings. Shift register section 31 for outputting in parallel, and ii) inputting one of a plurality of serial reception monitoring data strings as a target of the above processing,
A detection unit for detecting a logic "0" inserted in a bit immediately after a predetermined number of consecutive bits of a logic "1" appearing therein, and iii) each time the detection is performed by the detection unit, A selection signal generator that generates a selection signal for selecting a serial reception monitoring data string that is shifted by one bit later than the serial reception monitoring data string, and iv) receives a plurality of serial reception monitoring data strings in parallel, It comprises a selector section for switching to one serial reception monitoring data string designated by the selection signal output from the above selection signal generating section and outputting it as a target of the above processing.

(6) The transmission circuit 20 provided in the sixth aspect of the present invention includes the monitoring information collection processing unit 18, and processes the monitoring information for remote monitoring sent from the monitoring information collection processing unit 18. In the remote monitoring device (1) which inserts the parallel transmission monitoring data sd forming the monitoring information into the parallel transmission data SD of the high speed bit rate (CL1) and outputs the data, as one of the processes, A transparency process for inserting a logical "0" into a bit immediately after the predetermined number of consecutive bits of the logical "1" from the bit string forming the transmission monitoring data, and The above-mentioned processing including the transparency processing is converted into the transmission monitoring data s converted into the serial at the low bit rate (CL2).
This is a transmission circuit designed to be performed by d '.

The transparency processing unit 24 for performing the transparency processing receives i) serially converted transmission monitoring data sd 'and serially shifts bit by bit a plurality of serial transmission monitoring data strings. And ii) one of a plurality of serial transmission monitoring data strings is input as a target of the above processing, and a predetermined number of consecutive bits of logic "1" appearing therein are input. Detecting unit for detecting, and iii) Generates a selection signal for selecting the serial transmission monitoring data sequence shifted by 1 bit from the serial transmission monitoring data sequence every time the detection is performed by the detection unit. Selection signal generating section for performing iv) logically “0” data and a plurality of serial transmission monitoring data strings are received in parallel, and the above-mentioned detection is performed by the detecting section, and at the same time, the data of logical “0” is received. A data selection unit that selects and outputs the data, and then switches to one serial reception monitoring data string designated by the selection signal output by the selection signal generation unit and outputs the serial reception monitoring data string as the target of the above processing. .

(7) The receiving circuit 10 provided in the seventh aspect of the present invention uses the parallel reception monitoring data inserted as the monitoring information for remote monitoring in the parallel reception data of the high speed bit rate (CL1). In the remote monitoring device 1 that processes the rd and then inputs it to the monitoring information collection processing unit 18, the above-mentioned processing is performed by the reception monitoring data rd ′ converted into the serial at the low bit rate (CL2). Is.

In the receiving circuit 10, i) a latch circuit for latching parallel reception monitoring data rd consisting of a plurality of bits for each bit, and ii) a parallel circuit consisting of a plurality of bits latched by the latch circuit. A parallel / serial conversion circuit for converting the reception monitoring data into serial reception monitoring data. (8) The transmission circuit 20 provided in the eighth aspect of the present invention includes the monitoring information collection processing unit 18, processes the monitoring information for remote monitoring sent from the monitoring information collection processing unit 18, and performs the monitoring. In the remote monitoring device 1 which inserts parallel transmission monitoring data forming information into parallel transmission data of high speed bit rate (CL1) and outputs the same, the above processing is transmitted to serial transmission of low speed bit rate. This is a transmission circuit that is configured to perform monitoring data.

In the transmission circuit 20, i) a serial / parallel conversion circuit for converting the serial transmission monitor data sd 'into a plurality of bits of parallel data (sd), i
i) A multiplexer for inserting the parallel data from the serial / parallel conversion circuit into the parallel reception data SD as the transmission monitoring data sd. (9) The reception circuit 10 provided in the ninth aspect of the present invention processes the parallel reception monitoring data inserted as the monitoring information for remote monitoring into the parallel reception data of the high bit rate, and then performs the monitoring. In the remote monitoring device 1 input to the information collection processing unit 18, the above-mentioned processing is performed by the reception monitoring data converted into the low-speed bit rate serial, and the low-speed bit rate processing is performed to perform the above-mentioned processing. The clock CL2 is selectively enabled only during a period corresponding to a fixed continuous bit length forming the serial reception monitoring data, and the processing clock C is provided during other periods.
It is a receiving circuit configured to stop the supply of L2.

Here, in the receiving circuit 10, i) an enable pulse generator for continuously generating an enable pulse only during a period corresponding to the above period after the start timing signal of the reception monitoring data is given, and ii) this And an AND gate that outputs the processing clock CL2 into the receiving circuit while the enable pulse is generated. (10) Transmitting circuit 20 provided in the tenth aspect of the present invention
Includes a monitoring information collection processing unit 18, processes monitoring information for remote monitoring transmitted from the monitoring information collection processing unit 18, and transmits parallel transmission monitoring data forming the monitoring information to a parallel at a high bit rate. In the remote monitoring device 1 which inserts and outputs in the transmission data of the above, the above processing is performed by the transmission monitoring data converted into the serial of the low bit rate, and the low bit rate processing is performed to perform the above processing. The clock CL2 is selectively enabled only during a period corresponding to a fixed continuous bit length forming the serial transmission monitoring data sd ', and the supply of the processing clock CL2 is stopped during other periods. is there.

Here, in the transmission circuit 20, i) an enable pulse generator for continuously generating an enable pulse only during the period corresponding to the above period after the transmission start timing signal of the transmission monitor data is given, and ii). And an AND gate for outputting the processing clock CL2 to the transmission circuit while the enable pulse is being generated.

[0030]

Actions The actions in the first aspect (1) to the tenth aspect (10) are as follows. (1) If the high-speed bit rate (CL1) reception monitoring data rd input in 8-bit parallel is converted into the low-speed bit rate (CL2) serial reception monitoring data rd ′, the circuit scale is simply 1 /. It can be reduced to 8. Also, if a clock with a low bit rate is used, power consumption is also reduced.

For example, when parallel data (reception monitoring data) having a high bit rate of 19.44 MHz is converted into serial data, the serial data generally has a higher bit rate of an integral multiple of 19.44 MHz. I don't get. However, in the present invention, attention is paid to the fact that the parallel data of the high-speed bit rate appears periodically at the timing of the frame pulse, and before the next reception monitoring data arrives, the parallel data is time-divided for each bit. The data is stretched on the axis, and then each bit is sequentially sampled at a low bit rate and converted into serial data having a low bit rate.

FIG. 3 is a diagram showing the principle of data conversion in the present invention. In this figure, the parallel reception monitoring data rd corresponds to the monitoring data areas D4, D5 ... D12 in the overhead of FIG. Each data area has 1 byte = 8 bits (D4-1, D4-2 ... D4-8, D5
-1, D5-2 ...) and is input by the high-speed clock CL1 of 19.44 MHz. Also, these monitoring data are
It appears periodically in synchronization with the frame pulse FP. For example, the frame pulse FP appears at 8 kHz, that is, 125 μs.

When the data of each bit extended to 125 μs is sampled at the low speed bit rate clock CL2, for example, 1.215 MHz, the low speed bit rate serial reception monitoring data rd ′ can be obtained. The above concept applies not only to the receiving circuit (10) system but also to the transmitting circuit (20) system. That is, the required processing is completed with the serial transmission monitoring data sd ′ having the low bit rate (CL2), and finally the parallel transmission monitoring data sd having the high bit rate (CL1) is converted.

(2) As described above with reference to FIG. 3, since the required processing of the transmission monitoring data is performed with the serial data having the low bit rate, the circuit scale is the same as that described in the above operation (1). Miniaturization and low power consumption can be achieved. (3) The above low power consumption can be made more remarkable. This is because the receiving circuit 10 is fixed in the period during which the receiving circuit 10 is actually receiving the nine monitoring data D4 to D12. That is, it is 72 (= 8 bits × 9) bits. Moreover, this 72-bit data group appears periodically (8 kHz).
Therefore, only during this 72-bit period, the processing clock C
L2 is supplied to the circuit as CL2 '. This allows
Significant reduction in power consumption can be expected.

(4) The effect of (3) is obtained by the transmitting circuit 20.
The same applies to the side. (5) The transparency processing unit in the receiving circuit 10 can be realized relatively simply and with a small number of circuit elements. (6) The effect of (5) above also applies to the transmission circuit 20 side. (7) The receiving method of (1) above can be realized by a small-scale and inexpensive circuit.

(8) The transmission method of the above (2) can be realized by a small-scale and inexpensive circuit. (9) In the receiving circuit 10, the enable pulse generator and A
Significant reduction in power consumption can be expected only by introducing the ND gate. (10) The effect of (9) above also applies to the transmission circuit 20 side.

[0037]

FIG. 4 is a diagram showing a specific example of the receiving side transparency processing section. The transparency processing unit 14 receives the reception monitoring data r converted into serial at a low bit rate (CL2).
Transparency processing for deleting a logical "0" each time a logical "0" inserted in a bit immediately after 5 consecutive bits, for example, a predetermined number of logical "1" s is detected from the bit string forming d '. I do.

Here, the error detection by the transparency processing will be described. The purpose of this processing is to guarantee that the data to be subjected to the transparency processing is not simulated by the flag (01111110) or the abort sequence (data in which “1” is consecutive 7 times or more). Although the data is composed of integer multiples of bytes, the data may not be composed of integer multiples of bytes due to the transparency processing on the sending side, but the data may not be composed by the transparency processing on the receiving side. It will be an integral multiple of the bytes of. If this data is erroneous during transmission, the data will no longer consist of an integral number of bytes when the transparency process is performed on the receiving side, and this data will be invalid. An example is shown below.

Transmission side data 1111101010101010 (Before transparency processing) Transmission data 11111001010101010 (After transparency processing) ↓ (Data is wrong during transmission) Received data 11110001010101010 (Before transparency processing) Reception side data 11110001010101010 (After transparency processing) In the specific example according to the present invention, the transparency processing unit 14 includes a shift register unit 31 and a detection unit 32 as shown in the figure.
And a selector signal generator 33 and a selector 34.

FIG. 5 is a time chart showing the operation of the circuit shown in FIG. .. in FIG. 5 correspond to the signals respectively appearing in FIG. A description will be given with reference to FIGS. 4 and 5. The shift register unit 31 receives the serially converted reception monitoring data rd ′, and outputs a plurality of serial reception monitoring data strings sequentially bit-shifted bit by bit in parallel. This corresponds to the signals and in both figures. However, for simplification, only two serial reception monitoring data strings are shown.

The detection section 32 inputs one of a plurality of serial reception monitoring data strings, for example, as a processing target, and inserts it into the bit immediately after the 5 consecutive bits of logic "1" appearing therein. Detected logic "0". Indicates the detection pulse, and is generated at the timing of the fifth logic "1" in the data string. The selection signal generation unit 33 selects every time the detection unit 32 performs the detection (), to select the serial reception monitoring data string () that is shifted by one bit later than the serial reception monitoring data string. The signal SLr is generated. In FIG. 5, and represent the signal SLr, where is a signal for selecting the above data string, and is a signal for selecting the above data string.

The selector section 34 receives a plurality of serial reception monitoring data strings in parallel, and the selection signal generating section 33.
1 specified by the selection signal SLr output by
It is switched to one serial reception monitoring data string and is output as a target of the above processing. According to FIG. 5, by switching from the data string to the data string, as a result, the original data in which the logical "0" immediately after 5 consecutive "1" bits are deleted is reproduced, and with this, the error processing and the like in the subsequent stage are performed.

FIG. 6 is a diagram showing a specific example of the transmitting side transparency processing section. The transparency processing unit 24 uses the transmission monitoring data s converted into the low bit rate (CL2) serial.
A predetermined number of logical "1" s, for example, 5 from the bit string forming d '
Every time a continuous bit is detected, a transparency process for inserting a logical "0" into the bit immediately after the 5 continuous bits is performed.

In the embodiment according to the present invention, the transparency processing section 24 includes a shift register section 41 and
Detection unit 42, selection signal generation unit 43, and data selection unit 4
4 and. FIG. 7 is a time chart showing the operation of the circuit shown in FIG. In addition, in FIG.
6 correspond to the signals respectively appearing in FIG. 6 and 7
Will be described with reference to. The shift register unit 41 receives the serially converted transmission monitor data sd ', and outputs a plurality of serial transmission monitor data strings sequentially bit-shifted bit by bit in parallel. This corresponds to the signals and in both figures. However, for simplification, only two serial transmission monitoring data strings are shown.

The detection section 42 inputs one of a plurality of serial transmission monitoring data strings as a processing target, and detects 5 consecutive bits of logic "1" appearing therein. Indicates the detection pulse, and is generated at the timing of the fifth logic "1" in the data string. The selection signal generation unit 43 is for selecting the serial transmission monitoring data string (in FIG. 7) shifted by 1 bit from the serial transmission monitoring data string each time the detection unit 42 performs the detection. The selection signal SLs is generated. In FIG. 7, and indicate the signal SLs, is a signal for selecting the above data string, and is a signal for selecting the above data string.

The data selecting section 44 receives the data of logical "0" and a plurality of serial transmission monitoring data strings in parallel, and the detecting section 42 performs the above-mentioned detection, and at the same time selects the data of logical "0". Then, the serial signal is switched to one serial reception monitoring data string designated by the selection signal SLs output from the selection signal generation unit 43, and is output as a target of the above processing. According to FIG. 7, a bit string in which a logical "0" is inserted into the bit immediately after the 5 consecutive "1" bits in the data string is generated.

In the present invention, in order to significantly reduce the power consumption of the remote monitoring device 1, the clock control unit 13 is introduced in the receiving circuit 10 so that the serial reception monitoring data rd has a predetermined fixed continuous bit. Long and
When generated periodically, the low-bit-rate processing clock CL2 supplied for performing the processing in the circuit 10.
Are selectively enabled only during the period corresponding to the fixed continuous bit length, and during the other periods, the processing clock CL
Stop the supply of 2. That is, the mask clock CL2 'is used.

On the other hand, in the transmission circuit 20 as well, the clock control unit 22 is introduced so that the serial data d'having a low bit rate (CL2) lower than the high bit rate (CL1) of the parallel transmission data SD is previously stored. When the fixed continuous bit length is fixed and is generated periodically, the processing clock CL2 of the low bit rate supplied for performing the process in the transmission circuit 20 corresponds to the fixed continuous bit length. It is selectively enabled only during the period, and the supply of the processing clock CL2 is stopped during other periods. That is, the mask clock CL2 'is used.

FIG. 8 is a diagram showing a specific example of the clock controller 13 (22). Note that the clock control unit is adopted on both the receiving side and the transmitting side, but both have exactly the same configuration, so the drawing will be made on behalf of the receiving side. However,
Each part corresponding to the transmitting side is represented by a reference number with (). In the receiving circuit 10, the enable pulse generator 51
AND gate 52 is used.

FIG. 9 is a time chart showing the operation of the circuit shown in FIG. In addition, in FIG.
This corresponds to the signals appearing in, and of FIG. The enable pulse generator 51 continues to generate the enable pulse only during the period corresponding to the above period after being given the head timing signal of the reception monitoring data rd ′.

The AND gate 52 outputs the processing clock () to the receiving circuit () while the enable pulse is generated. The clock from the AND gate 52 is the above-mentioned mask clock. On the other hand, in the transmission circuit 20, the enable pulse generator 61 and A
The ND gate 62 is used.

The enable pulse generator 61 continues to generate the enable pulse only during the period corresponding to the above period after the transmission start timing signal of the transmission monitor data sd 'is given. The AND gate 62 outputs the processing clock to the transmission circuit while the enable pulse is being generated (). The clock from the AND gate 62 is the above-mentioned mask clock.

FIG. 10 is a diagram showing a detailed example of a part of the remote monitoring apparatus according to the present invention (No. 1), and FIG. 11 is a diagram showing a detailed example of a part of the remote monitoring apparatus according to the present invention (No. 2). In these figures, 71 is a latch circuit and 74 is a parallel / serial conversion circuit.
And 74 correspond to the speed / serial conversion unit 12 shown in FIG.

The latch circuit 71 latches parallel reception monitoring data rd consisting of a plurality of bits for each bit. The parallel / serial conversion circuit 74 converts the parallel reception monitoring data rd consisting of a plurality of bits latched by the latch circuit 71 into serial reception monitoring data rd ′. Further, 84 is a serial / parallel conversion circuit, 8
Reference numeral 5 denotes a multiplexer, which correspond to the parallel conversion unit 26 and the monitoring information insertion unit 27 shown in FIG.

The serial / parallel conversion circuit 84 converts the serial transmission monitoring data sd 'into a plurality of bits of parallel data sd. The multiplexer 85 inserts the parallel data from the serial / parallel conversion circuit 84 into the transmission data SD in parallel as the transmission monitoring data sd. On the receiver circuit 10 side of FIGS. 10 and 11, a pulse is input to the enable terminal EN of the latch circuit 71 by the 72 frequency division counter and the decoder 73, and the data D4-1, D4-2 ... D12-8 (shown in FIG. 72 total
Data).

Further, in the embodiment, the parallel / serial conversion circuit 74 converts 72 parallel data (8 kHz) into 1.
Since it is converted to serial data of 215MHz, the frequency divider 16 divides it by 1.215MHz (= 19.44 ÷ 1).
The clock CL2 of 6) is output. The remote monitoring receiving circuit 75 includes the blocks 13 in FIG. 1 and FIG.
This is a circuit that collectively represents 14, 16 and 17.

On the other hand, on the transmission circuit 20 side in FIGS. 10 and 11, the remote monitoring transmission circuit 81 is a circuit that collectively represents the blocks 22, 23, 24 and 25 in FIGS. 1 and 2. The 72 frequency-dividing counter 82 and the decoder 83 send a signal for replacing parallel data of 8 kHz (72 lines) to parallel data of 19.44 MHz in the multiplexer 85 in the multiplexer 85.
Supply to 5.

FIG. 12 is a diagram showing a detailed example of the circuit of FIG. Since the receiving side and the transmitting side have the same configuration, they are collectively shown in the left half of the figure. In the right half, the corresponding blocks 14 in FIG. 1 and FIG.
15, 16, 17, 23, 24 and 25 are shown in simplified form. As shown in the figure, the enable pulse generation unit 51 (61) includes a preset circuit (DO) 91, an inverter (INV) 92, a counter 93, a decoder 94, a decoder 95, an AND gate 96, and a JK-flip-flop 97.

FIG. 13 is a time chart showing the operation of the circuit shown in FIG. 12, and in the figure, ...
3 is a time chart of signals appearing in respective parts of. Is a clock CL2 (1.215 MHz) having a low bit rate, and the enable pulse generator 51 (61) operates with this as a reference.

In the receiving circuit 10, is the above-mentioned head timing signal, and in the transmitting circuit 20, is the above-mentioned transmission start timing signal. This signal forms the rising edge of the pulse. Is the output of the counter 93,
The 72 bits of 71 are repeatedly counted. Counter 9
The D input of 3 is preset to 0 by the preset circuit 91. Every time the Q output of the counter 93 reaches 71, a decode pulse is output by the decoder 94, and J
Applied to the K input of K-flip-flop 97, it forms the trailing edge of the pulse. The movement of the counter 93 is stopped at the 72nd bit.

The XQ output of this flip-flop 97 is A
The AND gate 96 does not accept any noise other than the true start timing (transmission start timing) signal returned to the ND gate 96. Thus, the pulse from the JK-flip-flop 97 selectively selects the AND gate 52 only during data transmission (or data reception).
(62) is opened to generate a processing clock CL2 'in which the clock CL2 is partially masked.

The circuit at the subsequent stage is the mask clock CL.
2'can reduce power consumption. FIG. 14 is a diagram showing a detailed example of the circuit of FIG. The reception-side transparency processing unit 14 shown in FIG. 4 can be realized in detail as shown in this figure. In particular, the selection signal generation unit 33 can be realized by the 49-bit counter 101 and the 49-bit decoder 102.

FIG. 15 is a time chart showing the operation of the circuit shown in FIG. , ... in FIG.
The following shows the time charts of the signals that respectively appear in each part of. The selector unit 34 of FIG. 14 switches the 49-bit shift data to 48-bit shift data when the 49-bit shift data is being used, according to the decode value supplied from the decoder 102.

FIG. 16 is a diagram showing a detailed example of the circuit of FIG. The transmission side transparency processing unit 24 shown in FIG. 6 can be realized in detail as shown in this figure. In particular, the selection signal generation unit 43 can be realized by the 7-bit counter 111 and the 7-bit decoder 112. FIG. 17 is a time chart showing the operation of the circuit shown in FIG. In this figure,
The time charts of the signals appearing at the respective parts of FIG.

The data selection section 44 of FIG.
Decoded value given by 12, 1 in
When bit shift data is being used, "0" is inserted and then switched to 2-bit shift data.

[0066]

As described above in detail, the first aspect of the present invention
According to the aspects (1) to 10th aspect (10), the following effects are obtained, respectively. (1) Since parallel data having a high bit rate is converted into serial data for processing, the hardware is simplified and the circuit scale on the receiving side can be reduced. Moreover, since the serial data has a low bit rate, the hardware is further simplified and the power consumption is suppressed.

(2) The same effect as the above (1) can be obtained on the transmission side of the remote monitoring device. (3) Since the processing clock is masked according to the arrival of processed data, the power consumption on the receiving side is greatly reduced. (4) The same effect as (3) above can be obtained on the transmission side of the remote monitoring device.

(5) There is no known concrete example of the receiving side transparency processing section at present, but according to the present invention, the concrete example can be realized relatively simply. (6) The effect of (5) above can also be obtained on the transmission side of the remote monitoring device. (7) The method (1) (reception side) can be actually embodied as hardware.

(8) The above method (2) (transmitting side) can be actually embodied as hardware. (9) The above method (3) (reception side) can be actually embodied as hardware. (10) The method (4) (sending side) can be actually embodied as hardware.

[Brief description of drawings]

FIG. 1 is a diagram (No. 1) showing the basic configuration of a remote monitoring device according to the present invention.

FIG. 2 is a diagram (No. 2) showing the basic configuration of the remote monitoring device according to the present invention.

FIG. 3 is a diagram showing the principle of data conversion in the present invention.

FIG. 4 is a diagram showing a specific example of a reception side transparency processing unit.

5 is a time chart showing the operation of the circuit shown in FIG.

FIG. 6 is a diagram showing a specific example of a transmission side transparency processing unit.

FIG. 7 is a time chart showing the operation of the circuit shown in FIG.

FIG. 8 is a diagram showing a specific example of a clock control unit.

9 is a time chart showing the operation of the circuit shown in FIG.

FIG. 10 is a diagram (No. 1) showing a detailed example of a part of the remote monitoring device according to the present invention.

FIG. 11 is a diagram (part 2) showing a detailed example of a part of the remote monitoring apparatus according to the present invention.

12 is a diagram showing a detailed example of the circuit of FIG.

FIG. 13 is a time chart showing the operation of the circuit shown in FIG.

14 is a diagram showing a detailed example of the circuit of FIG.

15 is a time chart showing the operation of the circuit shown in FIG.

16 is a diagram showing a detailed example of the circuit of FIG.

FIG. 17 is a time chart showing the operation of the circuit shown in FIG.

FIG. 18 is a diagram showing an example of a transmission system to which the present invention is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Remote monitoring device 11 ... Monitoring information extraction part 12 ... Speed / serial conversion part 13 ... Clock control part 14 ... Transparency processing part 18 ... Monitoring information collection processing part 21 ... Speed conversion part 22 ... Clock control part 25 ... Transparency Processing unit 26 ... Parallel conversion unit 27 ... Monitoring information insertion unit 31 ... Shift register unit 32 ... Detection unit 33 ... Selection signal generation unit 34 ... Selector unit 41 ... Shift register unit 42 ... Detection unit 43 ... Selection signal generation unit 44 ... Data Selector 51 ... Enable pulse generator 52 ... AND gate 61 ... Enable pulse generator 62 ... AND gate 71 ... Latch circuit 74 ... Parallel / serial converter 84 ... Serial / parallel converter 85 ... Multiplexer

Claims (10)

[Claims] 1. A remote monitoring device (1) which processes parallel reception monitoring data inserted as monitoring information for remote monitoring in parallel reception data and then inputs the data to a monitoring information collection processing section (18). In the above, in the parallel reception data input at a high bit rate, the parallel reception monitoring data consisting of a plurality of bits is latched in parallel for each bit before the next reception monitoring data arrives. And converting the latched reception monitoring data for each of the bits into serial reception monitoring data at a low-speed bit rate lower than the high-speed bit rate, and performing the processing according to the serial reception monitoring data. Receiving method in a remote monitoring device. 2. A parallel transmission monitoring data comprising a monitoring information collection processing unit (18), processing the monitoring information for remote monitoring sent from the monitoring information collection processing unit (18), and forming the monitoring information. In the remote monitoring device (1) for inserting and outputting in parallel transmission data, the processing of the monitoring information is performed by a serial device having a low bit rate lower than the high speed bit rate of the parallel transmission data. A transmission method in a remote monitoring device, characterized in that serial transmission monitoring data after data processing is converted into parallel data and the bit rate is converted into parallel transmission data. 3. When the serial reception monitoring data has a predetermined fixed continuous bit length and is periodically generated, the low speed bit rate processing clock supplied for performing the processing. 2. The receiving method in the remote monitoring device according to claim 1, wherein the processing is selectively enabled only during a period corresponding to each of the fixed continuous bit lengths, and the supply of the processing clock is stopped during other periods. 4. When the serial data having a low bit rate lower than the high bit rate of the parallel transmission data has a predetermined fixed continuous bit length and is periodically generated, the serial data is generated. The processing clock of the low-speed bit rate supplied for performing the processing is selectively enabled only during the period corresponding to each of the fixed continuous bit lengths, and the supply of the processing clock is stopped in other periods. The transmission method in the remote monitoring device according to claim 2. 5. The remote monitoring which processes parallel reception monitoring data inserted as monitoring information for remote monitoring in high-speed bit rate parallel reception data and then inputs it to the monitoring information collection processing section (18). In the device (1),
As one of the processes, the logical "0" is deleted every time when the logical "0" inserted in the bit immediately after the predetermined number of consecutive bits of the logical "1" is detected from the bit string forming the reception monitoring data. A receiving circuit (10) including a transparent processing for performing the transparent processing and performing the above-described processing including the transparent processing by reception monitoring data converted into serial at a low bit rate, The transparency processing unit (14) for performing the security processing inputs the reception monitoring data converted into the serial,
A shift register unit (3) that outputs in parallel a plurality of serial reception monitoring data strings sequentially bit-shifted by 1 bit
1), and one of the plurality of serial reception monitoring data strings is input as a target of the above processing, and is inserted into a bit immediately after a predetermined number of consecutive bits of the logic "1" appearing therein. A detection unit (32) that detects a logical "0" that is present, and a serial reception monitor that is shifted 1 bit later than the serial reception monitoring data sequence each time the detection unit (32) performs the detection. A selection signal generator (33) for generating a selection signal for selecting a data string, and a plurality of serial reception monitoring data strings received in parallel,
And a selector unit (34) for switching to one of the serial reception monitoring data strings designated by the selection signal output from the selection signal generation unit (33) and outputting the serial reception monitoring data sequence as a target of the processing. Receiver circuit in the remote monitoring device. 6. Parallel transmission monitoring data comprising a monitoring information collection processing unit (18), processing the monitoring information for remote monitoring sent from the monitoring information collection processing unit (18), and forming the monitoring information. In a remote monitoring device (1) that inserts and outputs in parallel transmission data of high-speed bit rate, as one of the processes, a predetermined number of logical "1" s are consecutive from a bit string forming the transmission monitoring data. Each time a bit is detected, a transparent process for inserting a logical "0" into a bit immediately after the predetermined number of consecutive bits is included, and the process including the transparent process is converted into a serial at a low bit rate. A transmission circuit (20) adapted to perform the transmission monitoring data converted, wherein a transparency processing unit (24) for performing the transparency processing converts the transmission monitoring data converted into the serial data. The force,
A shift register unit (4) that outputs in parallel a plurality of serial transmission monitoring data strings bit-shifted one bit at a time
1) and one of the plurality of serial transmission monitoring data strings are input as a target of the processing, and a detection unit (4) for detecting a predetermined number of consecutive bits of the logical "1" appearing therein.
2), and each time the detection is performed by the detection unit (42), a selection signal for selecting the serial transmission monitoring data string shifted by 1 bit from the serial transmission monitoring data string is generated. The selection signal generation unit (43) and the data of logic "0" and the plurality of serial transmission monitoring data strings are received in parallel, and the detection unit (42) performs the detection, and at the same time, the logic "0". Data selected and output, and then switched to one serial reception monitoring data string designated by the selection signal output from the selection signal generation unit (43) and output as a target of the processing A transmission circuit in a remote monitoring device, characterized in that it comprises a section (44). 7. Remote monitoring for processing parallel received monitoring data inserted as monitoring information for remote monitoring in parallel received data of a high bit rate and then inputting to a monitoring information collection processing section (18). In the device (1),
A receiving circuit (1) that performs the above-mentioned processing by the reception monitoring data converted into serial at a low bit rate
0), and the parallel reception monitoring data composed of a plurality of bits are
A latch circuit (71) for latching each bit, and a parallel / serial conversion circuit (74) for converting parallel reception monitoring data consisting of the plurality of bits latched by the latch circuit (71) into serial reception monitoring data.
A receiver circuit for a remote monitoring device, comprising: 8. A parallel transmission monitoring data comprising a monitoring information collection processing unit (18), processing the monitoring information for remote monitoring sent from the monitoring information collection processing unit (18), and forming the monitoring information. In a remote monitoring device (1) for inserting and outputting in parallel transmission data of a high bit rate, the above processing is performed by the transmission monitoring data converted into serial of a low bit rate. (20) A serial / parallel conversion circuit (8) for converting the serial transmission monitoring data into a plurality of bits of parallel data.
4) and a multiplexer (85) for inserting the parallel data from the serial / parallel conversion circuit (84) into the parallel transmission data as the transmission monitoring data, the remote monitoring device comprising: Transmission circuit. 9. The remote monitoring which processes parallel reception monitoring data inserted as monitoring information for remote monitoring in high-speed bit rate parallel reception data and then inputs it to the monitoring information collection processing section (18). In the device (1),
The above processing is performed by the reception monitoring data converted into the low speed bit rate serial, and the processing clock of the low speed bit rate for performing the above processing is fixed and continuous to form the serial reception monitoring data. The receiving circuit (10) is configured such that it is selectively effective only during the period corresponding to the bit length and stops the supply of the processing clock during other periods, and is supplied with the leading timing signal of the reception monitoring data. After that, the enable pulse generator (51) that continues to generate the enable pulse only during the period corresponding to the period, and the AND gate that outputs the processing clock to the inside of the receiving circuit while the enable pulse is generated. (52) A receiving circuit of a remote monitoring device, comprising: 10. A monitoring information collecting and processing unit (18) is provided,
The monitoring information for remote monitoring transmitted from the monitoring information collection processing section (18) is processed, and the parallel transmission monitoring data forming the monitoring information is inserted into the parallel transmission data of high bit rate. In the remote monitoring device (1) for outputting, the above processing is performed by the transmission monitoring data converted into the low speed bit rate serial, and the low speed bit rate processing clock is used for performing the above processing.
A transmission circuit (20) which is selectively enabled only during a period corresponding to a fixed continuous bit length that forms the serial transmission monitoring data, and stops the supply of the processing clock during other periods. An enable pulse generator (61) that continues to generate an enable pulse only during a period corresponding to the period after the transmission start timing signal of the transmission monitor data is given, and while the enable pulse is being generated, And a AND gate (62) for outputting a processing clock into the transmission circuit.