JPH0824112B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device formed at high speed and high density and a method for manufacturing the same, and more particularly to S
The present invention relates to a semiconductor device having a metal silicide layer formed on an i substrate and a manufacturing method thereof.

[0002]

2. Description of the Related Art Titanium silicide is known to have a small specific resistance among refractory metal silicides. For this reason, titanium silicide is typically used in semiconductor devices. However, it is known that when a titanium silicide is formed or by a heat treatment at 800 ° C. or more after the formation, the film-like ones are agglomerated and partially become agglomerates, whereby the titanium silicide layer has a high resistance. . Therefore, various applicable condition ranges have been narrowed in the process of forming a semiconductor device. This drawback is common when applying metal silicide to semiconductors. A conventional technique as a means for overcoming this drawback will be described with reference to the drawings.

FIG. 5 is a process sectional view showing an example of a conventional technique. A gate oxide film 2 is formed on a silicon substrate 1 having a field oxide film 6 formed at a predetermined position by a selective oxidation method by a thermal oxidation method. Next, polysilicon is deposited by the low pressure CVD method, and heat treatment is performed in POCl ₃ ,
Conductive polysilicon 4 is formed. Next, titanium silicide 5 is formed by the sputtering method. Further, patterning is performed by photolithography and dry etching to form a titanium silicide wiring having a composite structure of conductive polysilicon 4 and titanium silicide 5. Next, after forming the source and drain of the transistor, the interlayer insulating film 9
Is deposited. Next, as a gas having hydrogen as a constituent element, heat treatment is performed in a so-called pyro atmosphere, which is a mixed atmosphere of hydrogen and oxygen, to lower the resistance of the gate wiring and activate the source / drain.

As described above, the heat treatment is carried out in a gas atmosphere containing hydrogen as a component element to suppress the aggregation of the refractory metal silicide.
It is disclosed in Japanese Patent No. 290018. However, this method cannot obtain a sufficient effect when the design rule of the silicide layer is reduced to 1 μm or less.

FIG. 6 is a process sectional view showing another example of the prior art. Silicon substrate 1 surrounded by field oxide film 6
Source / drain diffusion layer 5 in the active region, gate polycrystalline silicon 3 on the gate oxide film 2, and LD on the side surface thereof.
After forming the D sidewall 4 and depositing titanium on the entire surface to form a titanium film having a predetermined thickness, heat treatment is performed in a vacuum or in an atmosphere in which an oxidation reaction does not occur to form a titanium silicide film 8. After that, heat treatment is performed in an oxygen atmosphere at a temperature of 600 ° C. or higher and 1000 ° C. or lower for a predetermined time to form a titanium oxide film 11 on the surface of the titanium silicide film 8 so as to suppress aggregation of titanium silicide. This technique is disclosed in Japanese Patent Laid-Open No. 3-4
It is disclosed in Japanese Patent No. 6323. However, this method has a problem in that, when the diffusion layer becomes shallow due to the miniaturization of the semiconductor device and the titanium silicide layer needs to be thinned, the condition of the oxidation treatment becomes severe.

[0006]

As described above, the prior art method for preventing the agglomeration of refractory metal silicide cannot obtain sufficient effect when the design rule is miniaturized, There is a drawback that the processing conditions become severe when the film thickness becomes thin.

[0007]

A feature of the present invention is that grain boundaries and lamination of titanium silicide formed on a Si single crystal substrate.
This is in a semiconductor device in which Zr or Hf is segregated in the defects .

Another feature of the present invention is that Ti as the main material and Zr as the containing material on the surface of the silicon crystal or
The steps of depositing Hf and Hf by sputtering from a target of these metals , the step of siliciding the Ti containing the Zr or Hf, and the grain boundary / stacking fault of the formed titanium silicide are described above. And a step of segregating Zr or Hf.

Aggregation of refractory metal silicides at high temperatures is explained by surface free energy. For this reason, agglomeration is particularly likely to occur when the crystal grains are increasing. The present invention suppresses the aggregation by suppressing the increase of the crystal grains. According to the present invention, when the refractory metal silicide is formed by the metal forming the total solid solution introduced in the refractory metal silicide. It is possible to prevent an increase in the crystal grain size of.

Of the refractory metal silicides, tungsten silicide does not have thermal cohesiveness, but has a problem that it has a high inherent resistance and a strong mutual diffusion with Si.

Titanium silicide is a refractory metal silicide to which the present invention is preferably applied, which has a low specific resistance, is not so strongly inter-diffused with Si, and is a good silicide if only thermal coagulation is prevented.

Further, it is possible to prevent an increase in layer resistance due to formation of a phase having a partially different composition by incorporating a metal forming a solid solution into the refractory metal silicide. Zr, Hf, etc. are preferable as the metal that forms a solid solution.

When Zr is contained in titanium silicide, the TiSi ₂ formation temperature is 600 ° C. and the ZrSi ₂ formation temperature is about 700 ° C.
When heat treatment is performed at about 0 ° C, TiSi ₂ is first produced and Z
r can be prevented aggregation of TiSi ₂ This can suppress grain diameter increment sized TiSi2.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

1 and 2 are sectional views showing a first embodiment of the present invention. FIGS. 1 (A) to 1 (D) show a process for manufacturing a salicide transistor using Ti as a refractory metal. The applied steps are shown, and FIGS. 2A to 2D show a state in each step of forming the silicided diffusion layer.

First, as shown in FIG.
An S-type LDD structure transistor is formed. A gate electrode 3 of polycrystalline silicon is formed on a silicon substrate 1 provided with a field oxide film 6 via a gate insulating film 2. The side wall 4 of the insulating film is provided on the side surface of the gate electrode 3, and the source / side wall 4 is provided on the outer surface of the semiconductor substrate 1 immediately below the side wall 4.
Diffusion layer 5 forming the drain region is formed. Further, each element formation region is separated by the element separation region 6.

Then, a Ti-- film having a predetermined thickness is formed on the entire surface of the formed MOS type LDD structure by sputtering or the like.
The Zr film 19 is formed (FIG. 1 (B)). The thin film formation condition by sputtering is RF power of 1 KW in an Ar atmosphere of 8 mmTorr. Zr is 0.
A Ti target mixed with about 5 ATOM% is used. At this time, the surface of the diffusion layer is Ti7 as shown in FIG.
And Zr17 are in a mixed state.

Thereafter, Rapid Thermal Annealing at 600 ° C. for about 30 seconds in a nitrogen atmosphere.
(RTN) is performed to silicidize the Ti—Zr film to form titanium silicide 8. The titanium silicide 8a formed at this stage shown in FIG. 2B has a C ₄₉ type crystal structure of a metastable layer and has a larger layer resistance than that of a stable layer having a C ₅₄ type crystal structure. It has been known. The inclusion of Zr17 suppresses an increase in the crystal grain size of the silicide 8a formed at this stage. The figure shows a state in which Zr17 is segregated at the grain boundaries of the titanium silicide 8a. Further, titanium nitride 12 is formed on the surface of the diffusion layer by heat treatment.

Subsequently, the titanium nitride film 12 formed on the surface of the silicide is removed by reactive ion etching (FIG. 1 (c)). The state of the diffusion layer at this time is shown in FIG.
It looks like (c).

Next, the crystal structure of C ₄₉ type 8a is changed to C ₅₄
Type 8b is changed to perform RTN treatment at 850 ° C. for 2 seconds in order to form a low resistance silicide. By this treatment, the crystal structure of the silicide is changed from C ₄₉ type 8a to C ₅₄ type 8b, the low resistance silicide layer 8b is formed, and T
Zr17 segregates at the crystal defect 18 in the iSi ₂ crystal grain (FIG. 2 (d)).

Next, the interlayer insulating film 9 is deposited by the CVD method and deposited on the surface of the low resistance silicide layer 8 (8b), and then annealed at a temperature of 800 ° C. or higher and 1000 ° C. or lower. This annealing is performed in order to improve the film quality by thermally diffusing phosphorus, bromine or the like doped in the interlayer insulating film 9 and to planarize the film by reflow.

The conventional manufacturing method has a problem that the titanium silicide film 8 is agglomerated during the annealing. However, in this embodiment, the titanium silicide film 8 does not aggregate even after annealing, and the uniform film thickness is maintained.

After annealing the interlayer insulating film 9, a contact hole is formed and a metal wiring 10 is further formed to complete the salicide transistor (FIG. 1D).

In the present embodiment, the effect of mixing Zr into titanium silicide is considered as follows. The aggregation of titanium silicide is because the crystal grains are deformed in the direction in which the surface free energy of the crystal grains becomes smaller. For this reason, when the silicide layer is thinned, if the crystal grains are large, the shape of the crystal grains becomes flat, so that aggregation easily occurs. On the other hand, when the size of the crystal grains in the C ₄₉ phase of the metastable layer is small, it is possible to prevent the crystal grains from becoming huge when the crystal structure is changed to the C ₅₄ phase by the subsequent heat treatment. Further, it is considered that the effect of suppressing the deformation of the crystal grains by segregating Zr in the stacking faults and crystal grain boundaries in TiSi2 and suppressing the movement thereof is possible.

The element to be mixed into titanium silicide may be one that satisfies the following conditions. A solid solution is formed at all rates, and the layer resistance when forming silicide is several tens Ω / c.
Must be about m ² . As such an element, there is Hf in addition to Zr.

FIG. 3 is a sectional view showing a dynamic memory cell according to a second embodiment of the present invention. In FIG. 3, parts having the same or similar functions as in FIG. 1 are indicated by the same reference numerals. Electric charges are accumulated between the lower electrode 14 formed in contact with the impurity diffusion layer 5 formed by diffusion on the main surface of the silicon substrate 1 and the upper electrode 16 formed via the charge storage insulating film 15. . The capacitor portion thus configured is separated by the element isolation region 6 and covered with the interlayer insulating films 9a and 9b. A plurality of capacitor portions are arranged and are interconnected by a word line 3 and a bit line 13 which are gate electrodes on the element. Highly heat-resistant silicide such as polysilicon or tungsten silicide is usually used for forming the bit line, but there is a strong demand to use titanium silicide having a low specific resistance as the integration becomes higher. When forming the bit line with titanium silicide,
First, a polycrystalline silicon film is formed on the surface of the element covered with the interlayer insulating film 9a in the region where the bit line 13 is to be formed by the CVD method or the like. Next, a Zr film having a predetermined thickness of 0.5 is formed on the polycrystalline silicon film by sputtering or the like.
% Titanium film is deposited and further heat-treated in a nitrogen atmosphere at 600 ° C. to form a titanium silicide film 8. Then, heat treatment is performed at 850 ° C. to reduce the resistance of titanium silicide. At this time, the titanium nitride film 12 is formed in the region not in contact with the Si substrate 1. Here, W (tungsten) is entirely grown and then etched back to fill the contact with W. Further, the WSi wiring is sputtered and then the bit line 13 is formed by lithography. Next, the interlayer insulating film 9b is formed. After that, a capacitance contact hole is opened in the interlayer insulating films 9a and 9b, a polysilicon electrode is formed, an electric charge storage insulating film is formed, and then an upper electrode is formed. At this time, heat treatment is performed at about 800 ° C. to reduce the resistance of the polysilicon. In this case as well, in the conventional titanium silicide, agglomeration may occur and device characteristics may be deteriorated. However, the use of the present invention suppresses agglomeration. Thus, the present invention enables stable mass production of devices.

[0027]

The effect of the present invention is that Ti is used as a refractory metal.
Will be described as an example.

According to the present invention, Z is formed in titanium silicide.
By mixing r, aggregation of titanium silicide in the subsequent heat treatment step is suppressed. Therefore, the resistance increase of the titanium silicide film is suppressed, and the applicable condition range at the time of forming the semiconductor device is increased. The reason why this effect is obtained is considered as follows. That is, the agglomeration of titanium silicide causes the crystal grains to deform so that the surface free energy of the crystal grains becomes smaller.

Therefore, as shown in FIG. 4, when the silicide layer is thinned, in the case of a silicide layer of only titanium (Ti), the shape of the crystal grain becomes flat when the crystal grain is large. As shown by the mark X, aggregation occurs and the total resistance value Ra increases. On the other hand, if titanium (Ti) is 0.
In the case of the present invention in which 5% zirconium (Zn) is added, the size of the crystal grains in the C ₄₉ phase of the metastable layer becomes small,
As a result, it is possible to prevent the crystal grains from becoming large when the crystal structure is changed to the C ₅₄ phase in the subsequent heat treatment, and as a result, even if the film thickness is made thin, the layer resistance Ra is almost the same. Does not increase. In addition, the effect of suppressing the deformation of crystal grains by segregating stacking faults and crystal grain boundaries Zr in TiSi ₂ and suppressing these movements can be considered. Further, since it is not necessary to oxidize the surface of the silicide, use of the present invention enables stable device mass production even when the depth of the diffusion layer becomes shallow.

Although the case where titanium silicide is used is described in the embodiment, the same effect can be obtained by mixing nickel as a solid solution metal with cobalt silicide as a high melting point silicide. .

Furthermore, in the embodiment, Zr is mixed in Ti by the sputtering method using a Ti-Zr mixed target.
The same effect can be obtained by performing sputtering to form a two-layer structure by a method of sputtering Ti and then Zr.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a state in a manufacturing process of a silicided diffusion layer in the first embodiment.

FIG. 3 is a sectional view showing a second embodiment of the present invention.

FIG. 4 is a diagram showing a change in layer resistance when the present invention is applied and a silicide layer is thinned, in comparison with a case where the present invention is not applied and a conventional technique.

FIG. 5 is a sectional view showing an example of a conventional technique.

FIG. 6 is a cross-sectional view showing another example of the prior art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate oxide film 3 Gate polycrystalline silicon 4 LDD sidewall 5 Diffusion layer 6 Element isolation 7 Titanium 8 Titanium silicide 8a Titanium silicide (C ₄₉ ) 8b Titanium silicide (C ₅₄ ) 9 Interlayer oxide film 9a Interlayer oxide film 9b Interlayer oxide film 10 Metal wiring 11 Titanium oxide 12 Titanium nitride 13 Bit line 14 Lower electrode 15 Charge storage insulating film 16 Upper electrode 17 Zirconium 18 Crystal defect with zirconium segregated 19 Ti-Zr film

Claims (2)

[Claims] 1. A formed on the Si single crystal substrate Chitanshi
Zr or Hf is segregated at the grain boundaries and stacking faults of the silicide.
Wherein a being. 2. T as a main material on the surface of a silicon crystal body
i and Zr or Hf as a containing material
A step of depositing of sputter from the target, the Z
A method for manufacturing a semiconductor device, comprising: a step of siliciding the Ti containing r or Hf; and a step of segregating the Zr or Hf to a grain boundary / stacking fault of the formed titanium silicide .