JPH0824164B2 - Method of forming interconnects - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION RELATED APPLICATION This application is a continuation-in-part application of pending US patent application serial no. 666,715, filed October 31, 1984.

FIELD OF THE INVENTION The present invention relates to the field of integrated circuit manufacturing methods. More particularly, the present invention relates to a method of forming connections to circuit components formed in deeply etched trenches in integrated circuits.

Prior Art and Problems It is well known that metal oxide semiconductor (MOS) capacitors have superior performance compared to other capacitor structures in integrated circuits. One aspect where MOS capacitors are excellent is the perfection of charge when alpha particles enter the capacitors. This is especially important in dynamic random access memory (dRAM). If the charge on the storage capacitor of the dRAM cell changes, the stored data will be erroneous. This is a form of soft error and is a widely recognized problem. The reason why soft error does not occur easily in MOS capacitors is that the α-particle must add enough energy to the electron and bring it to the conduction band of the oxide of this electron, but this conduction band is very high. .

One of the most recently developed MOS capacitors is the trench type.
It is Kyapashita. This capacitor is formed by etching a cavity in the surface of the substrate, forming an insulator on the side surface of the trench, and filling the trench with a conductive material. One plate of the capacitor is formed by the conductive material in the trench and the other is formed by the substrate. In order to have the soft error characteristics described above, the charge must be stored in an inner conductive layer that is electrically isolated from the substrate by an insulator. Electrical contacts to the conductive layers are provided by conventional integrated circuit interconnect methods.
Must be provided at the top of the trench. However, the better way of contacting the conductive layer allows the upper portion of the trench to be used for other purposes. This is one advantage of the present invention.

Another problem with integrated circuit manufacturing is minimizing the surface area required for a particular component. FIG. 1 is a simplified side view showing a conventional interconnection between a first level polycrystalline silicon interconnection and a source / drain region of a field effect transistor. As shown in FIG. 1, the required spacing for this interconnect is about 2.5 microns. The spacing between the interconnect and the gate and the opening between the insulator below the interconnect and the source / drain regions requires 1 micron each. In addition, 0.5 micron is required for alignment error.

Means and Actions for Solving Problems The present invention will be described in the case of manufacturing a dRAM cell, which is an important application of the present invention. The cell described here creates a dRAM cell structure and array of one transistor and one capacitor, and the pass transistor of the cell is formed on the side wall of the substrate trench having the cell capacitor, and the word line and bit line are formed. Intersect on this trench. This stacking of transistors on top of the capacitors minimizes the area of the cell on the substrate and solves the problem of tight cell packing.

One plate of the capacitor and the channel and source regions of the transistor are formed in the bulk sidewall of the trench, and the gate of the transistor and the other plate of the capacitor are both formed in the polysilicon of the trench, but oxidation in the trench They are separated from each other by a physical layer. By electrically connecting the source region of the vertical pass transistor to the polysilicon plate of the capacitor, the signal charge is transferred to the polysilicon plate of the capacitor. This connection between the source and the polysilicon capacitor plate, made in accordance with the presently described embodiment of the invention, is referred to as a buried lateral contact.

Another embodiment of the invention is an interconnect between the surface conductor and the surface of the substrate. This embodiment uses a conductive plug formed between the conductor and the substrate to form the interconnect using the minimum surface area of the substrate.

Embodiment The dRAM cell of the preferred embodiment is a transistor 1 connected to a bit line and a word line as shown in the circuit diagram of FIG. 2A.
Cells, one capacitor, and operates as described below. Capacitor 12 stores a charge representing an information bit. (For example, the absence of stored charge represents a logical 0,
A stored charge corresponding to a voltage of 5 volts across the capacitor plates can represent a logic one. The information bit is accessed (read or write a new bit) by applying a voltage to the word line 14 connected to the gate 16 and turning on the transistor 18. Turned on transistor 18 connects capacitor 12 to bit line 20 for read or write operations. Leakage current and capacitor
Due to the other sources of decay of the 12 charges, a periodic refresh of the charges is required, which is why the dynamic RAM (dRA
The name M) was born.

FIG. 2B is a plan view of a portion of a dRMA array having bit lines 20 and word lines 14 with the preferred embodiment cell 30 at the intersection of these lines. Note that bit line 20 passes under word line 14. The cells penetrate into the substrate below these lines, creating the highest density memory. If the smallest feature size is represented by f and the smallest match is represented by R, the cell area is [2 (f + R)]. For example, if the minimum feature size is 1.0 micron and the minimum alignment tolerance is 0.25 micron, then the cell area is about 6.25 square microns.
FIG. 3 is a sectional view of the dRAM cell 30 of the first preferred embodiment. A cell 30 is formed in a p + type silicon substrate 32 having a p type epitaxial layer 34 and comprises an n + type polysilicon bit line 20, a bit line insulating nitride 42, a field oxide 36, an n + type polysilicon word. Line 14, transistor
18, channel 44, transistor 18, gate oxide 46,
The n-type diffusion region 48 forming the source of the transistor 18, the n + type polysilicon region 50 forming one plate of the capacitor 12 (the other plate and ground are formed by the p + type substrate 32), the pole of the capacitor 12 Oxide 52 forming the insulator between the plates, insulating oxide 56 separating the word line 14 from the capacitor electrode plate 50, n-type diffusion region 22 forming the drain of transistor 18, connecting bit line 20 to drain region 22. Do n
An n-type polysilicon region 21 and an n-type polysilicon region 49 connecting the source 48 with an n + type capacitor plate 50. The gate 16 of transistor 18 is simply the portion of word line 14 that crosses channel region 44 and gate oxide 46.
The cell 30 shown in FIG. 3 is a cross-sectional view taken along the vertical line 2-2 in FIG. 2B. The square cross section of the trench containing capacitor 12 and transistor 18 is evident in FIG. 2B.

In cell 30, one electrode plate of capacitor 12 is an n + type region.
50 and the n-type region 48, the other plate is the substrate 32 and the epitaxial layer 34. However, the doping of the epitaxial layer 34 is lower than that of the p + type substrate 32, so that the region
48 and the n / p junction capacitance of the epitaxial layer 34 and n
The capacitance of the + -type region 50 / oxide 52 / p-type epitaxial layer 34 is smaller than the capacitance of the n + -type region 50 / oxide 52 / p + -type substrate 32, and can be ignored. I can. As will be described further below, the area of the electrode of the epitaxial layer 34 is smaller than that of the substrate 32, so that the capacitance associated with the epitaxial layer 34 becomes less of a problem. Therefore, the bulk of the charge stored in the capacitor 12 is
It is separated from the substrate 32 (and the epitaxial layer 34) by 52. In a trench with a cross section of 1 micron by 1 micron and a depth of 6 microns, the plate area of the capacitor 12 is about 21 square microns, where 1 micron of depth is the epitaxial layer 34 and bit lines 20. The p + type substrate 32 is the common ground for all cells 30 of the array.

The transistors 18 of the cell 30 are all contained in bulk silicon and have a polysilicon gate. The channel region 44 is part of the p-type epitaxial layer 34, the source region 48 (also part of the plate of the capacitor 12) and the drain region 20 are the n-type diffusions of the p-type epitaxial layer 34. , A gate oxide 46 is grown on the surface of the trench in p-type epitaxial layer 34, and gate 16 is part of polysilicon word line 14. Field oxide 36 is fairly thick and minimizes bit line 20 capacitance.

The dimensions and materials specific to the cell 30 will be best understood from the following description of the method of manufacture of the first preferred embodiment. 4A to 4G show a series of steps of the method.

1. A p-type epitaxial layer 34 is grown at a carrier concentration of 2 × 10 ¹⁶ / cm ^{3 on} a 100-oriented p + -type silicon substrate 32 having a resistivity of less than 1E-2 ohm · cm, and its thickness is After heat treatment, the final thickness of the p-type epitaxial layer is 2 microns. Field oxide 36 (Protective oxide 37
Are formed by standard processes. As an example, the SWAMI process can be used (strain relief oxide growth, low pressure chemical vapor deposition (LPCVD) to deposit nitrides, nitride-oxide-silicon patterns and plasma deposition).・ Etching, implanting boron to the channel stopper, growing a second strain relief oxide, depositing a second nitride, LP
Deposit CVD oxide, plasma etch LPCVD oxide-nitride, wet etch remaining LPCVD oxide filaments in previous etch, thermally grow field oxide to give roughly planar Make a structure,
Remove the nitride). Whichever method is used, the final thickness of the field oxide 36 is 5,000Å and the protective oxide 37
Is about 200Å. LP of 2,000Å polysilicon 20
Deposit by CVD, dope to a carrier concentration of 1 × 10 ²⁰ / cm ³ , pattern and etch, bit line
Forming 20. Optionally, the polysilicon bit lines can be replaced with n + type diffusion bit lines. Next, a 10,000 Å nitride 42 is deposited by LPCVD. See Figure 4A. Layer 42 may be a layer composed of deposited nitrides and oxides.

2. Define a pattern of nitride 42 to define a 1 micron square trench. The patterned nitride 42 is then used as a mask for drilling tretine to a depth of 8 microns by reactive ion etching (RIE) with hydrochloric acid. A wet acid etch is used to remove RIE damage and contamination from the trench walls. See FIG. 4B. Note that oxide 42 has also been partially removed by RIE.

3. Grow oxide 52 to a thickness of 200Å on the walls and bottom of the trench. The trench is then part of a 7,000-percent LP + n + polysilicon deposition by LPCVD.
Fill with n + doped polysilicon. See FIG. 4C.

4. Polysilicon 50 is planarized by using a spin-on photoresist, etc., and completely removed on the surface, and within the trench, approximately 3,000 Å from the interface of epitaxial layer 34 / substrate 32.
Etch to remove up. See Figure 4D. As will be seen later, the location of the top of polysilicon 50 remaining in the trench largely determines the bottom of the channel of transistor 18. Note that the nitride layer 42 has been further eroded by the plasma etch, but is still at least 2,000 Å thick.

5. Etch the exposed portion of oxide 52 and continue this etching until overetching 1,000 to 2,000 liters of oxide. This excess etching removes the top of the oxide 52 between the epitaxial layer 34 and the polysilicon 50 to a depth of 1,000 to 2,000 Å, as shown by arrow 53 in FIG. As shown by arrow 39, the epitaxial layer
1,000 to 2,000Å of protective oxide 37 between 34 and bit line 20
Is also removed, in effect this excess etch is 1,00
Form two small annular fissures with a depth of 0 to 2,000Å and a width of 200Å. One of these smaller cracks surrounds the top of the polysilicon 50, as indicated by arrow 53, and the other crack extends horizontally along the boundary of bit line 20, as indicated by arrow 39.

6. Deposit 500Å polysilicon 51 by LPCVD. This is thick enough to ensure that the small crevices shown by arrows 53, 39 in Figure 4E are filled. See Figure 4F.

7. Thermally grow 500Å oxide 55. It is too far from the oxidation interface. All polysilicon except in the small crevices shown by arrows 53 and 39 in Figure 4E.
Just enough oxidation to oxidize 51. The epitaxial layer 34 consumed by this amount of oxidation is very small. Due to the high temperature of the thermal oxidation of the polysilicon 51, the topant in the n + type polysilicon 50 passes through the polysilicon in the small crevice indicated by the arrow 53, and the p type epitaxial layer
Spread to 34. This diffusion of dopant results in n-type polysilicon region 49 and n-type region 48 in p-type epitaxial layer 34.
To form. See Figure 4G. In addition, the dopant from bit line 20 also diffuses into the epitaxial layer 34 through the polysilicon in the small crevice indicated by arrow 39, thereby causing an n-type polysilicon region in the epitaxial layer 34.
21 and n-type region 22 are formed. See Figure 4G. 500 can be selected from areas other than the backfilled crack areas 39 and 53 by optional selection.
Å Polysilicon 51 can be removed by a timed wet chemical silicon etch. This is followed by a thermal anneal to add the n + type dopant to the regions 53,39.
Can be spread to. N formed in the regions 53 and 39
The + type polysilicon contacts are called buried lateral contacts.
As can be seen in FIG. 4G, the buried lateral contacts allow the trench transistor to be connected to the trench capacitor and polysilicon bit lines in an efficient and compact manner.

8. Remove oxide 55 by etching and remove gate oxide 46.
And thermally grow the insulating oxide 56. 25 gate oxide 46
It is grown to a thickness of 0Å, so that the oxide 56 is
It also grows on the + -doped polysilicon 50, so it is somewhat thicker. Finally, by LPCVD, 7,000
A word line 14 is formed by depositing n + type polysilicon of Å, defining a pattern and etching. See Figure 3 for the completed cell. Gate 16
(A part of the word line 14 facing the channel 44)
However, it controls the entire channel 44, even though the oxide 56 is thick. This is because the n-type region 48 forming the source of the transistor 18 diffuses the dopant from the polysilicon 50 into the polysilicon region 49, thus extending horizontally from region 49 to the epitaxial layer 34. This is to get in. This vertical diffusion extends to the extent that the gate 16 controls the entire channel 44.

Whether the change is independent or in combination, the signal charge is stored by the capacitor or the transistor is turned on / off.
In terms of not being able to spin off action, preferred embodiments include
Many modifications can be made within the scope of the invention. These changes are described below.

The cross section of the trench can be any convenient shape, such as circular, rectangular, arbitrarily convex, corrugated or multi-connected (ie including multiple trenches), and vertically
It may change continuously or stepwise or both.
Similarly, the sidewalls of the trench need not be vertical, but any shape that can be processed, such as bulging, tapered and beveled sidewalls, will work to varying degrees. In fact, any easily connected trench is functionally equivalent to the parallelogram of the preferred embodiment. Lastly, the dimensions of the trench (depth, cross-sectional area, diameter, etc.) can be changed, but in reality, it is a trade-off between the convenience of the process, the required capacitance, the area of the substrate, etc. Of course, the required capacitance is related to refresh time, transistor leakage current, immunity to supply voltage soft errors, capacitor leakage current, etc.

Capacitor insulators can be any convenient material, such as oxides, nitrides, oxide-nitrides, oxide-nitride-oxides, and other stacking combinations, where the oxide is a thermal material. It may be growth, LPCVD, dry or steam growth and the like. The thickness of the insulator can be varied greatly depending on the convenience of the process, the reliability of the insulator, the dielectric constant, the breakdown voltage, and the like. Of course, when the cell and array are made in a semiconductor material other than silicon (such as gallium arsenide, aluminum gallium arsenide, gallium arsenide, mercury cadmium telluride, germanium, indium phosphide, etc.), the insulator of Capacitor is also a corresponding material. become. If the capacitor is formed with a reverse biased junction, the doping distribution can be varied, the choice being a tradeoff of process convenience, cell size, and capacitor performance. Similarly, amorphous silicon can be used in place of polysilicon and the etching to form the cracks can be wet or dry (plasma).

By adjusting the threshold voltage (such as by performing shallow diffusion in the channel just prior to gate oxide growth or deposition), transistors can be formed to operate at different threshold voltages. The characteristics of the transistor can be changed by changing the doping level and the doping type. The channel length of the transistor is roughly determined by the depth of the trench, the width of the channel is roughly equal to the perimeter of the trench, and the n-channel and p-channel devices require oppositely doped regions. Please note that. The transistor gate may be polysilicon, metal, silicide or the like. All of these changes affect the performance of the transistor, but in other respects of the cell, including the required read and write time, electrostatic charge, and refresh time, if the transistor behaves properly as a pass transistor for the cell. ,
Can accept.

FIG. 5A is a simplified side view showing the initial processing steps for making an interconnect in accordance with another embodiment of the present invention. The field isolation region 2 is formed in the substrate 1 to a thickness of about 1,000 Å by using a widely known method. A thin oxide layer 3 is deposited on the surface of the substrate 1 by thermal oxidation as is well known in the art.
Form to a thickness of 250Å. Using chemical reaction vapor deposition,
A polycrystalline silicon layer 4 is formed on the surface of the silicon dioxide layer 3 to a thickness of about 5,000Å. Then, the pattern of the polycrystalline silicon layer 4 and the silicon dioxide layer 3 is defined and etched by using a conventionally known photolithography method. The polycrystalline silicon layer 4 serves as an implantation mask for implanting phosphorus ions with an energy of, for example, about 50 kiloelectron volts and a density of about 1 × 10 ¹⁵ ions / cm ² . By implanting this ion, 5C
Source / drain regions 6 are formed as shown.
Next, a photoresist protective mask is formed on the polycrystalline silicon layer 4 and a part of the silicon dioxide layer 3. This photoresist layer 5 acts as an etch mask. The structure of Figure 5C is then exposed to a wet etching solution that is highly selective to silicon dioxide, such as a wet etch of about 10% hydrofluoric acid.

In order to make the photoresist layer 5 resistant to undercut etching, it must be heat treated or treated with UV light to cure it. For example, when using Shipley 1400-27 photoresist, the photoresist must be exposed to deep UV radiation and annealed at 160 ° C. for about 30 minutes to provide a proper cure. Next, the photoresistor layer 5 is removed by using a conventionally known method. Next, as shown in FIG. 5D, a 250 Å-thick polycrystalline silicon layer 7 is deposited in the same shape by chemical reaction vapor deposition. It is important that this isomorphic deposition fills the area that is left vacant by the undercut of the silicon dioxide layer 3 under the polycrystalline silicon layer 4. Next, the polycrystalline silicon layer 5 is subjected to thermal oxidation in a vapor atmosphere at about 900 ° C. for about 10 minutes. By this thermal oxidation, the silicon dioxide layer 8 as shown in FIG. 5E is obtained, but as shown in FIG. 5E, the plug 9 of polycrystalline silicon is not oxidized. During this oxidation, the dopant in the polycrystalline silicon layer 4 diffuses into the plug 9 of polycrystalline silicon, forming the portion of the source / drain layer 6 labeled 6A. This diffusion ensures a reliable ohmic contact to the source / drain regions and avoids shorting the polycrystalline silicon layer 4 to the substrate 1.

FIG. 5F is a simplified side view showing the structure of FIG. 5E with the silicon dioxide layer 8 removed. Comparing this structure with the structure of FIG. 2, it can be seen that the structure of FIG. 5F requires approximately half the required lateral spacing compared to the lateral spacing of the structure of FIG. When using a 1 micron minimum platemaking, a spacing of about 1.25 microns between the two portions of polycrystalline silicon layer 4 is required to make the interconnect and the gate of field effect transistor 10. This interval is equal to the polycrystalline silicon layer 4
A minimum platemaking spacing of 1 micron between the two parts of the .alpha. And a matching tolerance of 0.25 micron is required. Thus, this embodiment of the present invention uses the minimum surface area of the integrated circuit device to make the interconnect.

While particular embodiments of the present invention have been described, this should not be construed as limiting the scope of the invention. The invention is limited only by the claims.

 The following section is further disclosed in connection with the above description.

(1) A first region is provided, an insulating layer is formed on the first region, and a second region is formed on the insulating layer. Among the insulating layers, the first and second regions are formed. Forming a interconnect including removing a portion between the regions and filling the area from which the insulating layer has been removed with a conductive material.

(2) The method according to item (1), wherein the first region is a diffusion region in the substrate.

(3) The method described in the item (1), wherein the insulating layer is made of silicon dioxide.

(4) The method according to item (1), wherein the second region is made of polycrystalline silicon.

(5) In the method described in (1), the portion of the insulating layer to be removed is removed by chemical etching with a liquid.

(6) The method described in the item (1), wherein the conductive material is polycrystalline silicon deposited by isomorphic deposition.

(7) The method according to item (6), wherein the isomorphic deposition is chemical reaction vapor deposition.

(8) A semiconductor substrate having a first conductivity type is prepared, a void is formed in the substrate, and an insulating layer is formed on the wall of the void,
Forming a conductive layer on the insulating layer, removing a portion of the insulating layer between the substrate and the conductive layer, filling a region where the insulating layer is removed with a conductive contact material, and backfilling the conductive layer; Forming an interconnect in an integrated circuit including removing an excess of the conductive contact material from a region other than a void.

(9) A method according to item (8), including forming a region having a second conductivity type in the substrate adjacent the conductive contact material.

(10) The method according to item (8), wherein the portion of the insulating layer to be removed is removed by chemical etching with a liquid.

(11) The method according to item (8), wherein the conductive material is polycrystalline silicon deposited by isomorphic deposition.

(12) The method according to item (11), wherein the isomorphic deposition is chemical reaction vapor deposition.

(13) A substrate having a first conductivity type is prepared, a region having a second conductivity type is formed in the substrate, an insulating layer is formed on the surface of the substrate and the region, and the surface of the insulating layer is formed. Forming a conductive layer, removing a part of the insulating layer between the conductive layer and the region, and filling the removed part of the insulating layer with a conductive material.

(14) In the method described in (13), the portion of the insulating layer to be removed is removed by chemical etching with a liquid.

(15) The method described in (13) above, wherein the conductive material is polycrystalline silicon deposited by isomorphic deposition.

(16) The method described in (15), wherein the isomorphic deposition is chemical reaction vapor deposition.

(17) A first region is prepared, an insulating layer is formed on the first region, and a second region is formed on the insulating layer. Among the insulating layers, the first and second regions are formed. A product formed by a method comprising the step of removing a portion between two and filling the area from which the insulating layer has been removed with a conductive material.

[Brief description of drawings]

FIG. 1 is a simplified side view of a conventional interconnect between a surface conductor and a diffusion in a substrate, and FIGS. 2A and 2B are equivalent circuits of a preferred embodiment dRAM cell and a portion of a memory array. Figure showing the shape, Figure 3 is the first section taken along the line 2-2 in Figure 2B.
4A-4G are simplified side cross-sectional views of a preferred embodiment dRAM cell of the present invention, a series of steps of a method of manufacturing a memory cell of one embodiment of the present invention by a method according to another embodiment of the present invention. FIGS. 5A to 5F are views showing a series of steps of a method for manufacturing another embodiment of the present invention. Explanation of main symbols 1: Substrate 3: Thin oxide layer 4: Polycrystalline silicon layer 9: Conductive plug 10: P− type substrate 12: Buried DUF collector region 14: N− type epitaxial layer 18: Trench 48: Intrinsic Base area 49: Emitter area 58: Extrinsic base area 62: Collector contact area

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 21/90 C (72) Inventor William F. Richardson 1109 Princeton, Richardson, Texas, USA (72) Inventor Satto Winders. Maruhi Meadow Ridge Drive, Garland, Texas, USA 2626 (56) References JP-A-59-141262 (JP, A) JP-A-61-108163 (JP, A)

Claims (1)

[Claims] 1. A semiconductor substrate having a first conductivity type is prepared, a cavity is formed in the substrate, an insulating layer is formed on a wall of the cavity, and a conductive layer is formed on the insulating layer. A part of the insulating layer between the substrate and the conductive layer is removed, and the removal is performed by selectively etching the insulating layer, in which case the etchant is the conductive layer and the conductive layer. The insulating layer is selectively etched with respect to the substrate, the area where the insulating layer is removed is filled with a conductive contact material, and the excess portion of the conductive contact material is removed from a region other than the backfilled void. And forming an interconnect in an integrated circuit including the steps of: