JPH08241930A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [Purpose] When an n-type diffusion layer and a p-type diffusion layer of a CMOS device are formed and then an interlayer insulation film is formed, peeling of the interlayer insulation film on the gate wiring is prevented. [Composition] In a manufacturing process of a CMOS device, a field insulating film is formed in an element isolation region on a semiconductor substrate, then a gate insulating film is formed on the element region, and a gate insulating film is formed through the gate insulating film. The method has a step of forming a gate wiring extending in the central portion and on the field insulating film, and a step of performing ion implantation into the element regions on both sides of the gate wiring, and the one-conductivity type by the ion implantation step. Manufacture of a semiconductor device using an implantation mask that covers an opposite conductivity type channel FET and an intermediate mask extending from the opposite conductivity type channel FET to an adjacent one conductivity type channel FET to cover the gate wiring when forming the channel FET Method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a source / drain diffusion layer of a CMOS device.

With the recent increase in the speed of devices, it has been required to reduce the resistance of wiring materials, and tungsten silicide is often used as the wiring material. Also, CMOS
In the device, the resist mask for ion implantation at the time of forming the n-type diffusion layer and the p-type diffusion layer is increased by increasing the opening area of the resist mask as a measure to prevent the charge-up of the substrate at the time of implantation. Prevents destruction. The present invention can be used for manufacturing this type of CMOS device.

[0003]

2. Description of the Related Art Next, a conventional example of an ion implantation process for forming an n-type diffusion layer and a p-type diffusion layer of a CMOS device will be described.

3A and 3B are explanatory views of a conventional example. In the figure, 1 is a p-channel field effect transistor (FET),
2 is n-channel FET, 3 is gate wiring, 4 is p-channel FET
, A resist mask for covering the n-channel FET. The outside of the element region (region of each FET) is covered with a field oxide film, and the gate wiring is formed on it.

In FIG. 3A, the implantation mask for forming the diffusion layer of the n-channel FET 2 is the resist mask 4 which only covers the p-channel FET. This is the minimum necessary area for increasing the opening area of the resist mask as described above.

In FIG. 3B, the implantation mask for forming the diffusion layer of the p-channel FET 3 is the resist mask 5 which only covers the n-channel FET. This is also the minimum required area for increasing the opening area of the resist mask as described above.

[0007]

As in the conventional example, at the time of ion implantation for forming the n-type diffusion layer and the p-type diffusion layer, n-type ions (P ⁺ , As ⁺ ) and p-type are formed on the gate wiring. Ion (BF ₂
⁺ ) Is repeatedly injected in the same place. That is, the pattern data of the resist mask for implanting n-type ions is p
Only the region where the type ions should not be implanted is masked, and the p-type ion implantation is the opposite.

Therefore, both n-type and p-type ions are implanted into the gate wiring on the field oxide film in the element isolation region. In this case, the implanted fluorine is likely to diffuse due to the subsequent oxidation or heat treatment such as when growing a silicon oxide film by vapor phase epitaxy (CVD) as an interlayer insulating film,
Fluorine gas is released. The oxide film deposited at that time causes a bulge between the gate insulating film and the oxide film due to the influence of the gas (see FIG. 4), and the oxide film is peeled off.

FIG. 4 is an explanatory view of the problems of the conventional example. In the figure, 11 is a silicon (Si) substrate, 12 is a gate insulating film that is a silicon oxide (SiO ₂ ) film, 13 is a gate material that is a polysilicon film, 14 is a gate material that is a tungsten silicide film, and 14 is an interlayer insulating film. Silicon oxide film, 16 by phase growth (CVD) growth, is a cavity created by the diffusion and collection of fluorine.

An object of the present invention is to prevent peeling of an interlayer insulating film on a gate wiring when forming an interlayer insulating film after forming an n-type diffusion layer and a p-type diffusion layer of a CMOS device.

[0011]

[Means for Solving the Problems] The above-mentioned problems are solved by CMOS.
In a device manufacturing process, a field insulating film is formed in an element isolation region on a semiconductor substrate, a gate insulating film is then formed on the element region, and a gate insulating film is formed in the central portion of the element region. The method has a step of forming a gate wiring extending on the field insulating film and a step of implanting ions into the element regions on both sides of the gate wiring, and the one-conductivity-type channel FET is formed by the ion implantation step. When doing
Opposite conductivity type channel FET and the opposite conductivity type channel FET
It is achieved by a method of manufacturing a semiconductor device using an implantation mask that covers the gate wiring in a range wider than an intermediate point from one to the adjacent one conductivity type channel FET.

[0012]

In the present invention, in order to prevent at least p-type ions from being implanted into the gate wiring, a p-type ion implantation is performed to form a resist mask covering the p-channel FET and the gate wiring. Is prevented and peeling of the interlayer insulating film grown thereon is suppressed.

Therefore, according to the present invention, it is possible to carry out the processing only by changing the pattern data without changing the process flow, and it is possible to easily prevent the occurrence of defects.

[0014]

[Embodiment] Next, an embodiment of an ion implantation step when forming an n-type diffusion layer and a p-type diffusion layer of a CMOS device will be described.

1A and 1B are explanatory views of the first embodiment.
In the figure, 1 is a p-channel FET, 2 is an n-channel FET, 3
Is a gate wiring, 4A is a resist mask that covers part of the p-channel FET and gate wiring, and 5A is a resist mask that covers part of the n-channel FET and gate wiring. Also, each FE
The area outside T is covered with a field oxide film, and a gate wiring is formed on it.

In FIG. 1A, the implantation mask for forming the diffusion layer of the n-channel FET 2 is a p-channel FET and a resist mask 4A which covers a part of the gate wiring. This is not the minimum area required to increase the opening area of the resist mask as in the conventional example, but the p-channel of the gate wiring
The area between the FET and the n-channel FET is covered with a resist mask up to the region where a margin for misalignment in the lithography process is taken.

In FIG. 1B, the implantation mask for forming the diffusion layer of the p-channel FET 1 is a resist mask 5A which covers the n-channel FET and a part of the gate wiring. This is also not the minimum area necessary to increase the opening area of the resist mask as in the conventional example, but the p-channel of the gate wiring
The area between the FET and the n-channel FET is covered with a resist mask up to the region where a margin for misalignment in the lithography process is taken.

2A and 2B are explanatory views of the second embodiment.
In the figure, 1 is a p-channel FET, 2 is an n-channel FET, 3
Is a gate wiring, 4B is a resist mask covering almost the entire area of the p-channel FET and the gate wiring, and 5B is a resist mask covering almost the entire area of the n-channel FET and the gate wiring. The area outside each FET is covered with a field oxide film, and the gate wiring is formed on it.

In FIG. 2A, the implantation mask for forming the diffusion layer of the n-channel FET 2 is a resist mask 4B that covers almost the entire area of the p-channel FET and the gate wiring. Although this is not the minimum area required to increase the opening area of the resist mask as in the conventional example, the resist mask covers almost the entire region of the gate wiring extending on the p-channel FET and the field insulating film. .

In FIG. 2B, the implantation mask for forming the diffusion layer of the p-channel FET 3 is a resist mask 5B that covers almost the entire area of the n-channel FET and the gate wiring. This is also not the minimum area necessary to increase the opening area of the resist mask as in the conventional example, but the resist mask covers almost the entire region of the gate wiring extending on the n-channel FET and the field insulating film. .

Next, an outline of the process flow of the embodiment will be described. This is the same as the process flow of the conventional example as described above. A vapor deposition (CVD) method is used to cover the gate insulating film and deposit a polysilicon film with a thickness of 80 to 120 nm on the substrate. Deposit a low temperature deposition tungsten silicide film 150-250 nm thick. Wiring film (Polysilicon film and Tungsten silicide film are patterned to form gate wiring. Tungsten silicide crystallization annealing and sacrificial oxidation for ion implantation are performed. Oxidation temperature is 800 ℃ or higher, and oxidizing atmosphere is oxygen. An n-type diffusion layer is formed by ion implantation.

The ion implantation conditions are As ⁺ and energy.
It is 70 KeV and the dose is 4 × 10 ¹⁵ cm ^-2 . A p-type diffusion layer is formed by ion implantation.

The implantation conditions are that the ion species is BF ₂ ⁺ , the energy is 60 KeV, and the dose is 1 × 10 ¹⁵ cm ^-2 . Thickness as an interlayer insulation film by high temperature CVD method at 800 ℃ 1
A silicon oxide film of 00 nm is formed. Then, a 400 nm-thick film was formed as a planarization insulating film on the substrate.
Deposit a phosphosilicate glass (PSG) film. The substrate is placed in oxygen at 900 ° C or higher for 30 minutes to perform the planarization process.

Although only ions of p-type impurities are implanted with ions containing fluorine, in the embodiment, it is possible to avoid implanting both p-type and n-type ions at the same position, and p When forming the type diffusion layer, the mask covering the gate wiring is used as in the case of forming the n type diffusion layer.
It is self-evident that the gist of the present invention does not change even if only the p-channel FET is conventionally covered when forming the p-type diffusion layer.

[0025]

According to the present invention, when the interlayer insulating film is formed after the n-type diffusion layer and the p-type diffusion layer of the CMOS device are formed, the interlayer insulating film on the gate wiring is peeled off due to the emission of the injected fluorine. Can be prevented. As a result, the manufacturing yield and reliability of the device can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of Example 1.

FIG. 2 is an explanatory diagram of Example 2.

FIG. 3 is an explanatory diagram of a conventional example.

[Figure 4] Illustration of problems

[Explanation of symbols]

1 p-channel FET 2 n-channel FET 3 Gate wiring 4A p-channel FET and a resist mask that covers part of the gate wiring 4B p-channel FET and a resist mask that covers almost the entire area of the gate wiring 5A n-channel FET and part of the gate wiring Resist mask to cover 5B Resist mask to cover almost the entire area of n-channel FET and gate wiring

Claims (1)

[Claims] 1. A process for manufacturing a CMOS device, comprising forming a field insulating film in an element isolation region on a semiconductor substrate,
Next, a step of forming a gate insulating film on the element region, forming a gate wiring extending through the gate insulating film in the central portion of the element region and on the field insulating film, and on both sides of the gate wiring. And a step of implanting ions into the element region of the one conductivity type channel FE.
When forming T, the opposite conductivity type channel FET and the one conductivity type channel FET adjacent to the opposite conductivity type channel FET
A method of manufacturing a semiconductor device, characterized in that an implantation mask covering the gate wiring is used in a range wider than the intermediate point up to.