JPH08274331A - MOS semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] Suppression of gate impurity extraction by silicide without impairing the adhesion of the silicide layer, the corrosion resistance, and the low resistance of the gate. [Structure] A polysilicon layer 3 forming a gate electrode,
Refractory metal silicide layer 5 (WSix, TiSix, M
A grain boundary 4 (grain boundary portion on the surface of the polysilicon layer) of the polysilicon layer 3 in the vicinity of the interface (oSix, etc.) is oxide silicide, nitride silicide, or oxynitride silicide. To obtain such a structure, before forming the refractory metal silicide layer on the polysilicon layer forming the gate electrode,
A wet etching step of the surface of polysilicon, a step of depositing an extremely small amount of a silicide material, an oxidation and / or nitriding step, and an insulating film etch back step are performed in this order.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art Conventionally, CMO of sub-half micron or less
In the S device, both the Pch-Tr and the Nch-Tr need to be surface type in order to suppress the short channel effect.
Type impurities to the Nch-Tr polysilicon gate
It has been considered to adopt a dual gate that introduces (implants) a type impurity.

In this case, both gates are connected by an ohmic junction (necessary for avoiding threshold voltage shift and for speeding up), and gate resistance / contact resistance is reduced (necessary for speeding up. P
Boron (B), which is a type impurity, has a low solid solubility limit and has a higher resistance than the conventional N ⁺ gate because it uses an implantation method. Therefore, techniques such as polycide and salicide are indispensable. .

When forming the polycide gate, WSix, W and the like, which have good heat resistance (high melting point) and corrosion resistance (adhesion), are the most suitable materials. However, this silicide has a high diffusion coefficient with respect to implanted impurities, and impurities (particularly B) are sucked out from the polysilicon gate to deplete the gate (which causes fluctuations / shifts in threshold voltage, deterioration in reliability over time of oxide film, etc.). It is known that the gate depletion is caused also by causing the impurities to be diffused or diffusing the sucked-out impurities into the polysilicon layer on the opposite side (P type-polycide-N type) (interdiffusion via silicide).

The following method has been proposed as a method for suppressing the above-mentioned impurity extraction and mutual diffusion through silicide. A low resistance diffusion preventing film (having a smaller diffusion coefficient of impurities than WSi) such as TiN is provided as an intermediate layer between the polysilicon layer and the silicide (polycide) layer. As specific examples, JP-A-1-265542 and JP-A-2-26542.
Examples thereof include those described in Japanese Patent Laid-Open No. 183565 and Japanese Patent Laid-Open No. 2-192161. This technique is considered to be extremely effective, but Ti lacks heat resistance and corrosion resistance as compared with W (this is the reason why WSi is generally used as a material for polycide), so there is concern about film peeling or the like. .

In the above technique, a low melting point metal is used as the intermediate layer. As a specific example, Japanese Patent Laid-Open No. 2-542
There is one disclosed in Japanese Patent Laid-Open No. 2. This method is effective in preventing film peeling due to film stress of silicide. However, there is a problem that the heat resistance and the corrosion resistance are further lower than those mentioned above.

A nitride film is provided as an intermediate layer. Specific examples include those described in Japanese Patent Laid-Open No. 64-25475. This technique prevents the silicide metal from penetrating deep into the polysilicon layer and causing a breakdown voltage failure, and the upper silicide layer and the lower polysilicon layer are electrically connected by using polysilicon for the sidewalls. To do. The above-mentioned Japanese Patent Laid-Open No. 64-25475 does not describe the prevention of impurity diffusion, but the nitride film has the same effect as above, and is particularly effective as a B diffusion barrier. However, the diffusion of impurities from the sidewalls or through the sidewalls poses a similar problem. Also,
The transistor characteristics also differ depending on whether or not the sidewall is an insulator. Further, the nitrided layer has low adhesion to the silicide as well as the oxide layer, so that there is a risk of film peeling.

A method in which B atoms having a predetermined concentration or higher are introduced into a silicide without a concentration gradient. This technique is based on the principle that diffusion does not occur because there is no concentration gradient. As a specific example, there is one described in JP-A-5-183117.

Nitrogen atoms or indium atoms are introduced into the silicide and / or polysilicon by ion implantation or the like. Although details of the mechanism of suppressing the impurity diffusion by this method are unknown, it is said that nitrogen atoms or nitrides suppress the diffusion of gate impurities, especially B.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and the gate formed by silicide does not impair the adhesion of the silicide (polycide) layer, the corrosion resistance, and the low resistance of the gate. It is intended to suppress the sucking out of impurities (and simultaneously suppress mutual diffusion). That is, the object of the present invention is to oxidize and / or nitride only the grain boundaries of the polysilicon layer in the vicinity of the interface between the polysilicon layer forming the gate electrode and the refractory metal silicide layer (hereinafter abbreviated as grain boundary treatment). The gate depletion (particularly B) is suppressed by suppressing the draining of the gate impurities (particularly B) from the polysilicon layer without lowering the resistance and impairing the adhesion between the polysilicon layer and the refractory metal silicide layer. It is intended to prevent the gate impurities from being sucked out and / or interdiffused. A further object of the present invention is to add a small amount of a silicide material to promote grain boundary treatment and improve the adhesion of the silicide.

[0011]

A MOS semiconductor device having a polycide gate according to claim 1 has a polysilicon layer 3 forming a gate electrode and a refractory metal silicide layer 5 as shown in FIG. (WSix, TiSix, Mo
A grain boundary 4 of the polysilicon layer 3 (grain boundary portion of the polysilicon layer surface) near the interface of (Six, etc.) is oxidized, nitrided or oxynitrided (for example, exists as an oxynitride). . In FIG. 1, 1 is a silicon substrate and 2 is a gate oxide film.

A polycide gate MOS according to claim 2.
In the semiconductor device, as shown in FIG. 2, the grain boundary 4 of the polysilicon layer 3 in the vicinity of the interface between the polysilicon layer 3 forming the gate electrode and the refractory metal silicide layer 5 is oxide silicide, nitride silicide or oxynitride silicide. It is characterized in that. In addition, the grain boundary 4 in FIG.
It is an oxynitride silicide or a stack of oxynitride silicide and silicide.

A method of manufacturing a semiconductor device according to a third aspect is for manufacturing the MOS semiconductor device according to the first aspect, wherein a refractory metal is formed on the polysilicon layer 3 forming the gate electrode. Silicide layer 5 (WSix, Ti
Before laminating (Six, MoSix, etc.), as shown in FIG. 3, a wet etching step of the surface of the polysilicon layer 3, an oxidation and / or nitriding step, and an insulating film etchback step are performed in this order. . That is, FIG.
6A, the surface of the polysilicon layer 3 is wet-etched (the two-dot chain line shows the state before etching), and the surface of the polysilicon layer 3 is oxidized and oxidized as shown in FIG. A silicon nitride film 31 is formed, a part of the silicon oxynitride film 31 is etched back as shown in (c), and then a silicide layer 5 is laminated.

A method of manufacturing a semiconductor device according to a fourth aspect is for manufacturing the MOS semiconductor device according to the second aspect, wherein a refractory metal silicide layer is formed on the polysilicon layer forming the gate electrode. 5 (WSix, TiSi
x, MoSix, etc.), a wet etching step (not shown) of the polysilicon surface, and a step of depositing a very small amount of silicide material 41 (silicide or metal for silicide) as shown in FIG. 4A. The oxidation and / or nitridation process step as shown in FIG. 4B and the insulating film etchback step as shown in FIG. 4C are performed in this order. In FIG. 4, 42 is an oxynitride silicide and 43 is an oxynitride film.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein, when the MOS semiconductor device according to the fourth aspect is manufactured, a small amount of a silicide material deposited before an oxidation and / or nitriding treatment step is heat resistant. It is characterized in that a high melting point metal or a high melting point metal silicide is used.

[0016]

In the polycide gate MOS semiconductor device according to claim 1, the gate impurities introduced into the polysilicon layer 3 by a method such as ion implantation are diffused and activated in the polysilicon layer 3 by a subsequent heat treatment step. However, it is considered that most of the gate impurities diffuse in the grain boundaries of the polysilicon layer 3. Therefore, in order to suppress diffusion of impurities into the upper silicide layer 5 (sucking of impurities by the silicide layer 5), this grain boundary control is important. A silicon oxide film, a silicon nitride film, or a silicon oxynitride film has a lower diffusion coefficient for impurities introduced into a gate than silicon, and thus can serve as a diffusion barrier. However, if such an insulating film is formed on the entire polysilicon surface, the silicide layer 5
In addition to being unable to be electrically connected with, there is a concern that film peeling may occur due to a decrease in adhesion. Therefore, in order to suppress the diffusion of impurities from the polysilicon layer 3 (impurity absorption by the silicide layer 5) without impairing the adhesion of the silicide, in the present invention, the polysilicon particles near the interface between the silicide layer 5 and the polysilicon layer 3 are suppressed. This is solved by controlling the field 4 (the above-mentioned oxidation treatment and / or nitriding treatment).

Generally, the adhesion between the refractory metal silicide layer deposited on the surface of the polysilicon layer and the underlying polysilicon layer enhances the silicidation of the silicide due to the reaction with the polysilicon in the subsequent heat treatment step. It can be improved. However, when a refractory metal is used instead of refractory metal silicide, the silicidation reaction becomes too vigorous in the heat treatment process, and stress such as stress and spikes are generated, which damages the polysilicon layer and the gate oxide film. There is a fear. Considering the reliability of the MOS structure, it can be said that it is advantageous to use the refractory metal silicide.

In the polycide gate MOS semiconductor device of the second aspect, since the oxidized and / or nitrided portion of the grain boundary 4 is larger than that of the semiconductor device of the first aspect, the effect of preventing impurity diffusion is increased. The shift of the threshold voltage can be reduced (the depletion suppression effect can be improved).

In the method of manufacturing a semiconductor device according to the third aspect, the surface of the polysilicon layer 3 is oxidized and / or nitrided in the oxidation and / or nitriding treatment step, but the grain boundary 4 is larger than the crystal grain. The reaction is fast. Therefore, after that, the insulating film is removed by etching back (usually dry etching). However, by controlling the etching rate to prevent overetching, the grain boundaries 4 on the surface of the polysilicon layer 3 are selectively removed. The oxidized and / or nitrided portion can be left behind.

Impurities are introduced into the polysilicon layer by ion implantation or other known techniques. This impurity introduction and diffusion are performed before the formation of the silicide layer (that is,
It is better to perform after the formation of the polysilicon layer and before the wet etching). The reason is to prevent impurities from concentrating in the vicinity of the surface of the polysilicon layer, and there is an advantage that it is easy to avoid gate depletion due to sucking.

In the wet etching step, the surface of the polysilicon layer 3 is etched. Since the etching speed of the grain boundary 4 is higher than that of the crystal grain, the groove at the grain boundary portion can be made more prominent. After etching back, it becomes easier to selectively leave the oxidized and / or nitrided portion at the grain boundary portion [FIG. 3, particularly (c)]
]. The wet etching of the grain boundary 4 is Secc.
Also called o etching, as a chemical for etching,
A mixed solution of hydrofluoric acid and an aqueous K ₂ Cr ₂ O ₇ solution or the like is used. In the oxidation and / or nitridation step, the surface of the polysilicon layer is oxidized and / or nitrided, but since the grain boundary portion is not denser than the crystal grains, the speed of these oxidation and / or nitridation is higher than that of the crystal grains. The oxide film also acts as an impurity diffusion barrier, but the nitride film or the nitrided oxide film is more effective in suppressing the extraction of impurities (particularly B). A stoichiometric (stoichiometric composition) nitride film is more difficult to form than an oxide film, but light nitriding of an oxide film is relatively easy. About atom% is sufficient. Further, in the nitridation of the oxide film, nitrogen diffuses in the oxide film and is most likely to be segregated at the interface between the oxide film and the polysilicon layer, and therefore it is extremely easy to leave the nitrided portion of the grain boundary after the etch back.
As described above, oxide film and / or nitride film (particularly nitride film)
Is formed even in a deep part of the grain boundary, so that it can be left at the grain boundary after the insulating film is etched back.

In the method of manufacturing a semiconductor device according to the fourth aspect, the silicide material deposited before the oxidation and / or nitriding process may have an average film thickness of about 10 to 20Å or less. In such cases, the deposited material is in the form of islands rather than layered morphology, which is more like a liquid phase than a solid phase. If the surface of the polysilicon layer 3 is migrated by performing an appropriate heat treatment (a temperature at which silicidation does not occur, for example, about 300 ° C. for a refractory metal material) during or after vapor deposition, the deposited material is A larger number of grains will be retained in the grain boundary groove described above. This heat treatment utilizes the substrate heat treatment during vapor deposition,
Alternatively, heat treatment in the oxidation and / or nitriding step (heat treatment at the time of temperature rise) can be used. The vapor deposition can be performed by a known method such as a resistance heating method or a sputtering method. When the oxidation and / or nitriding treatment is performed in the above-mentioned state, silicidation occurs in the retention portion of the silicide material, and at the same time, the oxidation and / or nitriding is promoted. Therefore, oxidation and / or nitridation is promoted in the grain boundary portion more than that in the other portion, and the area becomes wider than that in the manufacturing method according to claim 3. In the next insulating film etch back step, the oxide film, nitride film and silicide on the surface are removed to obtain a desired polysilicon surface.

[0023]

Next, embodiments of the present invention will be described. Example 1 First, a MOS semiconductor element formation region in which pre-processes necessary for producing wells, element isolation, substrate channel doping, gate oxide film formation, and the like of MOS semiconductor elements and CMOS semiconductor elements, and integrated circuits thereof were performed. A 2000 Å polysilicon film was formed. Next, B implantation (4E15 / cm ² ) is performed on the PMOS formation portion and As implantation (4E15 / cm ² ) is performed on the NMOS formation portion by an ion implantation method, and the process is performed at 850
A heat treatment was performed at ℃ for about 20 minutes. At this point, SIMS analysis of the impurity distribution in the polysilicon confirmed that the impurities were diffused almost uniformly, although the concentration was slightly higher in the projected range. Further, it was observed from the RHEED pattern that the damage of the polysilicon film at the time of implantation was almost recovered and that the polysilicon film was recrystallized (polysilicon).

Next, grain boundary etching was performed by sufficiently diluting a mixed solution of hydrofluoric acid and an aqueous K ₂ Cr ₂ O ₇ solution. Next, Ti was deposited by an average film thickness of about 15 Å by the resistance heating method (calculated by rate × time). For comparison, a sample without depot was also prepared. Next, 1 in oxygen atmosphere
RTA (RTO) treatment was performed at 100 ° C. for about 10 seconds. The thickness of the surface oxide film at this point is 50Å for both
There was no significant difference. However, this film thickness is an average value and does not reflect the oxide film thickness (oxidation depth) at the grain boundary portion. Next, RTA (RTN) at 950 ° C for 60 seconds or less in an ammonia atmosphere
Treated. SIMS of surface oxynitride film at this point
As a result of analysis, the nitrogen concentration at the interface between the oxide film and the polysilicon was about 5 atom%, and the nitrogen concentration in the oxide film was about a fraction of the value.

Next, the above-described oxynitride film was subjected to an etch-back process with less over-etching by a known dry etching technique. The etching treatment conditions were determined by fixing a condition other than the etching time and performing a series of experiments (a series of MOS manufacturing steps). Next, a silicide WSix was formed into a film of about 1000 liters. Then C
An oxide film of about 500 to 1000 Å was formed by using the VD method. This oxide film is for preventing abnormal oxidation of WSix in the heat treatment in the subsequent steps (abnormal oxidation causes defective initial breakdown voltage, etc.). The heat treatment for ensuring the adhesion between the WSix film and the polysilicon film is performed in several thermal processes in later steps (diffusion layer activation processing and thermal history during high temperature oxide film deposition for sidewalls). I used it instead. Therefore, no special treatment was applied. Thereafter, processing such as gate pattern formation and diffusion layer formation was performed.

NMOS and PM manufactured as described above
As a result of evaluating the threshold voltage and the flat band voltage of OS, it was possible to confirm the respective impurity diffusion suppressing effects. The processing conditions according to the present invention are shown in [Table 1], and the processing results according to the present invention and the conventional method are shown in [Table 2].

[0027]

[Table 1]

[0028]

[Table 2] [Note] (1) ΔVfb [V]: Shift amount of flat band voltage in the case without silicide (2) ΔVth [V]: Shift amount of threshold voltage in the case without silicide (3) Silicide The sample without is equivalent to one without gate depletion. (4) The numerical values in the table are the difference between the average values of 50 points in the wafer plane.

[0029]

As is apparent from the above description, according to the present invention, diffusion of impurities (suction of impurities) from a polysilicon layer to a silicide layer is suppressed, mutual diffusion is almost eliminated, and a polycide gate is manufactured. It is possible to avoid the problem of depletion of the gate. Therefore, there is an effect that the device can be easily designed and a device that does not hinder high-speed operation can be manufactured.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a main part of a semiconductor device according to claim 1.

FIG. 2 is a cross-sectional view showing a main part of a semiconductor device according to claim 2.

FIG. 3 is an explanatory view showing the manufacturing process of the semiconductor device according to claim 3;

FIG. 4 is an explanatory view showing the manufacturing process of the semiconductor device according to the fourth aspect.

[Explanation of symbols]

 1 Silicon Substrate 2 Gate Oxide Film 3 Polysilicon Layer 4 Grain Boundary (Grain Boundary Part of Polysilicon Layer Surface) 5 Silicide Layer 31 Silicon Oxynitride 41 Silicide Material 42 Oxynitride Silicide 43 Oxidation Nitride Film

Claims (5)

[Claims] 1. In a MOS semiconductor device having a polycide gate, a grain boundary of the polysilicon layer in the vicinity of the interface between the polysilicon layer forming the gate electrode and the refractory metal silicide layer is oxidized and / or nitrided. A polycide gate MOS semiconductor device characterized in that 2. In a MOS semiconductor device having a polycide gate, the grain boundary of the polysilicon layer near the interface between the polysilicon layer forming the gate electrode and the refractory metal silicide layer is oxide silicide, nitride silicide or oxynitride silicide. And a polycide gate MOS semiconductor device. 3. When forming a polycide gate in the MOS semiconductor device according to claim 1, before the step of forming the refractory metal silicide layer on the polysilicon layer forming the gate electrode, the polysilicon surface is formed. A method of manufacturing a semiconductor device, which comprises sequentially performing a wet etch step, an oxidation and / or nitriding step, and an insulating film etch back step. 4. When forming a polycide gate in the MOS semiconductor device according to claim 2, before the step of forming the refractory metal silicide layer on the polysilicon layer forming the gate electrode, the polysilicon surface is formed. A method of manufacturing a semiconductor device, which comprises performing a wet etching step, a step of depositing an extremely small amount of a silicide material, an oxidation and / or nitriding step, and an insulating film etch back step in this order. 5. A semiconductor characterized by using refractory metal or refractory metal silicide as a silicide material to be deposited before an oxidation and / or nitriding process in manufacturing the MOS semiconductor device according to claim 4. Device manufacturing method.