JPH08274585A - Clock transfer circuit and video camera device having the same - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a clock transfer circuit that facilitates clock phase management. [Configuration] Data DAa synchronized with clock CLK1 is set to D
The flip-flop 2 latches with the clock CLK1 and supplies its output data DAb to the memory means 10. In the memory means 10, the clocks CLK1, CLK
Depending on the frequency ratio of 2, thinning processing and double reading processing,
The data DAd synchronized with the clock CLK2 is obtained. The writing and reading operations of the memory means 10 are performed based on the address signals WAD and RAD generated by the W / R control unit 13. The output data DAd of the memory means 10 is latched by the D flip-flop 3 with the clock CLK2 and the data DAe synchronized with the clock CLK2 is obtained at the output terminal 4. In this case, the data DAd can be latched almost at the center of each bit data switching point, and there is no portion where the timing for transferring the data becomes strict.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock transfer circuit and a video camera device having the same. More specifically, by interposing a memory means that can perform writing and reading independently between two latch means that operate with clocks of different frequencies, the clock loading that facilitates the phase management of the clock is performed. The present invention relates to a replacement circuit and a video camera device having the replacement circuit.

[0002]

2. Description of the Related Art Conventionally, there has been proposed a clock transfer circuit for converting digital data synchronized with a first clock into digital data synchronized with a second clock.
FIG. 6 shows a configuration example of a conventional clock transfer circuit. The clock transfer circuit has D flip-flops 2 and 3 which form a latch means.

Clock CLK1 supplied to input terminal 1
The digital data DAa synchronized with is supplied to the data terminal D of the D flip-flop 2. The clock CLK1 is supplied to the clock terminal of the D flip-flop 2. Further, the digital data DAb obtained at the output terminal Q of the D flip-flop 2 is supplied to the data terminal D of the D flip-flop 3. The clock CLK2 is supplied to the clock terminal of the D flip-flop 3. Then, the digital data DAc obtained at the output terminal Q of the D flip-flop 3 and synchronized with the clock CLK2 is led to the output terminal 4.

An example of operation when the clock CLK1 is 18 MHz and the clock CLK2 is 13.5 MHz will be described. In this case, since the digital data DAa shown in FIG. 7A is latched by the D flip-flop 2 at the clock CLK1 shown in FIG. 7B, the digital data DAb is obtained at the output terminal Q of the D flip-flop 2 as shown in FIG. 7C. . Since this digital data DAb is latched by the D flip-flop 3 at the clock CLK2 shown in FIG. 7D, the digital data DAc is obtained at the output terminal Q of the D flip-flop 3 as shown in FIG. 7E.

[0005]

Generally, in order to properly latch the digital data supplied to the data terminal D in the D flip-flop, it is necessary to satisfy the setup time and hold time of the D flip-flop. Here, the setup time is the data terminal D
This is the minimum margin time from the change of the digital data supplied to the device to the supply of the clock to the clock terminal. The hold time is the minimum margin time from the supply of the clock to the clock terminal to the change of the digital data supplied to the data terminal D. The setup time and the hold time are both times required for the flip-flop to reliably respond.

In the conventional clock transfer circuit of FIG. 6,
Since the data is directly transferred from the D flip-flop 2 to the D flip-flop 3, there is a part where the timing for transferring the data becomes very strict from the viewpoint of the setup time and the hold time of the D flip-flop 3. For example, when the clocks CLK1 and CLK2 have a phase relationship as shown in FIGS.
The timing of 1 is the strictest from the viewpoint of the hold time, and the timing of t2 is the strictest from the viewpoint of the setup time. Therefore, in the conventional clock transfer circuit, data transfer cannot be performed properly unless the phase management of the clocks CLK1 and CLK2 is strict.

In view of this, the present invention provides a clock transfer circuit which facilitates clock phase management and a video camera device having the same.

[0008]

A clock transfer circuit according to the present invention comprises first latch means for latching first digital data synchronized with a first clock in synchronization with a first clock, and The output data of the first latch means is supplied as write data, and the memory means capable of writing and reading independently of each other and the output data of the memory means are latched in synchronization with the second clock. The second clock synchronized with the second clock
Latching means for obtaining the digital data of, a first counter for cyclically counting the first clock, and a second counter for cyclically counting the second clock.
And the output data of the first latch means are sequentially written to the address of the memory means according to the output value of the first counter and the data of the memory means according to the output value of the second counter. And a memory control means for controlling the reading.

The video camera device according to the present invention has a clock transfer circuit. Then, the clock transfer circuit has a first clock synchronized with the first clock.
A first latching means for latching the digital video data of 1) in synchronization with a first clock, and output data of the first latching means are supplied as write data, and writing and reading are performed independently of each other. And a memory means capable of performing the second output data from the memory means.
Second latch means for obtaining the second digital video data synchronized with the second clock by latching in synchronization with the second clock, the first counter for cyclically counting the first clock, and the second A second counter that cyclically counts the clock of the first counter, and the output data of the first latch means are sequentially written to the address of the memory means according to the output value of the first counter, and at the same time, the output value of the second counter is set. And memory control means for controlling to sequentially read data from the corresponding address of the memory means.

[0010]

The first latch means latches the first digital data synchronized with the first clock in synchronization with the first clock. The memory means sequentially writes the output data of the first latch means in synchronization with the first clock,
The data is read in synchronization with the clock of. The second latch means outputs the output data of the memory means to the second data.
Latch in synchronization with the clock of. Thus, the second digital data synchronized with the second clock can be obtained from the second latch means.

The first counter cyclically counts the first clock, and the second counter cyclically counts the second clock. Then, the memory control means sequentially writes the output data of the first latch means to the address of the memory means according to the output value of the first counter, and from the address of the memory means according to the output value of the second counter. The data is controlled to be read sequentially. Thereby, in the memory means, the first clock and the second clock
Depending on the clock frequency ratio, the data thinning process or double reading process is performed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the main structure of the video camera device 100. Digital video data DAf output from an image pickup signal processing unit (not shown) synchronized with the clock CLK1 is supplied to the low pass filter 6 for band limitation. The band-limited digital video data DAa output from the low-pass filter 6 is supplied to the clock transfer circuit 7, and a clock transfer process is performed from this video data DAa to obtain digital video data DAe synchronized with the clock CLK2. . Then, the video data DA output from the clock transfer circuit 7
e is led to the output terminal 8.

The operations of the low pass filter 6 and the clock transfer circuit 7 described above are controlled by the system controller 9. The system controller 9 has a clock CLK1.
And CLK2, the frequency information INF of the clock CLK1 and the clock CL2 is supplied. In the low-pass filter 6, the cutoff frequency is set based on the frequency information INF so that the band of the video data DAf is limited to the extent that aliasing distortion does not occur when the clock changing circuit 7 in the subsequent stage performs the clock changing process. It is changed appropriately.

FIG. 2 shows a configuration example of the clock transfer circuit 7. In FIG. 2, parts corresponding to those in FIG. 6 are designated by the same reference numerals. The clock transfer circuit 7 of this example has D flip-flops 2 and 3 which constitute a latch means, and a memory means 10 is interposed between these D flip-flops 2 and 3.

The data terminal D of the D flip-flop 2 is supplied with digital video data DAa synchronized with the clock CLK1 from the input terminal 1, and the system controller 9 supplies the clock CLK1 as a latch clock to the clock terminal. In this case, the bit data of the video data DAa is set to be latched at approximately the center of the switching point.

The output data DAd of the memory means 10 is supplied to the data terminal D of the D flip-flop 3.
The system controller 9 supplies a clock C to the clock terminal.
LK2 is supplied as a latch clock. in this case,
Since the output data DAd of the memory means 10 is synchronized with the clock CLK2 as described later, it is set in the D flip-flop 3 so as to be latched at approximately the center of the switching point of each bit data of the video data DAd. The output data of the D flip-flop 3 is led to the output terminal 4 as digital video data DAe.

The memory means 10 can perform writing and reading independently of each other, and is composed of, for example, a dual port memory. In the memory means 10, data thinning processing or double reading processing is performed according to the frequency ratio of the clocks CLK1 and CLK2.

Here, the clocks CLK1 and CLK2
When the frequency ratio is 4: 3, the memory means 10 equivalently has four unit memory units 101a to 101d and a switch circuit 102 for selecting which of the unit memory units 101a to 101d is to be written. Unit memory unit 101a
The switch circuit 103 is used to select which of the read data is to be read out. In this case, the output data DAb of the D flip-flop 2 is the switching circuit 10
2 is supplied to and written in the unit memory units 101a to 101d through the unit memory units 101a to 101d.
The data read from d is output data DAd of the memory means 10 via the switch circuit 103.

Further, the clock transfer circuit 7 of this example is
A counter 11 for a write address (W address),
A counter 12 for a read address (R address),
It has a write / read controller (W / R controller) 13 for controlling writing and reading of the memory means 10. The clock CLK1 is supplied from the system control unit 9 to the counter 11 and is counted. The system controller 9 supplies the clock CLK2 to the counter 12 for counting.

Here, the clocks CLK1 and CLK2
When the frequency ratio of is m: n (m and n are positive integers),
For example, the counter 11 is an m-ary counter, while the counter 12 is an n-ary counter. As described above, the frequency ratio of the clocks CLK1 and CLK2 is 4: 3.
, The counter 11 has a count output of "0"-
The counter 12 can be composed of a quaternary counter which repeats "3", and the counter 12 can be composed of a ternary counter whose count output is repetition of "0" to "2".

The counters 11 and 12 have a system control unit 9
For example, the reset signal RS is supplied and initialized at the time of power-on. As a result, while the write / read operation is being performed in the memory means 10, the memory means selected based on the write address of the memory means 10 and the count output of the counter 12 are selected based on the count output of the counter 11. The read addresses of 10 are set far enough apart. For example, as described above, when the frequency ratio of the clocks CLK1 and CLK2 is 4: 3, the counter 11 is a quaternary counter, and the counter 12 is a ternary counter, the counter 11,
The 12 count outputs are initialized to "0" and "2" by the reset signal RS, respectively.

The W / R control unit 13 includes counters 11 and 12
Count output is provided. In the W / R control unit 13, the write address signal WAD is formed based on the count output of the counter 11, and the read address signal RAD is formed based on the count output of the counter 12. The address signals WAD and RAD generated by the W / R control unit 13 are supplied to the memory means 10 described above.

In this case, the clocks CLK1 and CLK
When the frequency ratio of 2 is m: n, the W / R control unit 13 performs address signal WAD and RAD so that the memory unit 10 performs data thinning processing or double reading processing.
Is formed.

Here, when m> n, the output data DAb of the D flip-flop 2 is sequentially and repeatedly written to the first to mth addresses of the memory means 10, and
The address signals WAD and RAD are formed so that the data is sequentially and repeatedly read from the n-th address of the first to the m-th addresses of the memory means 10 and the thinned output data DAd is obtained. In this case, n
Since data is not read from addresses other than these addresses, data thinning-out processing may be performed without writing to that address.

For example, clocks CLK1 and CLK2
The frequency ratio of 4: 3 is 4: 3, the first of the memory means 10 is
-Fourth address, that is, unit memory units 101a-1
01d, the output data DAb of the D flip-flop 2 is sequentially and repeatedly written, and the data is sequentially and repeatedly read from the first, second, and fourth addresses of the memory means 10 to obtain the output data DAd. Signals WAD and RAD are formed. In this case, since the data is not read from the third address, the data thinning-out process may be executed without writing to the address.

Although not described above, in the W / R control unit 13, when the count output of the counter 11 is "0", "1", "2", and "3", the first address (unit memory unit 101a) is obtained. ), The second address (unit memory unit 101
b), the write address signal WAD is formed so that the third address (unit memory unit 101c) and the fourth address (unit memory unit 101d) are selected, and the count output of the counter 12 is "0", When it is “1” and “2”, the first address (unit memory unit 101a) and the second address (unit memory unit 101), respectively.
The read address signal RAD is formed so that b) and the fourth address (unit memory unit 101d) are selected.

When m <n, the memory means 1
The output data DAb of the D flip-flop 2 is sequentially and repeatedly written to the first to mth addresses of 0, and n pieces of data are sequentially read from the first to mth addresses of the memory means 10 by the double reading process. The address signals WAD and RAD are formed so as to obtain the output data DAd that is repeatedly read and read twice.

In the above configuration, when the digital video data DAa synchronized with the clock CLK1 is supplied to the input terminal 1, the video data DAa is latched by the D flip-flop 2 in synchronization with the clock CLK1. Then, the output data DAb of the D flip-flop 2
Is supplied to the memory means 10, and the W / R control unit 13 controls writing based on the write address signal WAD formed according to the count output of the counter 11.
In this case, when the frequency ratio of the clocks CLK1 and CLK2 is m: n, the output data DAb of the D flip-flop 2 is sequentially and repeatedly written to the first to mth addresses of the memory means 10.

Further, the W / R control unit 13 controls the reading of the memory means 10 based on the read address signal RAD formed according to the count output of the counter 12. In this case, when the frequency ratio of the clocks CLK1 and CLK2 is m: n and when m> n, the data is sequentially and repeatedly read from n addresses of the first to mth addresses of the memory means 10. Output data DAd which has been thinned out by the above, and when m <n, n pieces of data are sequentially read out repeatedly from the first to mth addresses of the memory means 10 by the double reading processing. Output data DAd that has been read once is obtained. Here, since the counter 12 counts the clock CLK2 and the W / R control unit 13 forms the read address signal RAD according to the count output of the counter 12, the output data DAd of the memory means 10 becomes the clock CLK2. It will be synchronized.

The output data DAd of the memory means 10 is latched by the D flip-flop 3 in synchronization with the clock CLK2. In this case, the output data DAd is synchronized with the clock CLK2 as described above, and is latched in the D flip-flop 3 at approximately the center of the switching point of each bit data of the output data DAd. The output data of the D flip-flop 3 becomes synchronized with the clock CLK2, and this is obtained at the output terminal 4 as digital video data DAe. Thus, in the clock transfer circuit 7 of FIG. 2, when the digital data DAa synchronized with the clock CLK1 is supplied to the input terminal 1, the digital video data DAe synchronized with the clock CLK2 is obtained at the output terminal 4.

When the frequency ratio of the clock CLK1 and the clock CLK2 is 4: 3, for example, the clock CLK1 is 18 MHz and the clock CLK2 is 13.5.
An operation example in the case of MHz will be briefly described. In this case, the digital video data DAa shown in FIG. 3A is transferred to the D flip-flop 2 by the clock CLK shown in FIG. 3B.
Since it is latched at 1, the output data DAb of the D flip-flop 2 is obtained as shown in FIG. 3C. Then, this output data DAb is the write address signal W formed according to the count output of the counter 11 shown in FIG. 3D.
Based on the AD, it is sequentially and repeatedly written in the first to fourth addresses of the memory means 10, that is, the unit memory units 101a to 101d, as shown in FIG. 3E.

Further, based on the read address signal RAD formed according to the count output of the counter 12 shown in FIG. 3G in which the clock CLK2 shown in FIG. 3F is counted, the first, second and fourth memory means 10 are provided. Address, and therefore unit memory sections 101a, 101b and 10
Data is sequentially read from 1d as output data DAd as shown in FIG. 3H. Then, the output data DAd of the memory means 10 is supplied to the D flip-flop 3,
In this D flip-flop 3, the bit data of the output data DAd is latched at the center of the switching point, so that the output terminal 4 receives the clock CLK as shown in FIG. 3I.
The digital video data DAe synchronized with 2 is obtained.

In this way, the clock transfer circuit 7 of this example is
Then, the memory means 10 is interposed between the D flip-flops 2 and 3, and the output data DA of the memory means 10 is
d becomes synchronous with the clock CLK2, and D
In the flip-flop 3, the bit data of the output data DAd is latched at the approximate center of the switching point. Therefore, there is no part where the timing for transferring the data becomes strict in relation to the setup time and the hold time of the D flip-flop 3, and the phase management of the clocks CLK1 and CLK2 can be loosened as compared with the conventional example. .

Further, in the clock transfer circuit 7 of this embodiment, for example, while the power is turned on, the reset signal RS is supplied to the counters 11 and 12 for initialization, and while the memory means 10 is performing the write / read operation. Since the write address and the read address of the memory means 10 are sufficiently separated from each other, it is possible to reliably avoid a malfunction such as the read overtaking the write in the memory means 10.

Although the example of FIG. 2 shows an equivalent circuit of the memory means 10 when the frequency ratio of the clocks CLK1 and CLK2 is 4: 3, the frequency ratio of the clocks CLK1 and CLK2 is 5: 3. , The memory means 10 is equivalent to five unit memory units 104a to 104e and unit memory units 104a to 104e as shown in FIG.
Switch circuit 1 for selecting which to write to 04e
05 and a switch circuit 106 for selecting which of the unit memory units 104a to 104e is read. In this case, the output data DAb of the D flip-flop 2 is supplied to and written in the unit memory units 104a to 104e via the switch circuit 105, and
The data read from the unit memory units 104a to 104e is used as the output data DAd of the memory means 10 via the switch circuit 106.

Further, as described above, when the frequency ratio of the clocks CLK1 and CLK2 is 5: 3, the counter 11 can be constituted by a quinary counter whose count output is a repetition of "0" to "4", and the counter 12 Can be composed of a ternary counter whose count output is a repetition of "0" to "2". In this case, the count outputs of the counters 11 and 12 are, for example, “0” and “2” by the reset signal RS.
Is initialized to.

When the frequency ratio of the clocks CLK1 and CLK2 is 5: 3 as described above, the W / R control unit 13 has the first to fifth addresses of the memory means 10, that is, the unit memory units 104a to 104a. The output data DAb of the D flip-flop 2 is sequentially written into 104e, and the data is sequentially read from the first, second and fourth addresses of the memory means 10 to obtain the output data DAd. Signal WAD,
RAD is formed. In this case, since the data is not read from the third and fifth addresses, the data thinning-out process may be executed without writing to the address.

Although not described above, in the W / R control unit 13, the count output of the counter 11 is "0", "1", "2",
When it is “3” and “4”, the first address (unit memory unit 104a), the second address (unit memory unit 104b), and the third address (unit memory unit 104), respectively.
c), the write address signal WAD is formed so that the fourth address (unit memory unit 104d) and the fifth address (unit memory unit 104e) are selected, and the count output of the counter 12 is "0", When it is "1" and "2", the first address (unit memory unit 104a) and the second address (unit memory unit 104a), respectively.
The read address signal RAD is formed so that b) and the fourth address (unit memory unit 104d) are selected.

When the frequency ratio of the clock CLK1 and the clock CLK2 is 5: 3, for example, the clock CLK1 is 22.5 MHz and the clock CLK2 is 1.
An operation example in the case of 3.5 MHz will be briefly described. In this case, the digital video data DAa shown in FIG. 5A is transferred to the D flip-flop 2 at the clock C shown in FIG. 5B.
Since it is latched by LK1, the output data DAb of the D flip-flop 2 is obtained as shown in FIG. 5C. The output data DAb is the counter 1 shown in FIG. 5D.
Based on the write address signal WAD formed according to the count output of 1, the first to fifth addresses of the memory means 10, and hence the unit memory units 104a to 104e, are shown in FIG.
As shown in E, the data is sequentially and repeatedly written.

Also, based on the read address signal RAD formed in response to the output of the counter 12 shown in FIG. 5G in which the clock CLK2 shown in FIG. 5F is counted, the first, second and fourth addresses of the memory means 10 are read. Therefore, as shown in FIG. 5H, the data is sequentially read from the unit memory units 104a, 104b, and 104d and becomes the output data DAd. Then, the output data DAd of the memory means 10 is supplied to the D flip-flop 3, and the D flip-flop 3 latches at about the center of the switching point of each bit data of the output data DAd. As shown in, the digital video data DAe synchronized with the clock CLK2 is obtained.

In the above-mentioned embodiment, the clock changing process of the digital video data is described, but it is needless to say that the clock changing process of the audio data can be performed with the same configuration.

[0043]

According to the present invention, since the memory means capable of performing writing and reading independently of each other is interposed between the two latch means operating with clocks of different frequencies, the second latch means is not provided. It is possible to latch at about the center of the switching point of each bit data of the output data of the memory means, there is no part where the timing for transferring the data becomes strict, and the phase management of the first and second clocks can be loosened. Further, by initializing the first and second counters so that the write address and the read address of the memory means are separated from each other, it is possible to reliably avoid a malfunction such as the read overtaking the write in the memory means. Further, in a video camera device provided with a low-pass filter for suppressing the occurrence of aliasing distortion in the preceding stage of the clock transfer circuit, the cut-off frequency of the low-pass filter is changed and controlled based on the frequencies of the first and second clocks. As a result, it is possible to favorably suppress the occurrence of aliasing distortion without limiting the transitional band.

[Brief description of drawings]

FIG. 1 is a system diagram showing a main configuration of a video camera device according to an embodiment.

FIG. 2 is a system diagram showing a configuration of a clock transfer circuit according to an embodiment.

FIG. 3 shows that the frequency ratio of clocks CLK1 and CLK2 is 4:
6 is a timing chart showing the operation of the clock handoff circuit in the case of 3.

FIG. 4 is a system diagram showing a configuration of a clock transfer circuit according to an embodiment.

FIG. 5 shows that the frequency ratio of clocks CLK1 and CLK2 is 5:
6 is a timing chart showing the operation of the clock handoff circuit in the case of 3.

FIG. 6 is a system diagram showing a configuration example of a conventional clock transfer circuit.

FIG. 7 is a timing chart showing the operation of a conventional clock handoff circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 input terminal 2, 3 D flip-flop 4, 8 output terminal 6 low pass filter 7 clock transfer circuit 9 system control unit 10 memory means 11 counter for write address 12 counter for read address 13 write / read control unit 100 video camera apparatus

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H04L 7/00 H04N 5/04 Z H04N 5/04 5/232 Z 5/232 G06F 1/04 340A

Claims (5)

[Claims] 1. A clock transfer circuit for converting first digital data synchronized with a first clock into second digital data synchronized with a second clock, wherein the first digital data is converted into the first digital data. First latching means for latching in synchronization with a clock; memory means for supplying output data of the first latching means as write data and capable of writing and reading independently of each other; Second latch means for obtaining the second digital data by latching output data of the means in synchronization with the second clock; and first latch for cyclically counting the first clock.
And a second counter that cyclically counts the second clock described above.
And the output data of the first latch means are sequentially written to the address of the memory means corresponding to the output value of the first counter and the memory means of the memory means according to the output value of the second counter. A clock transfer circuit, comprising: a memory control unit that controls to sequentially read data from an address. 2. The clock transfer according to claim 1, further comprising means for initializing the first counter and the second counter so that a write address and a read address of the memory means are separated from each other. circuit. 3. The frequency of the second clock is the first frequency.
2. The clock transfer circuit according to claim 1, wherein the data thinning process is performed by the write and read operations with respect to the memory means at a frequency lower than the clock frequency. 4. A video camera device having a clock transfer circuit for converting first digital data synchronized with a first clock into second digital data synchronized with a second clock, wherein the clock transfer circuit comprises: , First latch means for latching the first digital data in synchronization with the first clock, and output data of the first latch means are supplied as write data, and write and read are independent of each other. Memory means that can be done by
Second latch means for obtaining the second digital data by latching the output data of the memory means in synchronization with the second clock, and a first counter for cyclically counting the first clock. And a second counter that cyclically counts the second clock, and sequentially writes the output data of the first latch means to an address of the memory means according to the output value of the first counter, A video camera device, comprising: memory control means for controlling to sequentially read data from an address of the memory means according to an output value of the second counter. 5. A low-pass filter for suppressing the generation of aliasing distortion is provided in the preceding stage of the clock hand-over circuit, and the cut-off frequency of the low-pass filter is changed and controlled based on the frequencies of the first and second clocks. The video camera device according to claim 4, wherein