JPH0827646B2 - Sequence Controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a sequence controller that cyclically executes a sequence and that is capable of performing interrupt processing when an interrupt factor occurs.

BACKGROUND ART There are two types of programmable sequencers: step-by-step type, which performs logical operations based on a sequence program each time an external input signal is received, and cyclic type, which executes logical operations based on a sequence program in synchronization with a timing signal regardless of the arrival of an input signal. Step-by-step type is used only in devices with a relatively small number of inputs and outputs, and therefore functions such as interrupt processing are rarely required.

In the case of cyclic type, the time required to execute one cycle of a sequence program depends on the length of the sequence program, but recently there are sequence programs that take more than 100 milliseconds.
In such a system, each step in the sequence program is executed only once every 100 milliseconds. However, depending on the input signal, for example, if a signal indicating the occurrence of an abnormality is received, it may not be possible to wait until the next scanning to process the abnormality. An interrupt processing function is required to handle such cases.

However, when the number of input and output points increases, the number of input signals requiring interrupt processing can reach several tens of points.

In such a case, if it takes too much time to analyze which interrupt signal has been received, there is a risk that the response will be delayed even if an interrupt request signal has been received.

In addition, the Japanese Utility Model Laid-Open Publication No. 1982 is known to have an interrupt processing function.
Those disclosed in Japanese Patent Application Laid-Open No. 62-145329 are known.

DISCLOSURE OF THE INVENTION The present invention has been made in view of the above points, and its main object is to provide a sequence controller that can analyze an interrupt in a short time.

Another object of the present invention is to provide a sequence controller that allows relatively free setting of the input terminal for a signal that requests an interrupt.

The present invention comprises a program storage means for storing a sequence program, a calculation processing means divided into a plurality of blocks, at least one of which is further divided into a plurality of groups, each of which is provided with a plurality of external signal input terminals and a timing signal generating section for generating timing signals, and which performs logical operations on a plurality of signals including external signals input from the external signal input terminals in accordance with instructions of the sequence program read from the program storage means, in synchronization with the timing signals;
The programmable sequence controller has an output means for outputting a control signal according to the calculation result of the calculation processing means, and is characterized by the following configuration.

That is, the system has first signal generating means for outputting a first signal when a factor requiring interrupt processing occurs in a group, second signal generating means for outputting a second signal when any one of the blocks is outputting the first signal, second signal generating and transmitting means for transmitting the fact to the arithmetic processing means when the second signal is output in any of the blocks, and accessing means for sequentially accessing the first signal generating means belonging to a block when the arithmetic processing means is notified by the second signal generating and transmitting means that the second signal has been output, and for sequentially accessing the first signal generating means belonging to that block when the arithmetic processing means finds a block from which the second signal is output, and is configured to identify the group outputting the first signal.

The timing signal generating section is composed of a program counter which outputs a memory address signal in synchronization with the timing signal generated by the timing signal generating section, and the arithmetic processing means can be configured to perform logical operations on a plurality of signals, including an external signal taken in from an external signal input terminal, in relation to the memory address signal and in accordance with instructions from a sequence program read from the program storage means.

The first signal generating means can be configured to output a first signal when a signal is input to a specific terminal of the external signal input terminal.

For this purpose, a designation means can be provided for designating a specific terminal of the external signal input terminals as an interrupt signal input terminal. This designation means can designate all of the external signal input terminals in a specific group as interrupt signal input terminals, or can designate a specific terminal within the group as an interrupt signal input terminal.

In addition to signals input to external signal input terminals, signals generated within a group can also be treated as interrupt signals.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a sequence controller according to the present invention.

FIG. 2 is a circuit diagram of the main part of the sequence controller shown in FIG.

FIG. 3 shows the order in which the gates of the interrupt status register and data status register shown in FIG. 2 are opened.

FIG. 4 is a diagram showing the setting state of the flip-flops constituting the designation means shown in FIG.

FIG. 5 is a diagram showing the signal state of each bit obtained when the gate of the interrupt status register shown in FIG. 2 is opened.

FIG. 6 is a flowchart showing the operation of the controller of the present invention.

FIG. 7 is a diagram showing more detailed steps of step St4 shown in FIG.

FIG. 8 is a circuit diagram showing a modified embodiment of the present invention.

FIG. 9 is a circuit diagram showing yet another modified embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION The sequence controller, generally designated by 1, is composed of a basic unit 2 and multiple (two in the figure) input/output interface blocks 3a and 3b. The input/output interface blocks 3a and 3b are also called expansion units for the basic unit 2, and are configured so that a number of units corresponding to the number of input/output points can be connected to the basic unit 2 within a certain limit.

The basic unit 2 includes a central processing unit 21 as a processing means and a program memory as a program storage means.
The central processing unit 21 further comprises a program counter 21a, a processing unit 21b, and an overall control unit 21c.
and an input/output control unit 21d. A user's sequence program is stored in the program memory 22. The program counter 21a generates a timing signal at a fixed cycle and outputs a memory address signal in synchronization with this timing signal.
21b executes the blocks 3a and 3b according to the instruction in the address specified by the memory address signal from the program counter 21a in the sequence program in the program memory 22.
The input/output control unit 21d takes in signals from the blocks 3a and 3b to the central processing unit 21 and outputs signals from the central processing unit 21 to the blocks 3a and 3b.
The overall control unit 21c has a built-in system memory and controls the overall central processing unit 21. Specifically, for example, it takes in start/stop inputs for the entire sequence controller 1 and controls the program counter 21.
It also receives input/output interrupt requests, which are urgent processing requests from the blocks 3a and 3b, and issues commands to execute interrupt processing such as analyzing the cause and changing the content of the processing.

The block 3a is composed of input modules Ia1 and Ia2 and output modules Oa1 and Oa2, and the block 3b is composed of input modules Ib1, Ib2, and Ib3 and output module Ob1.
Each of the output modules Oa1 to Ob1 has an external signal input terminal indicated by t1 to tn. The input modules Ia1 to Ib3 convert the voltage level of the signal input to these terminals to a constant value, and when a signal is input, have the function of latching it so that it is known that a signal has been input until the next time the input signal of that terminal is accessed. Each of the output modules Oa1 to Ob1 also has a signal output terminal indicated by t1 to tn. The output modules Oa1 to Ob1 convert the signals output from these terminals to the required voltage form (DC or AC) at the required voltage level, and have the function of latching it until the next time the output signal of that terminal is accessed. Each of the circuits equipped with a latch and signal conversion function is ia.
From the above, the signal input terminals are divided into a plurality of blocks shown as blocks 3a and 3b, and at least one of the blocks
It can be seen that the first (both in the embodiment) are divided into a plurality of groups indicated by Ia1 to Ib3, and that a plurality of units are provided in each group.

The input/output control unit 21d and the blocks 3a and 3b are connected by an address bus B
a, Baa, Bab, data buses Bd, Bda, Bdb, and interrupt signal transmission lines Bi, Bia, Bib.

If the interrupt signal transmission lines Bi, Bia, and Bib are to transmit only interrupt signals, it is sufficient for them to transmit only 1-bit information.

The bidirectional bus driver DaD is located between the data buses Bda and Bdb.
b are provided, and the gates are configured to open and close in response to gate signals from the central processing unit 21. Address buses Baa and Bab are also provided with address decoders Ada and Adb. The outputs of these address decoders Ada and Adb are input to data output switching units Ca1, Ca2, Cb1 and Cb2 shown in FIG. 2. Ca1, Ca2, Cb1 and Cb2 are respectively connected to interrupt status registers Sia and Sib and data status register Sd.
a,It is configured to send a signal to Sdb.

When the central processing unit 21 receives information requiring interrupt processing via the interrupt signal transmission line Bi, it controls the address decoders Ada and Adb to switch the data output switches Ca1, Ca2, Cb1, and Cb2 in the order shown in Figure 3. That is, first, it opens the gate of the interrupt status register Sia of the input module Ia1, then it closes that gate and opens the gate of the interrupt status register Sia of the input module Ia2 instead. Next, it closes that gate and opens the gate of the input module Ib1. In this way, it opens the gate of Ib3, then it closes that gate and opens the gate of the input module Ib2.
The gate of the data status register Sba of Ia1 is opened. Next, that gate is closed and the Sda gate of Ia2 is opened instead. In this manner, the gates of Sdb are opened one by one in sequence.

However, if, as a result of opening the gates of the interrupt status registers Sia and Sib, a first signal requesting an interrupt is detected from either of the interrupt status registers Sia and Sib at that time, the central processing unit 21 stops opening the gates of the interrupt status registers Sia and Sib thereafter, and instead jumps to open the gates of the data status registers Sda and Sdb in either of the blocks 3a and 3b in which the signal requesting an interrupt was detected.

2, due to the size of the paper, only two input/output modules Ia1, Ia2, Ib1, and Ib2 are shown for each block, which is sufficient for explaining the configuration and operation of the present invention.

Latch circuits ia1' and ia2' of input/output modules Ia1 to Ib3
The outputs of the OR circuits OR1 and OR2' are input to the interrupt status registers Sia and Sib, respectively. The interrupt status registers Sia and Sib also have interrupt signal transmission lines Bia and Bib.
The above signal is input via a NOT circuit N.

On the other hand, the outputs of the OR circuit OR1 are NAND circuits (NAN
The NAND circuit NA performs a logical operation with the outputs of flip-flops Fa1 to Fb3 (only Fa1, Fa2, Fb1, and Fb2 are shown in the figure) that constitute part of the designation means. The signal generated at the output terminal of the NAND circuit NA is the first signal.

The first signal is connected to the interrupt signal transmission lines Bia and Bib, respectively. The interrupt signal transmission lines Bia and Bib are usually connected to resistors r
Since 5V is given through the
When the NAND circuit NA outputs a signal indicating that an interrupt process has been requested, the signal goes to L level.

Now, the designation means will be explained in detail. Flip-flops Fa1 to Fb3 are provided in all input modules, and by initialization processing before starting operation, the data shown in Fig. 4 is sent from the central processing unit 21 via the data bus Bd, and the flip-flop outputs of input modules that accept interrupt processing are latched to H, and the flip-flop outputs of input modules that do not accept interrupt processing are latched to L. Fig. 4 shows input modules Ia1,
Ib1 and Ib2 indicate that they can receive interrupt processing, but Ia2 and Ib3 indicate that they cannot accept interrupt processing.

From the above, it can be understood that the output of the NAND circuit NA in the input module Ia2 is always H, and that no matter which signal is input to any of the input terminals t1 to tn in the input module Ia2, it will not be accepted as an interrupt signal.

Now, when a signal requesting interrupt processing is output from any module in the blocks 3a and 3b, the interrupt signal transmission lines Bia and Bib of the block to which that module belongs become L.
This state is transmitted to the basic unit 2 via the one-way gates Ga and Gb and the interrupt signal transmission line Bi. In other words, the outputs of the one-way gates Ga and Gb are the second signals.

When the second signal is output from either block 3a or 3b, the basic unit 2 knows that an interrupt request has been issued, but it does not yet know which of the blocks 3a or 3b the request came from, or which module.

Therefore, the execution of logical operations based on the sequence program is immediately stopped, and instead the gates are opened in the order shown in Figure 3. If a signal requesting interrupt processing is now input to terminal t1 of input module Ib1, when the gate of Sia in Ia1 is opened, the information shown in a1 in Figure 5 is taken into basic unit 2 via data buses Bda and Bd. At this time, the output of NAND circuit NA and the output of OR1 in module Ia1 are both L, so it can be seen that no interrupt request signal is being output from module Ia1, or any other module in this block. Therefore,
The gate is closed and the gate of the next block, that is, the gate of Sib in module Ib1, is opened instead. When this gate is opened, the 0th bit is H and the 1st bit is L, as shown in b1 of Figure 5. NAND circuit NA
When the output of the first bit of OR1 is L, it is understood that an interrupt request has been issued from that block, and when the output of OR2 is H, it is understood that a signal has been issued from that module, so in the end, the signal requesting this interrupt processing is
The interrupt request signal is then sent to the basic unit 2 via the data bus Bdb and Bd.
It is recognized that the signal has entered the input terminal t1 in the basic unit 1. Therefore, the basic unit 2 performs processing based on this recognition.

Note that a2 and b2 in Figure 5 are the signal states obtained by opening the interrupt status registers Sia and Sib of the modules Ia2 and Ib2, respectively. As shown in a2 in Figure 5, the 0th bit is either L or H, but even when it is H, the flip-flop
Since the output of Fa2 is L, the terminal of this module Ia2
t1 to tn do not become interrupt request signals.

6 and 7 are flowcharts for explaining the operation. After the start, initialization is performed in St1. At this time, the flip-flop Fa1 explained in FIG.
~Fb3 is set.

In St2, processing is performed based on the sequence program. In other words, the basic unit 2 takes in information from the signal input terminal latched in a specified input module, performs logical operations according to the sequence program, and outputs the results to a specified output terminal in the output module. At this time, the basic unit 2 checks in St3 in a time-sharing manner to see if an interrupt processing request has been received. If an interrupt processing request has not been received, it returns to St2; if it has, it proceeds to St4. In St4, the processing explained with reference to Figure 5 is performed, and then once the cause of the interrupt is determined, it proceeds to St5 and performs the necessary processing.

The detailed flow in ST4 is shown in Figure 7. The details of this will be easily understood from the above explanation. If the terminal that issued the interrupt signal cannot be found in the last unit shown in ST43, the interrupt signal transmission lines Bi, Bi
It is possible that noise has entered a,Bib, so it is advisable to return to St2.

8 shows another embodiment of the present invention. In this embodiment, in addition to the signal input terminals t1 to tn, internal terminals t11 and t12 are provided for signals requesting interrupts. For example, in module I,
If an abnormality occurs in the microcomputer (not shown) in a1, information is output to a predetermined terminal of t11 or t12, which is used to issue a signal to the outside to indicate the occurrence of the abnormality, for example.

Figure 9 shows yet another embodiment of the present invention. With this circuit, it is possible to set for each input terminal of the input module which terminals require interrupt processing and which do not. That is, the flip-flop indicated as a whole by Fa1 has the same number of flip-flop elements F1 to Fn as the number of input terminals t1 to tn. Elements corresponding to terminals requiring interrupt processing are set to H during initialization, and those not requiring interrupt processing are set to L. The outputs of flip-flop elements F1 to Fn are subjected to logical operations with the latched signals input to each input terminal in logical AND circuit AN.
N1 is a NOT circuit.

Claims (6)

[Claims] [Claim 1] A device comprising: program storage means for storing a sequence program; a plurality of blocks, at least one of which is further divided into a plurality of groups, each of which is provided with a plurality of external signal input terminals; a timing signal generating section for generating timing signals; arithmetic processing means for performing logical operations on a plurality of signals, including the external signal received from the external signal input terminal, in accordance with instructions of the sequence program read from the program storage means, in synchronization with the timing signals; and output means for outputting a control signal according to the operation result of the arithmetic processing means, a first signal generating means for outputting a first signal when a factor requesting the first signal occurs; a second signal generating means for outputting a second signal when any of the blocks is outputting the first signal; a second signal generating and transmitting means for transmitting the second signal to the arithmetic processing means when the second signal is output from any of the blocks; and when the arithmetic processing means is notified by the second signal generating and transmitting means that the second signal is being output, the arithmetic processing means stops executing the logical operation based on the sequence program, sequentially accesses each of the second signal generating means, and when it finds the block from which the second signal is being output, accesses the first signal belonging to that block.
and access means for sequentially accessing the signal generating means, and for identifying the unit that is outputting the first signal. 2. The sequence controller according to claim 1, wherein said timing signal generating section is a program counter which outputs a memory address signal in synchronization with said timing signal, and said arithmetic processing means executes the following in accordance with instructions of said sequence program read from said program storage means in relation to said memory address signal:
a sequence controller configured to perform a logical operation on a plurality of signals including the external signal received from the external signal input terminal; 3. The sequence controller according to claim 1, wherein said first signal generating means generates a signal when a signal is input to a specific terminal of said external signal input terminal.
A sequence controller configured to output a first signal. 4. A device comprising: program storage means for storing a sequence program; a plurality of external signal input terminals divided into a plurality of blocks, at least one of said blocks being further divided into a plurality of groups, each of said blocks being provided with a plurality of external signal input terminals; a program counter for outputting a memory address signal in synchronization with a timing signal; arithmetic processing means for performing logical operations on a plurality of signals including said external signal received from said external signal input terminals in accordance with instructions of said sequence program read from said program storage means in relation to said memory address signal; and output means for outputting a control signal in accordance with the operation result of said arithmetic processing means, a designation means for designating the terminal as a signal input terminal; a first signal generation means for outputting a first signal when a signal requesting an interrupt is input to the specific terminal in the group to which the interrupt signal input terminal belongs; a second signal generation means for outputting a second signal when any of the blocks is outputting the first signal; a second signal generation and transmission means for transmitting to the arithmetic processing means when the second signal is output to any of the blocks; and when the arithmetic processing means is notified by the second signal generation and transmission means that the second signal is output, the arithmetic processing means stops execution of a logical operation based on the sequence program, and sequentially accesses each of the second signal generation means and executes the second signal generation and transmission means.
and an access means for sequentially accessing the first signal generating means belonging to the block when the block from which the signal is being output is found, thereby identifying the unit outputting the first signal. 5. The sequence controller according to claim 4, wherein said designation means is configured to designate said external signal input terminals as interrupt signal input terminals in said group units. 6. The sequence controller according to claim 4, wherein said designation means is configured to designate said external signal input terminals in said group as interrupt signal input terminals on an individual basis.