JPH0828526B2 - Method for manufacturing semiconductor photoelectric conversion device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a photoelectric conversion device using an electrostatic induction transistor (hereinafter referred to as SIT).

[Prior art]

It is already known that photoelectric conversion devices using SIT have the characteristics of high current gain, equal signal-to-noise ratio, and wide dynamic range (for example, see Japanese Patent Application No. 58-249546). ).

Due to the above features, the SIT photoelectric conversion device is particularly useful for detecting weak light.

Hereinafter, a conventional SIT photoelectric conversion device will be described with reference to the drawings. Figure 3 shows the planar type (surface diffusion gate type)
1 shows an example of the structure of a SIT photoelectric conversion device. In this figure, when light is incident on the depleted low impurity concentration layer of the N ^- epitaxial growth layer 2 formed on the N ⁺ substrate 1 serving as the source region, electrons are emitted depending on the incident light amount.
Hole pairs are generated. Electrons are N-type high impurity concentration region
It flows out from the electrode 3 through the N ⁺ substrate 1. The holes flow into and accumulate in the gate region 4 and change the potential of the gate. Since the gate region 4 is in contact with the gate electrode 6 (which is a transparent electrode such as ITO for transmitting light) through the insulating film 5, holes do not flow out of the gate, and the gate according to the amount of incident light is generated. Bring about a change in potential. At this time, if a voltage is applied between the electrode 8 formed on the drain region 7 and the source electrode 3, a main current according to the gate potential, that is, according to the amount of incident light flows.

FIG. 4 shows an example of a method of manufacturing the structure shown in FIG. An N ⁻ high resistance epitaxial layer 2 is grown on the N ⁺ resistance substrate 1 and covered with a diffusion mask 11. Further, the window 12 is opened in the portion which will be the gate region (a). For example, the resistivity of N ⁺ substrate is 0.00
7-0.02Ω-cm, the resistivity of the epitaxial layer 2 is 100Ω-
Be at least cm. The diffusion mask may be, for example, a thermal oxide film having a thickness of 0.6 to 1 μm. Next, in order to form the gate portion 4 from the window 12, P
A type impurity (for example, boron) is diffused to a depth of 2 to 4 μm (b). A window 13 is opened in a portion which will be a drain, and N-type impurities are diffused to a depth of 0.2 to 0.7 μm (c). Finally, by forming the source electrode 3 and the drain electrode 8 and the thin insulating layer 5 and the transparent electrode 6 on the gate, the planar type SI
A T photoelectric conversion device can be manufactured.

[Problems of conventional technology]

However, according to the conventional method for manufacturing the SIT photoelectric conversion device, as shown in FIG. 3, the gate-mask interval is Wg, the surface main electrode width is Ws, the gate diffusion depth is Xj, and the gate-main electrode interval is ΔW, lateral spread of gate diffusion is 0.8X
j Becomes Practical values of these variables, eg Wg = 6μm
In the case of, in order to improve the effectiveness of the gate, it is necessary that Xj≈2.5 μm, but Ws + 2ΔW≈2 μm
Even if = 1 μm, only a narrow interval ΔW = 0.5 μm can be obtained.

Therefore, the breakdown voltage is as low as about 12 V, and due to an error in the mask alignment process, the breakdown voltage and the leak current often increase due to the contact between the gate and the main electrode. Further, the proximity of the two regions increases the parasitic capacitance between the gate and the drain, which causes a decrease in photoelectric conversion speed and an increase in drive current.

As a means for solving such a problem, it is necessary to increase the distance between the gate and the main electrode with respect to the planar structure.
A cut gate structure as shown in the figure has been proposed. However, in the fine structure as in the above example, when the silicon or the like is cut using an appropriate mask, the lateral etching is largely uncontrollable in isotropic etching such as chemical (wet) etching. It is necessary to make vertical cuts using anisotropic etching with. However, according to this anisotropic plasma etching, unrecoverable crystal defects 14 of extremely high density are generated in the crystal, so that the device characteristics are deteriorated and a practical one cannot be obtained.

[Object of the Invention]

The purpose of the present invention is to reduce the leakage current depending on the manufacturing process and parasitic capacitance while making use of the features of the SIT photoelectric conversion device described above, and a new manufacturing process for preventing the introduction of crystal defects that deteriorate the device characteristics. To provide.

[Outline of Invention]

Therefore, the present invention provides a mask for selective epitaxial growth, which has a two-layer structure and whose sidewall portion is formed of the material of the first layer in a method of manufacturing a semiconductor photoelectric conversion device using an electrostatic induction transistor. A step of selectively epitaxially growing a high resistance layer using the same, a step of ion-implanting a portion of the high resistance layer area that has been selectively epitaxially grown to serve as a main electrode, and a mask for selective epitaxial growth on both sides of the ion-implanted area And a step of selectively implanting ions into the gate region using the first layer of the selective epitaxial growth mask as a mask. It is characterized in that the region and the impurity density region of the gate are formed in a self-aligned manner.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

Next, a first embodiment of the present invention will be described in detail with reference to FIG.

(A) 31 is an N ⁺ silicon substrate having an impurity concentration of 10 ¹⁸ to 10 ¹⁹ / cm ³ , and 32 is an N ⁻ silicon layer having a thickness of ^{3 to} 10 μm and an impurity concentration of about 10 ¹⁴ / cm ³ or less. On this N ^- silicon layer 32, a silicon nitride film (Si ₃ N ₄ ) 33 having a thickness of about 1500Å and a silicon oxide film (SiO ₂ ) 34 having a thickness of about 1 to 2 μm are formed by chemical vapor deposition (CVD). To grow respectively. Here, a resist pattern is formed by photoetching, and anisotropic etching is performed by CF ₄ + H ₂ gas plasma using this as a mask to form a mask for selective epitaxial growth.

(B) A silicon nitride film is similarly grown to a thickness of about 1000Å, the entire surface is anisotropically etched by reactive ion etching with CF ₄ + H ₂ gas plasma, and only the wall surface is nitrided with silicon nitride. Leave the membrane 35. SiCl
₄ (or SiHCl ₃ , SiH ₂ Cl ₂ ) is reduced by H ₂ gas to selectively epitaxially grow silicon to obtain a high resistance N ⁻ layer 36 having a thickness of 1 to 2 μm.

(C) The photoresist is coated with a photoresist 37 having a thickness of about 1 to 2 μm except for the SIT channel and the portion to be the main electrode on the front surface side. In this case, since the photoresist 37 can be formed so as to overlap the silicon nitride film 33, there is a margin in the mask alignment dimension, which facilitates manufacturing. Where As ⁺ ion is 1
Ion implantation is performed with an energy of 00 KeV and about 10 ¹⁶ / cm ³ . Since As ⁺ ions are stopped by the photoresist 37 and SiO ₂ 34, the portion that should become the N ⁺ surface main electrode of the SIT 3
Only 8 will be injected.

(D) The photoresist 37 is removed by a resist stripping solution, and the SiO ₂ 34 on the surface is removed by etching with a hydrofluoric acid solution, and then the As implanted in the previous step is driven in.
Surface impurity concentration of 10 ¹⁹ to 10 ²⁰ / cm ³ , N of depth 0.3 to 0.6 μm
⁺ Selectively oxidize except the part where the surface main electrode is formed and covered with the silicon nitride films 33 and 35, and 4000 to 6000Å SiO ₂
Get 39. B ⁺ ion implantation (energy 75 KeV, implantation amount about 1
X 10 ¹⁴ to 1 x 10 ¹⁶ / cm ³ ), B ⁺ is stopped at the part covered with SiO ₂ 39, and the part of the silicon nitride film 33 is
Since B ⁺ ions pass, it can be ion-implanted to selectively form a B ^+.

(E) B ⁺ implanted in the previous step is annealed to form a gate region 40, and then a required opening is formed in the silicon nitride film 33 and SiO ₂ 39 by photoetching, and an electrode pattern 41 made of a metal such as aluminum. To form. Further, an electrode 42 for the back side N ⁺ main electrode 31 is formed.

Next, a second embodiment of the present invention will be described with reference to FIG.
In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts.

(A) A mask for selective epitaxial growth is formed and selective epitaxial growth is performed in the same manner as in the embodiment of FIG.

(B) After removing the silicon oxide film 34 by etching with a hydrofluoric acid solution, the silicon oxide film 39 is formed to a thickness of about 4000 to 6000Å by thermal oxidation except for the portions covered with the silicon nitride films 33 and 35. After this, B ⁺ ion implantation (eg 1 × 1 at 75 KeV)
0 ¹⁴ -1 × 10 ¹⁶ / cm ³ ), B ⁺ is not implanted into the silicon portion covered with the silicon oxide film 39, but since the silicon nitride film 33 is sufficiently thin, B ⁺ is implanted. To be done. Annealing is performed to form the P ⁺ gate region 40.

(C) By photo-etching, the silicon oxide film 39 only on the portion 38 forming the surface N ⁺ main electrode of the SIT is removed by etching with a hydrofluoric acid solution, and As ⁺ ion implantation (for example, 100 Ke
1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ³ ) is performed with V, and then SiO ₂ 39 is formed only on the main electrode portion 38 again.

(D) The ion-implanted As ⁺ is annealed and driven in to form the surface N ⁺ main electrode 38. A desired contact hole is formed by photoetching, and the required N ⁺ electrode wiring 41a
Is made of polysilicon, aluminum, etc., and if a storage capacitor is to be provided on the gate as shown in this example, M (ITO) (Indium / Tin / Oxide film) with good incident light efficiency
The IS gate electrode 41d is formed. Also, the electrode 4
2 is similarly formed.

In this way, if the photoelectric conversion device is manufactured,
^- without contacting the surface main electrode and the P ⁺ control electrode (gate portion), it is possible to separately formed across the high-resistance epitaxial layer, reducing a leak current between the electrodes, and significantly improve the withstand voltage The parasitic capacitance can be reduced. In addition, the channel width can be accurately determined by selective epitaxial growth, and it is not necessary to form the P ⁺ gate part deep as in the conventional planar type. It can be manufactured well. On the other hand, in the gate method for incision using etching, the use of plasma etching for incision in the gate portion inevitably causes the generation of crystal defects in the gate portion, and it was extremely difficult to reduce the leakage current. Since the invention essentially uses only epitaxial growth with few defects, the leak current can be suppressed to an extremely small value.

In addition, even if the gate depth to be the photosensitive part is formed as shallow as about 1 μm, the controllability is sufficiently good that the respiratory coefficient of 500 n is large.
Conventional sensitivity to short wavelength light of m or less (gate depth 2
.About.3 .mu.m), a SIT photoelectric conversion device which is several times higher than that of the present invention can be realized.

Although the N-channel SIT is described in the above-described embodiment, the present invention can be sufficiently applied to the P-channel SIT by modifying the conductivity type to be opposite.

Further, in the above-mentioned embodiment, the description has been made only for the case of the N ⁺ substrate (common main electrode).
N-type on the P-type substrate as in the case of forming the bottom main electrode or when it is necessary to form the lower main electrode separately for each SIT.
Needless to say, the present invention can be applied to a structure in which the ⁺ layer or the N ⁺ region is partially provided as a so-called buried layer.

Further, the present invention is not limited to silicon,
It goes without saying that it can be applied to III-V group semiconductors and other semiconductors.

〔The invention's effect〕

As described above, according to the present invention, since characteristics of low leakage current, high breakdown voltage, and low parasitic capacitance are obtained, an excellent SIT photoelectric conversion device with high sensitivity, low crosstalk, high speed, and low power consumption can be obtained. .

[Brief description of drawings]

1 (a) to 1 (e) are explanatory views of a manufacturing process of a photoelectric conversion device according to the first embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are second embodiment of the present invention. FIG. 4A to FIG. 4D are sectional views showing an example of a conventional structure of a photoelectric conversion element using an electrostatic induction transistor. 4) is a process explanatory view for producing the structure shown in FIG. 3, and FIG. 5 is a sectional view showing a conventional example of a notch gate type for eliminating the drawback of FIG. 21 …… Mask for selective growth, 23, 37 …… Photoresist, 34, 39 …… Silicon oxide film (SiO ₂ ).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Mizusaki 1337-1, Tennocho, Hamamatsu City, Shizuoka Prefecture Mansion Camellia No. 3-303 (72) Inventor Hitoshi Anzai 177, Kamiishidacho, Hamamatsu City, Shizuoka Prefecture (72) Inventor Junichi Nishizawa 1-6-16 Yonegabukuro, Sendai City, Miyagi Prefecture (56) Reference JP-A-56-88370 (JP, A) JP-A-59-107578 (JP, A) JP-A-59-43581 (JP, A) )

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor photoelectric conversion device using a static induction transistor, which has a two-layer structure, and
A step of selectively epitaxially growing the high resistance layer using a mask for selective epitaxial growth, the side wall of which is formed of the first layer material; and ion implantation into a portion of the high resistance layer region that has been selectively epitaxially grown to serve as a main electrode. And a step of etching the second layer of the selective epitaxial growth mask on both sides of the ion-implanted region, and selectively using the first layer of the selective epitaxial growth mask as a mask And a step of implanting ions, the method for manufacturing a semiconductor photoelectric conversion device, comprising: forming an impurity density region serving as a main electrode on a surface and an impurity density region of a gate in a self-aligned manner.