JPH0828731B2 - Time division multi-directional multiplex communication device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multi-directional multiplex communication device.

[0002]

2. Description of the Related Art In a conventional time division multi-directional multiplex communication apparatus, as shown in FIG. 3, an upstream signal transmitted by a relay station R _n and a slave station T _n has a temporal position of a received downstream signal. Based on the standard, the master station B is given a delay amount so that the downlink signal and the uplink signal differ by the time corresponding to one frame, and is transmitted to the host station (for example, see Japanese Patent Laid-Open No. 63-74234).

[0003]

The above-described conventional time division multi-directional multiplex communication apparatus is configured so that each relay station, such that the time delay of the downlink signal and the uplink signal at the master station B differs by one frame time, Since the delay of the upstream signal of the slave station is adjusted, the time delay between the downstream signal and the upstream signal is always generated in the master station B by one frame regardless of the distance of the remote station at the farthest end. There was a problem.

It is an object of the present invention to provide a time division multi-directional multiplex communication device capable of controlling the amount of delay of an upstream signal (direction of each station from each station) of each station to a minimum value.

[0005]

The present invention comprises one master station and a plurality of relay stations / slave stations, and transmits a frame synchronization pattern from the master station / relay station to a lower station (downstream direction). , The relay station / slave station of the lower station detects the received frame synchronization pattern, generates a frame pulse indicating the temporal reference of the downlink / uplink frame, and uses the frame pulse as a reference for the upstream signal to be transmitted to the upper station. Hierarchical bus type time division multi-directional multiplex communication apparatus for performing communication by giving a delay amount D, adjusting a temporal position, transmitting as a burst signal to a higher station, and controlling the higher station to line up on a time axis. In the above, a delay adjustment channel is provided in an up / down transmission path between each station, and the master station B is instructed to transmit the delay amount D of the upstream signal to each slave station T, or each relay. Station / each slave station Means for generating a second command for instructing to reduce the delay amount by D from the total amount, means for multiplexing the first and second commands on the downlink delay adjustment channel DCH, and a child multiplexed on the uplink delay adjustment channel. A unit for separating the delay amount D of the upstream signal of the station and a unit for detecting the minimum value D _min of the separated delay amount D of the upstream signal are provided, and each slave station multiplexes by the master station from the downlink delay adjustment channel. And a means for separating the generated first command and a means for multiplexing the delay amount D of the upstream signal of the local station on the upstream delay adjustment channel when the first command is a command for the local station. The relay station and each slave station are provided with means for separating the second command multiplexed by the master station from the downlink delay adjustment channel, and means for reducing the delay amount of the own station by D by the second command. Is characterized by.

[0006]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a relay station R and a slave station T under a master station B are connected in a hierarchical bus type to a relay station R _n and a slave station T. It is shown for _n .

The master station includes a multiplexing circuit 11 and an arithmetic circuit 12
And a separation circuit 13.

The relay station R _n includes a frame synchronization circuit 21 and
Separation circuit 22, upstream delay adjustment circuit 23, and multiplexing circuit 2
4 and.

The slave station T _n includes a frame synchronization circuit 31, a separation circuit 32, an upstream delay adjustment circuit 33, and a multiplexing circuit 35.
It has and.

As shown in FIG. 1, a downlink frame 100 is provided with a frame synchronization pattern F, a downlink delay adjustment channel DCH is multiplexed, and a master station B to lower stations (relay station R _n , slave station T _n ). To the upstream frame 2
At 00, the upstream delay adjustment channel DCH becomes a burst signal and is transmitted from the lower station to the upper station.

In FIG. 1, the multiplexing circuit 11 of the master station B is
It is a circuit that multiplexes the frame synchronization pattern F on the downlink signal and the command from the arithmetic circuit 12 to the downlink delay adjustment channel DCH.

The arithmetic circuit 12 is a circuit which receives the data of the upstream delay adjustment channel DCH separated by the separation circuit 13 and outputs a command for the lower station to the multiplexing circuit 11.

The separation circuit 13 has an upstream delay adjustment channel D.
This is a circuit for separating CH data.

The frame synchronization circuit 21 of the relay station R _n
Is a circuit that receives the downlink frame 100 transmitted from the upper station, detects the frame synchronization pattern F in the downlink frame 100, and outputs a frame pulse indicating the temporal reference of the downlink / uplink frame to the separation circuit 22. is there.

The separation circuit 22 uses the frame pulse input from the frame synchronization circuit 21 as a reference, and sets the downlink frame 1
This is a circuit that separates the data of the downlink delay adjustment channel DCH from 00 and outputs the data to the uplink delay adjustment circuit 23 when the command is for the own station.

The multiplexing circuit 24 is a circuit for multiplexing the upstream burst signal transmitted from the lower station with the upstream signal of the local station.

Further, the frame synchronization circuit 31 of the slave station T _n receives the downlink frame 100 transmitted from the upper station, detects the frame synchronization pattern F in the downlink frame 100, and sets the time reference of the downlink / uplink frame. The circuit outputs the frame pulse shown to the separation circuit 32.

The demultiplexing circuit 32 uses the frame pulse input from the frame synchronization circuit 31 as a reference, and the down frame 1
This is a circuit for separating the data of the downlink delay adjustment channel DCH from 00 and outputting the data to the uplink delay adjustment circuit 33 and the multiplexing circuit 35 when the command is for the own station.

The multiplexing circuit 35 is a circuit for multiplexing the delay adjustment data output from the separation circuit 32 on the upstream signal of the own station and the upstream signal of the own station.

Based on the above structure, the operation will be described with reference to FIG. Note that FIG. 2 is a diagram showing a temporal relationship between downlink / uplink frames in the master station B, the relay station R _n , and the slave station T _n .

First, in FIG. 1, the relay station R _n and the slave station T are made to have a time relationship as shown by the dotted line in FIG. 2 by using, for example, the method described in Japanese Patent Laid-Open No. 63-74234. It is assumed that the delay amount of the upstream signal of _n is adjusted.

Next, the arithmetic circuit 12 of the master station B sends 1 to the slave station T located at the lowest station of the hierarchical bus type network.
A command A for transmitting the uplink delay amount D to the master station B is generated for each station and output to the multiplexing circuit 11. Multiplex circuit 11
Command multiplexes the command A on the downlink delay adjustment channel DCH of the downlink frame 100 and transmits it to the lower station.

In the slave station T, the frame synchronization circuit 31 detects the frame synchronization pattern F in the downlink frame 100 and outputs a frame pulse indicating the reference of the downlink / uplink frame to the separation circuit 32. The separation circuit 32 determines whether the separated command A is a command for its own station,
When the command is for the own station, the delay amount D of the upstream signal of the own station is output to the multiplexing circuit 35. The multiplexing circuit 35 is
The delay amount D is multiplexed on the uplink adjustment channel DCH, and the uplink delay adjustment channel DCH is transmitted to the upper station via the uplink delay adjustment circuit 33 and reaches the master station B.

In the master station B, the separation circuit 13 separates the delay amount D in the upstream delay adjustment channel DCH sent from the slave station, and outputs the delay amount D to the arithmetic circuit 12.

[0026] Thus, the arithmetic circuit of the master station B 12, to the slave station T _n located at the lowest station of the hierarchical bus network, the delay amount D of the sub-stations T _n polling described above
get _n Therefore, the arithmetic circuit 12 obtains the minimum delay amount D _min of the delay amounts D _n .

Next, the arithmetic circuit 12 of the master station B generates a command B for instructing all the relay stations R _n and slave stations T _n to reduce the delay amount of the upstream signal by D _min , and the multiplexing circuit 1
Output to 1. The multiplexing circuit 11 multiplexes the command B on the uplink delay adjustment channel DCH of the downlink frame 100 and transmits it to the lower station.

In each relay station R _n and slave station T _n , the frame synchronization circuits 21 and 31 detect the frame synchronization pattern F in the downlink frame 100, and separate the frame pulse indicating the reference of the downlink / uplink frame into the separation circuit 22 and 31. To 32. The separating circuits 22 and 32 instruct the upstream delay adjusting circuits 23 and 33 to reduce the delay amount of the local station by D _min by the separated command B, and the upstream delay amounts of the relay stations R _n and the slave stations T _n. Is reduced by D _min all at once.

Therefore, by the above-mentioned operation, the delay amount of the upstream signal of each relay station R _n and slave station T _n can be adjusted so that the time relationship as shown by the solid line in FIG. 2 is obtained.

[0030]

As described above, according to the present invention, the delay amount of the upstream signal can be controlled to be the minimum in accordance with the positional relationship between the lowest station T _n and the master station B of the hierarchical bus type network. Have an effect.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a timing chart in an example of the present invention.

FIG. 3 is a timing chart in a conventional example.

[Explanation of symbols]

 11,24,35 Multiplexing circuit 12 Arithmetic circuit 13,22,32 Separation circuit 21,31 Frame synchronization circuit 23,33 Up delay adjustment circuit

Claims (2)

[Claims] 1. A master station and a plurality of relay stations / slave stations, which transmits a frame synchronization pattern from the master station / relay station to a lower station (downward direction) to relay / slave the lower station. The station detects the received frame synchronization pattern, generates a frame pulse indicating the temporal reference of the downlink / uplink frame, gives a delay amount D to the upstream signal to be sent to the higher station based on the frame pulse, and sets the temporal position. In the hierarchical bus type time division multi-directional multiplex communication device for adjusting and transmitting a burst signal to the upper station, and controlling the upper station to line up on the time axis, the master station is a hierarchical bus. Means for obtaining the delay amount D of the upstream signal by polling with respect to the slave station at the end of the type network, and calculating the minimum delay amount D _min of the obtained delay amounts D, and each relay station and each slave station. It decreased by D _min delay amount to And means for instructing the division multidirectional multiplex communication system when, characterized in that. 2. A master station and a plurality of relay stations / slave stations, which transmits a frame synchronization pattern from the master station / relay station in a lower station direction (downstream direction) and which is a relay station / slave of the lower station. The station detects the received frame synchronization pattern, generates a frame pulse indicating the temporal reference of the downlink / uplink frame, gives a delay amount D to the upstream signal to be sent to the higher station based on the frame pulse, and sets the temporal position. In a hierarchical bus type time division multi-directional multiplex communication device that performs communication by controlling the signal to be transmitted as a burst signal to a higher station and arranging them in a line on the time axis at the higher station. A delay adjustment channel is provided on the transmission path, and the master station B is instructed to transmit the delay amount D of the upstream signal to each slave station T, or to each relay station / each slave station. For the upstream signal, add the delay amount D from the delay amount Means for generating a second command to the cheat instructions, the first and second command downlink delay adjustment channel DCH
Means for separating the delay amount D of the upstream signal of the slave station multiplexed on the upstream delay adjustment channel, and means for detecting the minimum value D _min of the delay amount D of the separated upstream signal, Each slave station has means for separating the first command multiplexed by the master station from the downlink delay adjustment channel, and when the first command is a command for the own station, the uplink delay adjustment channel of the own station Means for multiplexing the delay amount D of the upstream signal, and means for separating each second relay station and each slave station from the second command multiplexed by the master station from the downstream delay adjustment channel, and the second command. A time-division multi-directional multiplex communication device, comprising means for reducing the delay amount of its own station by D.