JPH08297631A - Bus control method - Google Patents

Abstract

(57) [Abstract] [Purpose] Efficient bus control so that one bus master can secure the bus for a long time and operate when multiple bus masters use the system bus unless another bus master requests it. Is possible. When the bus master B is busy and a request is made from the bus master A having a high priority, the bus controller 12 negates an acknowledge signal and requests the bus master B to release the bus 13. When the bus master B releases the bus 13 and negates the request signal, the bus controller 12 asserts an acknowledge signal to the bus master A. As a result, the right to use the bus 13 is transferred from the bus master B to the bus master A. In addition, the bus master B immediately asserts the request signal and the bus 13
Request the use of. As a result, after the bus access by the bus master A is completed, the right to use the bus 13 is transferred to the bus master B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control method for performing priority control when a plurality of bus masters use a system bus in an information processing system such as a personal computer.

[0002]

2. Description of the Related Art Conventionally, in an information processing system such as a personal computer, the system bus is
CPU, DAMC (direct memory acsess controller)
), A main memory, a ROM, a video RAM, and various input / output interfaces are connected. The DAMC is a controller that centrally controls data transfer between a high speed device such as a hard disk device and a floppy disk device and a main memory.

Generally, the bus access right is the CPU and D.
Bus control is simplified by limiting to AMC, but CPU
In addition, there are cases where a system bus that allows a plurality of bus masters (modules that have access to the bus) to coexist is adopted. In this case, in addition to the CPU, there is an I / O controller or the like as a module that can be a bus master.

Here, in a system in which a plurality of bus masters use a system bus, two signal lines called request and acknowledge are used to contend for the bus. The request signal is a signal from the bus master to notify the bus controller of the bus use request. The acknowledge signal is a signal for permitting the bus master to use the bus from the bus controller.

The bus controller is a controller for controlling the priority of each bus master. When the request signal is output from the bus master, the bus controller asserts the acknowledge signal (sets the active state) according to the priority of the bus master, and releases the bus to the bus master until the request signal is negated.

[0006]

By the way, in the conventional bus control system, the bus is released by setting the time during which one bus master can occupy the bus by one access. During this time, a bus use request (request signal) from another bus master is checked, and if there is a request from a bus master with a high priority, the bus use right is transferred to that bus master.

This state is shown in FIG. FIG. 3 is a timing chart showing a conventional bus control operation. Eg 2
When two bus masters A and B use the bus (priority: A> B), it is assumed that the bus master B is currently using the bus. During this time, for example, the bus master A
Even if there is a bus use request from the bus master B, the bus master B has the bus use right until a predetermined time elapses. Bus master B
When the bus access is completed, the bus right to use is transferred to the bus master A.

In this way, the bus occupancy time is determined, and the requests from other bus masters are accepted at each interval, whereby the bus control according to the priority is realized.
However, in such a bus control method, when a bus master asserts a request signal (when the bus is in use), a bus master with a high priority outputs a request signal (requests use of the bus). However, the bus cannot be used until the bus master which is currently using the bus finishes the access, that is, until the bus occupation time elapses.

Further, even if there is no request from another bus master, the bus must be released once at a predetermined interval.
For this reason, one bus master cannot occupy the bus for a long time, which causes a problem when performing continuous processing.

Further, since the bus is accessed at predetermined intervals, bus contention control occurs each time and 1
There is a problem that it takes time for the two bus masters to access the bus.

If the bus master can confirm the bus usage status of another bus master, the above problem can be solved. However, in addition to the signal line of its own request / acknowledge, another request / acknowledgement. This is not an effective method because it requires a signal line.

The present invention has been made in view of the above points, and when a plurality of bus masters use the system bus, one bus master reserves the bus for a long time unless requested by another bus master. It is also an object of the present invention to provide a bus control method that enables efficient bus control such that it can operate.

[0013]

The bus control method of the present invention is a bus control method for an information processing system in which a plurality of bus masters use a system bus, and a bus use request from another bus master while the bus master is using the bus. When there is an error, the priority of the bus master is determined.If the priority of the bus master is higher than that of the bus master that is using the bus, the bus master that is using the bus is requested to release the bus, and the bus is released. After confirmation, the bus master with the higher priority is permitted to use the bus.

When the bus master that is using the bus releases the bus, the bus master requests the use of the bus immediately, and when the bus access of the bus master with the higher priority is completed, the bus master continues to use the bus. Is given priority.

[0015]

According to the bus control method as described above, if a bus master has a bus use request from a bus master with a high priority while the bus is in use, the bus use right is transferred to the bus master with a high priority. At this time, the bus master that has released the bus immediately requests the use of the bus, and when the bus master with the higher priority finishes the bus access, the bus use right is transferred to the bus master again.

[0016]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an information processing system according to an embodiment of the present invention. This system includes a plurality of bus masters 11a to 11c and a bus controller 12
Have. The bus masters 11 a to 11 c are connected to a system bus (hereinafter, simply referred to as a bus) 13 and
To share and use. In this case, a module that can be a bus master is a CPU, an I / O controller, or the like. A memory 14 such as a ROM or a RAM is connected to the system bus 13 as another module.

The bus controller 12 is for permitting the use of the bus 13. Here, the priority control unit 1 is used.
2a to control the priority of bus use of each of the bus masters 11a to 11c. In addition, this bus controller 12
May be built in each of the bus masters 11a to 11c.

Here, in this embodiment, the bus master 11a
Two signal lines for a request signal and an acknowledge signal are provided between 11c and the bus controller 12. The request signal is a signal for notifying a use request of the bus 13, and is output from the bus masters 11a to 11c to the bus controller 12. The acknowledge signal is a signal for permitting use of the bus 13, and is output from the bus controller 12 to the bus masters 11a to 11c.

Next, the operation of the embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing the bus control operation of the present invention. Here, for ease of understanding,
Description will be made assuming that two bus masters A (bus master 11a) and bus master B (bus master 11b) use the bus 13 (priority: A> B).

In FIG. 2, T1 indicates the timing at which the bus master B asserts the request signal, and the bus controller 12 asserts the acknowledge signal when the bus 13 is released.

T2 indicates the timing at which the bus master A asserts the request signal, the bus controller 12 negates the acknowledge signal for the bus master B, and requests the bus master B to release the bus.

T3 indicates the timing at which the bus master B negates the request signal. When the bus master B releases the bus 13, the bus master B negates the request signal to declare the release of the bus 13, and the bus controller 12 acknowledges the bus master A. Assert the signal.

T4 indicates the timing at which the bus master B re-asserts the request signal, and after the bus access of the bus master A is completed, the bus master B makes a request to acquire the bus 13 again.

T5 indicates the timing at which the bus master A negates the request signal. After the bus master A releases the bus 13, the bus master A negates the request signal and the bus 1
3, the bus controller 12 reasserts the acknowledge signal to the bus master B.

However, when the bus master A and the bus master B use the bus 13, the bus master B asserts the request signal and receives the acknowledge signal from the bus controller 12 and secures the bus 13 to operate. (T1).

At this time, when the bus master A having a high priority asserts the request signal, the bus controller 12
Requests the bus master B currently using the bus to release the bus 13 by negating the acknowledge signal (T
2). The bus master B releases the bus 13 in accordance with this request and negates the request signal to declare the release of the bus 13. Bus controller 12 is bus 1
When it is confirmed that 3 is released, the acknowledge signal for the bus master A is asserted (T3).

In this way, the right to use the bus 13 is transferred from the bus master B to the bus master A. As a result, the bus master A can secure the bus 13 and perform operations such as accessing the memory 14, for example.

The bus master B releases the bus 13 and negates the request signal, and immediately asserts the request signal to request the use of the bus 13 (T4). As a result, after the bus access of the bus master A is completed, the bus master B can immediately secure the bus 13 and operate (T5).

As described above, when the bus master B requests the use of the bus 13 from the high-priority bus master A while the bus is in use, the right to use the bus 13 is passed to the bus master A.
After the bus access of the bus master A is completed, the bus 13 will be used again. In this case, if there is no bus use request from the bus master A, the bus master B can continuously use the bus 13.

[0030]

As described above, according to the present invention, when a plurality of bus masters use the system bus, a request from another bus master can be accepted even if a certain bus master is using the bus. Therefore, by always keeping the bus reserved by one bus master, the bus can be accessed without causing contention for the bus unless there is a request from another bus master.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an information processing system according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the bus control operation of the present invention.

FIG. 3 is a timing chart showing a conventional bus control operation.

[Explanation of symbols]

11a to 11c ... Bus master, 12 ... Bus controller, 12a ... Bus controller, 13 ... System bus,
14 ... Memory.

Claims (4)

[Claims] 1. In a bus control method for an information processing system in which a plurality of bus masters use a system bus, when a bus master requests a bus use while another bus master is using the bus, the priority of the bus master is determined. However, if the priority is higher than the bus master that is using the bus, the bus master that is using the bus is requested to release the bus, and after confirming that the bus has been released, the bus master that has the higher priority A bus control method characterized by permitting use. 2. When the bus master that is using the bus releases the bus, the bus master requests the use of the bus immediately, and when the bus access of the bus master with the higher priority is completed, the bus master continues to use the bus. 2. The bus control method according to claim 1, wherein the bus control is permitted with priority. 3. A plurality of bus masters sharing a system bus with a request signal for notifying a bus use request and an acknowledge signal for permitting the use of the bus, and the priority of each bus master. In a bus control method of an information processing system provided between a bus controller for controlling and a bus master, when another bus master asserts the request signal to request the use of the bus while the bus master is using the bus, the bus master When the priority is higher than that of the bus master in use of the bus, the bus controller negates the acknowledge signal to the bus master in use of the bus to request the release of the bus, and the bus master in use of the bus requests the request signal. When declaring the release of the bus by negating the Bus control method is characterized in that by asserting the acknowledge signal to allow use of the bus for the serial high-priority bus master. 4. When the bus master in use of the bus negates the request signal and releases the bus, the request signal is immediately asserted to request the use of the bus, so that the bus master having the higher priority can use the bus. 4. The bus control method according to claim 3, wherein when the access is completed, the bus controller asserts the request signal of the bus master to preferentially permit continuous use of the bus.