JPH08297922A - Digital signal recording / reproducing method and apparatus - Google Patents

Abstract

PURPOSE: To inhibit the duplication of recorded information by efficiently recording packeted digital information in a recording and reproducing device at close packet intervals by adding arriving time information to each packet and, at the same time, changing at least one bit of the time information added to the information at the time of reproducing the information. CONSTITUTION: Packeted(PK) digital information is efficiently recorded in a recording and reproducing device by making the PK interval shorter by adding a time stamp(TS) indicating the arrival time of PK to each PK. Then reproduced signals are sent to a memory 520 and TS reading circuit 550 at every PK through a memory 510. When a coincidence detecting circuit 552 detects the coincidence between the outputs of the TS reading circuit 550 and a count circuit 551, a TS gate circuit 530 outputs the signal in the memory 520 by returning the PK interval to the original time interval and changing at least one bit of the TS information. Therefore, the duplication of the information recorded in the recording and reproducing device is inhibited.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for recording and reproducing digital information signals such as movies and programs transmitted by transmission means such as coaxial cables, optical cables, telephone lines and satellite broadcasting. It relates to a method and a device which makes it difficult to make a duplicate of a recorded digital information signal.

[0002]

2. Description of the Related Art As a method for inhibiting copying of a video signal in a recording / reproducing apparatus, for example, Japanese Patent Laid-Open No. 61-288582 (hereinafter referred to as the first publication) is known. In the technology described in this first publication, the signal is added immediately after the synchronizing signal of the video signal so that the television receiver does not malfunction and the video cassette recorder (hereinafter referred to as VTR) deteriorates in image quality. It is designed to record signals.

Further, Japanese Patent Laid-Open No. 4-360068 (hereinafter referred to as the second publication) discloses a technique relating to a data recording / reproducing apparatus which restricts copying and prevents browsing.

As a method for digitally compressing a video signal with high efficiency, for example, MPEG-2 (Moving Picture Exper).
ts Group) is known as the ITU-T Draft Rec. H.262 standard. As a transmission standard for video signals and audio signals compressed by MPEG-2, the MPEG-2 Systems Working
Draft is known.

[0005]

The above-mentioned standard describes a technique for compressing a program and digitally broadcasting it. When this compression method is used, a large compression rate can be obtained, and therefore, in the same transmission channel, 4 ~
Eight times as many programs can be broadcast. For this reason, for example, a service called near video on demand, which repeatedly broadcasts the same two-hour movie by shifting the time by 30 minutes, has already been started. However, since not all programs can be broadcast on-demand near video all day long, there is a demand to record the broadcast signal, shift the time, and play back at the time convenient for you, as in the past. There is.

As a method of recording and reproducing the digitally compressed and digitally broadcasted program, a method of decompressing the received digital signal, converting it into an analog signal, and recording it in a conventional analog VTR can be considered. However, converting to an analog signal and recording with an analog VTR would impair the good S / N of the digital signal.

Although it is desired to digitally record the digitally broadcasted signal as it is, the above-mentioned MPEG, for example, is used.
There is still no disclosure of a technique for recording a digital signal which is compressed by a standard and transmitted. Normally, when recording / reproducing a digital signal, error correction is sufficiently performed, so that image quality does not deteriorate even if copying is repeated.
However, on the other hand, it is difficult to protect the rights of the copyright holder if copying is permitted without deterioration of image quality. Conventional analog VT
The technology for protecting the rights of the copyright holder in the case of R is disclosed in the first publication. Further, the second publication discloses a technique relating to a data recording / reproducing apparatus that restricts copying and prevents browsing.

[0008] However, the above-mentioned technique of recording the digital signal as transmitted by compressing it according to the MPEG standard,
Nor is there any indication of a technique for limiting the duplication of such recorded signals.

The object of the present invention is to compress, for example, the MPEG standard,
It is an object of the present invention to provide a method and an apparatus capable of efficiently recording a transmitted signal and limiting duplication.

[0010]

In order to solve the above problems, the following means were used. That is, each of a plurality of programs is bit-compressed, each of the bit-compressed programs is encrypted, each of the encrypted programs is packetized and time-division multiplexed,
Modulate a time division multiplexed program with a single carrier, transmit a modulated signal, receive a transmitted signal, demodulate the received signal, and packetize at least one program from the demodulated signal Select as it is, decrypt the encryption of the selected packet format program, input the packet signal with time information with the time information of the packet arrival for each packet of the decrypted packet format signal, and input that time information In a method for recording / reproducing digital information for recording a packet signal with a time stamp, the recorded packet signal with time information is reproduced, and at least one bit of the time stamp information included in the reproduced packet signal is changed. It is designed to be output.

[0011]

The packet signal with the time information input to the recording / reproducing apparatus is recorded with the intervals between the packet signals reduced in order to improve the recording efficiency. During reproduction, the time information added to each packet signal is detected, and the packet interval is returned to the input state based on the time information and output from the recording / reproducing apparatus. Since the packet signals are recorded at intervals close to each other, it is possible to record at a signal rate lower than the input signal, and it is possible to perform efficient recording. Then, by using the time information added to the packet signal, the original packet interval can be restored for reproduction. At the time of reproduction, by converting and outputting at least 1-bit information of the added time information, when the reproduction signal is input to another recording / reproducing device and recorded, the signal is reproduced and the original signal is reproduced. Even if an attempt is made to return to the packet interval, since the added time information is different from the original time information, it is no longer possible to return to the original packet interval. Therefore, the signal cannot be expanded and restored.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As one embodiment of the present invention, a video distribution service using satellites will be described with reference to FIG. In FIG. 1, 10 is a software supply company, 20 is an operation center, 30 is a program distribution center, 31 is a transmission device, and 35.
Is a current broadcasting station, 36 is a transmitting device, 40 is a satellite for distributing signals, 50 is a subscribing household, 51 is a receiving device, 52
Is a receiver decoder, 53 is a VTR, 54 is a television receiver, 55 is a telephone, and 56 is a receiving device.

The video distribution service is provided by an operator who operates the operation center 20. The operator contracts with the software supply company 10, and the required software is supplied from the software supply company 10 to the program distribution center 30.
Although only one software supply company 10 is shown in the embodiment shown in FIG. 1, software is normally supplied from a plurality of software supply companies.

The program distribution center 30 launches a radio wave toward a satellite 40 by means of a transmitter 31 provided in the center. The satellite 40 receives the radio wave and transmits the radio wave to the subscriber 50. The transmitted radio wave is received by the receiver 51. Although only one subscriber 50 is shown in the embodiment shown in FIG. 1, there are actually multiple subscribers.

The radio wave received by the receiver 51 is input to the receiver decoder 52, and the software of the channel selected by the receiver decoder 52 is selected. The selected software is recorded in the VTR 53 as needed. The signal recorded in the VTR 53 and reproduced at any time is the receiver / decoder 5
After being returned to 2, the original video signal is restored, and then output to the television receiver 54. When it is desired to view the image as it is without recording it, the image signal is restored to the original video signal without passing through the VTR 53 and then output to the television receiver 54.

The subscriber uses the telephone 55 to select the software he or she wants to see.
It is also possible to request transmission from the operation center 20. In addition, the operation center 20 can check the reception / viewing status of the subscriber 30 via the telephone line from the receiver / decoder 52, and can also charge according to the viewing / listening status.

In addition, from the current broadcasting station 35 to the transmission device 36.
The radio wave broadcast by is received by the receiving device 56, and the received signal is input and recorded in the VTR 53. The signal reproduced by the VTR 53 is input to the television receiver 54 and can be viewed. Of course, if the VTR 53 does not need to be recorded, the signal from the receiving device 56 is input to the television receiver 54 and can be viewed as it is.

FIG. 2 is a block diagram showing details of the program distribution center 30. In FIG. 2, 100 is an input means for the software sent from the software supply company 10, 101 is an input means for inputting a control signal such as a program sent from the operation center 20, and 110 is the software input from the input means 100. Receiving processing means for performing receiving processing according to 111,
120 and 131 are storage media such as digital VTRs,
112 is a switching device, 121 and 130 are bit compression devices, 140 is a transmission processing device, and 150 is a program control device.

From the software supply company 10 to the program distribution center 3
The program is supplied to 0 using an optical fiber, a coaxial line, or a line such as a satellite. In some cases, it is also possible to transport storage media such as VTR cassettes and optical discs. When the software is supplied via the line, it is input to the reception processing device 110 via the input means 100. The reception processing device 110 performs processing such as demodulation, error correction, and bit expansion on the signal input via the line as necessary. The output signal from the reception processing device 110 is input to the switching device 112 and the storage medium 120. In the storage medium 120, the input software is stored and stored in the medium of the storage medium 120. When the storage medium such as a VTR cassette and an optical disc is supplied from the software supply company 10 to the program distribution center 30 and supplied, it is reproduced on the storage medium 111 that matches the supply medium. The program reproduced on the storage medium 111 is input to the switching device 112.

The switching device 112 switches according to the input condition of the signal, and the output signal thereof is the bit compression device 130.
Is input to The bit compression device 130 is, for example, as described above.
Digital compression called MPEG-2 is performed to reduce the amount of data required for transmission. When the digitally compressed data is supplied from the software supply company 10, the bit compression device 130 can be omitted. The output signal of the bit compression device 130 is input to the storage medium 131.
As the storage medium 131, for example, a recordable / reproducible medium such as a digital VTR, an optical disc, a magnetic disc, or the like can be used.

From the operation center 20 to the input means 1
A control signal such as a program transmitted via 01 is transmitted to the program control device 15
Input to 0. The program transmission control signal from the program control device 150 is stored in the storage media 120, 131 and the transmission processing device 1.
40 is input. The necessary software is output from the storage media 120 and 131 according to this control signal. The software output from the storage medium 120 is the bit compression device 12
1 and, like the bit compression device 130, for example,
Digital compression called MPEG-2 is performed to reduce the amount of data required for transmission. The output signal of the bit compression device 121 is input to the transmission processing device 140. In addition, the signal output from the storage medium 131 is also transmitted to the transmission processing device 14.
Input to 0.

When the software supplied from the software supply company 10 is immediately transmitted, the storage medium 1
20 does not reproduce and output the software once recorded, but records the input signal to the storage medium 120 as necessary while recording the input signal to the storage medium 120.
May be output to.

Furthermore, if the software supplied from the software supply company 10 is already bit-compressed data, it is not necessary to go through the bit compression device 121 again. In the embodiment shown in FIG. 2, only two programs are input to the transmission processing device 140, but more devices can be connected. Further, although the processing for one transmission channel is shown, the storage media 120 and 131, the bit compression device 12
1. By having a plurality of devices including the transmission processing device 140, it is possible to send signals of a plurality of transmission channels.

If necessary, the transmission processing device 140 encrypts each program, packetizes them, time-division multiplexes a plurality of programs, adds error correction codes for transmission, and follows a control signal from the program control device 150. , Modulate so as to be a signal of a predetermined transmission channel and output. Transmission processing device 140
Is output to the transmitter 31. Transmitter 31
Sends a signal to the satellite 40 shown in FIG.

FIG. 3 is a block diagram of another embodiment showing the details of the program distribution center 30. 3 is partly common to FIG. 2, and the common parts are denoted by the same reference numerals and detailed description thereof will be omitted. In FIG. 3, 115 is a storage medium supply device, 160 to 163 are storage media, and 170 to 173.
Is a bit compression device, 180 is a transmission processing device, 190 is a program control device, and 191 is a program guide generation device.

The embodiment shown in FIG. 3 shows the case where the software is supplied from the software supply company 10 shown in FIG. In this case, the terminal 100 merely indicates the receiving point of the storage medium to the program distribution center 30. The received storage medium is stored in the storage medium supply device 115, and the storage media 160 to 163 are controlled by the program control device 190.
Supply the storage medium to. The signals reproduced on the storage media 160 to 163 are bit compression devices 170 to 17 respectively.
3 and bit-compressed according to the MPEG-2 standard or the like, and the output signal is input to the transmission processing device 180.

A control signal such as a transmitted program is input from the operation center 20 to the program control device 190 via the input means 101. A program transmission control signal from the program control device 190 is input to the storage medium supply device 115, the storage media 160 to 163, and the transmission processing device 140. According to this control signal, as described above, the storage medium in the storage medium supply device 115 is supplied to the storage media 160 to 163, and the software of the storage media 160 to 163 is reproduced.
Stop etc. is controlled.

Also, from the program distribution center 30 to the subscribing household 5
The guide information of the program distributed to
It is generated by the program guide generation device 191 according to the information from 0 and input to the transmission processing device 180. Transmission processing device 1
At 80, for example, signal processing for transmission according to the above-mentioned MPEG transmission standard is performed. The transmission processed signal is transmitted by the transmission device 3
1 is output to the satellite 40 from the transmission device 31.

FIG. 4 is a block diagram showing an example of signal processing in the transmission processing device 180. In FIG. 4, 170
a to 173a, 190a, 191a are input terminals,
170b to 173b and 31a are output terminals and 181 respectively.
184 is an encryption device, 185 is a time division multiplexing device, 1
86 is an error correction code addition device, and 187 is a modulation device.

In FIG. 4, the signals from the bit compression devices 170 to 173 are input to the encryption devices 181 to 184 via the input terminals 170a to 173a, respectively. Encryption device 1
At 81 to 184, each input program is encrypted as necessary. This encryption may be performed on the video signal only, the audio signal only, or both the video signal and the audio signal. The encrypted signal is input to the time division multiplexer 185. The terminal 190a is an input terminal for a signal from the program control device 190, and a viewing right control signal of each program is input to the time division multiplexing device 185. This signal consists of a signal indicating whether each subscriber has the right to view the broadcasted signal. Further, the program guide information from the program guide generator 191 is also input to the time division multiplexer 185. Then, each signal is packetized into a predetermined format, compressed in the time axis direction and multiplexed. In the present embodiment, the viewing right control signal and the program guide information are shown without the encryption device, but these may also be encrypted.

Also, rate control information of each program is input from the terminal 190a. This is because, for example, the program input from the bit compression device 170 is bit-compressed in the range of 4 to 8 Mbps, and the program input from the bit compression device 171 is 2 bits.
It is information such as bit compression in the range of up to 6 Mbps. Based on this information, the time division multiplexer 185 controls the bit rates of the bit compressors 170 to 173. Output terminals 170b to 173b from the time division multiplexer 185.
A control signal is output to the bit compression devices 170 to 173 via. With this, the bit rate of each program is controlled so that the signal rate after time division multiplexing becomes equal to or lower than a certain rate.

The output signal of the time division multiplexer 185 is input to the error correction code addition device 186. Here, for example, an error correction code for correcting a transmission error caused by noise in a satellite line, a CATV line, etc. is added. The output signal of the error correction coding device is input to the modulation device 187,
In the case of the embodiment shown in FIG. 3, the programs of four channels are modulated into a single carrier to form one transmission channel. The signal modulated into the single carrier is output to the transmitting device 31 via the terminal 31a.

The output signal of the transmission processing device 180 is input to the transmission device 31. The subsequent operation is similar to that of the embodiment shown in FIG. In the embodiment shown in FIG. 3, four storage media are provided and four programs can be input to the transmission processing device 180. However, many storage media may be provided and more programs may be time-division multiplexed. .

In the embodiment shown in FIG. 3, the processing for one transmission channel is shown, but the storage media 160 to 163,
It is also possible to send signals of a plurality of transmission channels by having a plurality of combinations of the bit compression devices 170 to 173 and the transmission processing device 180.

Here, the transmission channel means a signal obtained by time-division-multiplexing a plurality of programs and modulating with a single carrier as described above, and each of the plurality of programs is simply called a channel.

FIG. 5 shows a concrete example of the configuration of the receiver / decoder in the subscribing household 50. In FIG. 5, 200 is an input terminal for a signal from the receiving device 51, 201 is a signal for requesting software to the operation center,
A signal input / output terminal for exchanging signals for knowing the reception status of pay broadcasting, 202 is a restored signal output terminal, 203 is a VTR signal input / output terminal, and 205 is the receiving apparatus shown in FIG. Input terminal of signal from 56, 210 is tuner, 220 is error correction circuit, 230 is program division circuit, 240 is switching circuit, 250 is encryption / decryption circuit, 2
Reference numeral 60 is a decoding circuit for decompressing bits, 270 is a signal output processing circuit, 280 is a control circuit, and 290 is an interface circuit.

Receiving device 5 that receives the signal from satellite 40
1 inputs a reception signal to the tuner 210 via the terminal 200. The tuner 210 selects the signal of the transmission channel of the program to be watched from the received signal according to the control signal from the control circuit 280, demodulates the signal modulated by the modulation device 187 in the transmission processing devices 140 and 180, and corrects the error correction circuit. Output to 220. The error correction circuit 220 mainly corrects an error generated in the line according to the error correction code added by the error correction code addition device 186 in the transmission processing devices 140 and 180. The error-corrected signal is the program division circuit 23.
Input to 0. The program division circuit 230 selects and outputs a desired program from a plurality of programs time-division multiplexed by the time-division multiplexer 185 of the transmission processing devices 140 and 180 on one transmission channel in accordance with a control signal from the control circuit 280. To do.

The output signal of the program division circuit 230 is input to the switching circuit 240 and the interface circuit 290, and further input to the VTR 53 via the output terminal 203. VTR
At 53, the input digital bit stream is recorded, and at the time of reproduction, the interface circuit 290 is input through the input terminal 203 in the same form as the input bit stream.
Is input to The output signal of the interface circuit 290 is input to the switching circuit 240. Switching circuit 240
In response to the control signal from the control circuit 280, the signal from the program division circuit 230 is selected and output when the received signal is restored, and the interface circuit when the reproduction output signal of the VTR 53 is selected and output. The signal from 290 is selected and output.

The output signal of the switching circuit 240 is input to the encryption / decryption circuit 250. In the encryption / decryption circuit 250, the encryption devices 181 to 18 in the transmission processing circuits 140 and 180 are included.
4. Decrypt the signal encrypted at 4. Encryption / decryption circuit 250
The decrypted signal output from the decrypted signal is the decryption circuit 260.
Input to the bit compression devices 121 and 13 shown in FIG.
0, the bit compression devices 160 to 163 shown in FIG. 3 or the bit compression performed by the software supply company 10 shown in FIG. 1 are decoded and expanded.

The signal decompressed by the decoding circuit 260 is input to the output processing circuit 270 as a component signal composed of a luminance signal and two color difference signals. Output processing circuit 27
At 0, the two input color difference signals are subjected to quadrature two-phase modulation and converted into a carrier color signal, and the obtained carrier color signal and luminance signal are output. The output signal is input to the television receiver 54 via the output terminal 202. Since the television receiver 54 has only a composite input terminal, the output processing circuit 270
May output the composite signal by adding the luminance signal and the carrier color signal. Further, all of the signal including the luminance signal and the carrier color signal and the composite signal may be output.

The signal from the receiving device 56 input from the input terminal 205 is recorded by the VTR 53 as needed,
When no reproduction signal or recording is performed, an input signal or a signal equivalent to the input is output to the television receiver 54. In the embodiment shown in FIG. 5, the signal before encryption / decryption is VTR53.
Since it is recorded in the VTR 53, it is not always necessary to perform the decryption at the time of recording in the VTR 53, and therefore, the recording process is free at the time of recording, and the charging process can be performed every time it is reproduced.

FIG. 6 shows another embodiment of the receiver decoder shown in FIG. FIG. 6 is partially common to the embodiment shown in FIG. 5, the common parts are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the embodiment shown in FIG. 6, the switching circuit 240 is moved after the encryption / decryption circuit 250 as compared with the embodiment shown in FIG. That is, the output signal of the encryption / decryption circuit 250 is VTR5.
3 and the switching circuit 240, and the output signal of the VTR 53 is input to the switching circuit 240. Then, the output signal of the switching circuit 240 is input to the decoding circuit 260.

In the embodiment shown in FIG. 6, the encryption / decryption circuit 25
This is a case of recording a signal which is encrypted and decrypted by 0. In this case, since the encrypted and decrypted signal is recorded in the VTR, the billing process for the decryption is performed at the time of recording, and at the time of reproduction, reproduction can be performed without being charged.

In the embodiment shown in FIG. 6, the encryption / decryption circuit 250 is provided after the program division circuit 230, but the program division processing may be performed after the encryption / decryption is performed first.

FIG. 7 is a block diagram showing an embodiment of the VTR 53. 7, 300 is an input / output terminal of a signal from the receiver decoder 52 shown in FIG. 1, 302 is an input terminal of a signal from the receiver 56 shown in FIG. 1, 303 is an output terminal thereof, 305 is an interface circuit, 311 is Parity addition circuit, 312 modulation circuit, 320 tape transport system, 330 demodulation circuit, 331 error correction circuit, 340 analog video signal recording processing circuit, 350 analog video signal reproduction processing circuit, 360 analog audio signal The recording processing circuit 370 is an analog audio signal reproduction processing circuit.

The signal input from the input terminal 300 is supplied to the parity adding circuit 311 via the interface circuit 305.
Is input to The parity adding circuit 311 adds a parity code for correcting an error generated in the tape transport system 320. The output signal of the parity addition circuit 311 is input to the modulation circuit 312. The modulation circuit 312 modulates the digital signal into a form suitable for the tape transport system 320. Examples of modulation methods are NRZ, NRZI, 8
-10 conversion, MFM, M2 and other methods are known. The modulated signal is input to the tape transport system 320 and recorded on the magnetic tape.

During reproduction, the reproduced signal is the demodulation circuit 3
The signal is input to 30, and demodulation corresponding to the modulation circuit 312 is performed. The output signal of the demodulation circuit 330 is an error correction circuit 331.
The error generated in the tape transport system 320 is corrected on the basis of the parity code input to the parity adder 311 and added to the parity adder 311. The output signal of the error correction circuit 331 is input to the interface circuit 305, and the input terminal 300
After being converted into a signal of the same format as the signal input from, it is output from the terminal 300. The signal output from the terminal 300 is input to the receiver decoder 52 shown in FIG.

As shown in the embodiment of FIG. 7, the bit compression devices 121 and 130 as shown in FIG. 2 are not required inside the VTR 53, and a digital signal recording VTR having a small circuit scale can be realized. Further, since it is not necessary to have a bit compression device inside each VTR, and it is sufficient to have it in the software supply company 10 or the program distribution center 30, the circuit scale becomes large and the price becomes large, but a high performance bit compression device. Can be used, and the bit compression rate can be relatively large, so that the data rate of the digital signal to be transmitted can be reduced. Therefore, the VTR 53 used by the subscriber is capable of high image quality, low price, and long-time recording.

Further, the analog signal from the receiving device 56 is input from the terminal 302, and is input to the analog video signal recording processing circuit 340 and the analog audio signal recording processing circuit 360. Here, for example, VHS standard, β standard, 8 mm V
Signal processing such as TR standard is performed. The processed signal is input to the tape transport system 320. In the tape transport system 320, signals are recorded according to each format as in the conventional VTR.

At the time of reproduction, the tape transport system 32
The signal reproduced by 0 is the analog video signal reproduction processing circuit 3
50 and an analog audio signal reproduction processing circuit 370, and reproduction signal processing corresponding to the analog video signal recording processing circuit 340 and the analog audio signal recording processing circuit 360 is performed. The reproduced signal is appropriately output terminal 303
Is input to the television receiver 54 shown in FIG. As a result, digital broadcasting and conventional analog broadcasting can be recorded using the same tape transport system.

FIG. 8 is a schematic diagram showing an example of a signal output from the transmitter 31 (or an output signal of the output terminal 31a shown in FIG. 4) in the embodiment shown in FIG. 2 or FIG.
In the embodiment shown in FIG. 8, in accordance with the embodiment shown in FIG.
The case where four programs are transmitted by one transmission channel is shown. Also, the transmission channels are shown for the case of n transmission channels (1) to (n). In FIG. 8, V1, V2,
V3 and V4 are video signals of four programs, A1, A2, A3,
A4 is an audio signal of each of the four programs, PG is a signal indicating program guide information, and VECM and AECM are control signals indicating the right of viewing. And each shall represent the signal of one packet.

In the embodiment shown in FIG. 3, the four programs generally have different transmission rates. In addition, when viewed instantaneously, the amount of data increases or decreases.
In order to control this efficiently, each information is packetized and time-division multiplexed as shown in FIG. The details of the signals in the packet are described in the transmission standards mentioned above. Although not shown in detail in the schematic diagram shown in FIG. 8, as described with reference to FIG. 4, the signals in each packet are encrypted by the encryption devices 181 to 184 as necessary, and error correction is performed. The error correction code is added by the code addition device 186,
Header information such as a synchronization signal is added to the time division multiplexer 185.

In the embodiment shown in FIGS. 5 and 6, the terminal 200
8 (1) ... (n) are input, and the tuner 210 selects one of the transmission channel signals. Here, it is assumed that FIG. 8 (1) is selected.
The selected signal shown in FIG. 8A is the error correction circuit 220.
Is error-corrected and input to the program division circuit 230. It is assumed that the program shown in Appendix 1 is selected from the four programs which are time-division multiplexed in the program division circuit 230.
At this time, the program guide information PG and the viewing right control signals VECM and AECM are separately output at the same time as the video signal V1 and the audio signal A1. FIG. 9 (2) shows the signal obtained by dividing the program. Figure 9
(1) is a rewrite of FIG. 8 (1).

The switching circuit 2 in the embodiment shown in FIGS.
First, a case where the signal 40 from the tuner 210 is directly selected instead of the reproduced signal from the VTR 53 will be described. Figure 9
The program-divided signal shown in (2) is the decryption circuit 250.
Is encrypted and decrypted. This is performed based on the viewing right control signals VECM and AECM signals shown in FIG. 9 (2). That is, if the subscribing household has the right to view the selected program, the code is decrypted. If the household does not have the right to view, the code is not decrypted, and it is clearly stated that the right to view is not available. The information indicating how to obtain the right is output from the terminal 202. The output of this information is so-called OSD, and the output processing circuit 270 adds this information to the video signal and outputs it.

The encrypted and decrypted signal is input to the decryption circuit 260. The decoding circuit 260 includes bit compression devices 121 and 130 shown in FIG. 2 and bit compression devices 170 to 17 shown in FIG.
It corresponds to 3 and decodes an input signal according to the MPEG-2 standard, for example. When decoding a signal compressed by the MPEG standard, it is necessary to synchronize the transmitted signal with the data to be decoded. This is because, for example, if the transmitted signal and the data to be decoded are not synchronized, and if the decoding speed is faster than the transmission speed, the data will be insufficient and decoding will not be possible. For this reason, in the MPEG standard, a time reference reference value called PCR or SCR is added to the packet. At the time of decoding, the clock signal for decoding is restored based on this time reference value. This is shown, for example, in "Point Illustrated Latest MPEG Textbook (ASCII Co., Ltd., first edition issued on August 1, 1994)".
Therefore, the arrival time of the packet cannot be changed.

Therefore, in order to record the selected signal shown in FIG. 9 (2) in the VTR 53, it is necessary to devise a means for reproducing the packet while maintaining the time interval of the input packet.

As the input signal of the interface circuit 290, the signal corresponding to FIG. 9 (2) is input. As an example, the signal rate of the signal output from the transmission device 31 shown in FIGS. 2 and 3 is 40 Mb / s. Of these, 7/6 for error correction
It is assumed that 17 bytes of header information is added to 130 bytes of the packet compressed by the bit compression device. In this case, the error correction circuit 2 shown in FIGS.
In the state in which the header information necessary for transmission is removed by error correction at 20, it becomes about 30 Mb / s as represented by the following equation.

40 × (6/7) × (130/147) = 30.3 (Equation 1) As shown in FIG. 9 (2), there is a portion where packets are continuously present, and an interval for several packets is set. There is also a part that exists. In order to record on the VTR 53 while maintaining the time interval of this signal, it is necessary to record at a rate higher than the rate shown in (Equation 1). As shown in FIG. 9 (2), there is a period during which no packet is sent, so if the packets can be recorded together and returned to the original time interval during reproduction, the recording rate will be the value shown in (Equation 1). Can be smaller than Figure 9
(3) is for packing and recording packets at the time of recording and for returning to the original time interval at the time of reproduction,
From the interface circuit 290 in FIGS. 5 and 6 to the VTR
The signal output to 53 is shown.

FIG. 9 (3) shows a signal input from the program division circuit 230 in the embodiment shown in FIG. 5 to the interface circuit 290 from the encryption / decryption circuit 250 in the embodiment shown in FIG. The interface circuit 290 adds information (time stamp) indicating the time when the packet arrives to the input signal as header information. Information other than the time stamp may be further added as header information, if necessary. Further, in order to add header information such as a time stamp to the input signal of the interface circuit 290 shown in FIG. 9B, it is necessary to increase the packet transmission rate. FIG. 9 (3) schematically shows it. That is, in (3), one packet is transmitted in a shorter time than the transmission time of one packet shown in FIG. 9 (2).

FIG. 10 shows an embodiment of a circuit for adding a time stamp. Reference numeral 400 denotes a clock signal input terminal for counting time stamps, 401 denotes a packet signal input terminal shown in FIG. 9B, 402 denotes a time stamped signal output terminal, 410 denotes a counting circuit, and 411 denotes a latch. Reference numeral 420 is a memory, 430 is a packet head detection circuit, 431 is a memory control circuit, 440 is a multiplexing circuit, and 450 is a delay circuit.

The packet signal shown in FIG. 9B is input from the terminal 401, and is input to the memory 420 and the packet head detection circuit 430. The packet head detection circuit 430 detects the head of the packet of the input signal, and the detection signal is input to the latch circuit 411, the control circuit 431, and the delay circuit 450. On the other hand, the clock signal input from the terminal 400 is input to the counting circuit 410 and continuously counts the clock signal. The output signal of the counting circuit is input to the latch circuit 411. The latch circuit 411 latches the input count value with the packet head signal from the packet head detection circuit 430. The latched count value is input to the multiplexing circuit 440. This count value becomes the time stamp information of the packet.

A control signal for the memory 420 is created based on the packet head detection signal input to the control circuit 431.
The write clock of the memory 420 uses the clock signal input from the terminal 404. For this, the one that matches the packet signal frequency input from the terminal 401 is used. The clock signal input from the terminal 403 is used as the read clock of the memory 420. This clock signal frequency is selected to be higher than the write clock frequency input from the terminal 404. As an example, when the write clock frequency is (Formula 1) and is 30.3 MHz, the read clock frequency is 49.152 MHz. This read clock becomes the bus clock frequency of the signal sent from the terminal 203 shown in FIGS. 5 and 6 to the VTR 53. At this time, as the clock signal of the counting circuit 410 input from the terminal 400, that is, the clock signal frequency for time stamp,
For example, the frequency is the same as the frequency of the clock signal input from the terminal 403. In this case, the same time stamp clock signal and bus clock signal input from the terminal 403 can be used. This does not limit the time stamp clock frequency to the same as the bus clock signal frequency.

After the packet is input to the memory 420,
Read from memory after a predetermined time. Since the frequency of the read clock signal is set higher than the frequency of the write clock signal, the transmission time of the output packet is made shorter than the transmission time of the input packet signal as shown in FIGS. 9 (2) and 9 (3). be able to. Therefore, even in a portion where packets are continuously transmitted, it is possible to obtain a period in which header information including time stamp information is added, as shown in FIG. 9C. The output signal of the memory 420 is the multiplexing circuit 44.
Input to 0.

The delay circuit 450 delays the packet head detection signal and outputs a gate signal indicating the position to which the time stamp signal is added according to the packet signal output from the memory 420. The gate signal is input to the multiplexing circuit 440, and the multiplexing circuit 440 adds the time stamp information from the latch circuit 411 according to the gate signal and outputs the signal shown in FIG. 9C from the terminal 402.

The signal shown in FIG. 9C is input to the VTR 53 via the terminal 203 shown in FIGS. Figure 11
(1) is a signal obtained by rewriting the signal corresponding to FIG. 9 (3), and P1, P2, ... Show packet signals to be input, respectively. In the VTR 53, as shown in FIG. 7, the packet signals P1, P2, ... Shown in FIG. 11A are input to the parity addition circuit 311 via the terminal 300 and the interface circuit 305. The parity adding circuit 311 has a memory (not shown) having a capacity for signals to be recorded on at least one track, and the packet signals P1, P2, ... Are stored in the memory. From the parity addition circuit 311 to FIG.
As shown in, the packet signal is output in a packed state. Between the packets of the input signal shown in FIG.
Although there is a gap as described with reference to FIG. 11, the packet signal is output in a state in which the packet signal interval is narrowed as shown in FIG. 11 (2). Therefore, the output signal rate is lower than the input packet signal rate. Can also be lowered. Therefore, the recording rate in the tape transport system 320 can be lowered. In FIG. 11, the input signal (1) and the output signal (2) are 1
Although the figure is shown in which the output is delayed for the track period, this is shown for convenience and the present invention is not limited to one track period, and the time required for signal processing may be delayed.

At the time of reproduction, the tape transport system 32
The signal reproduced and output from 0 is input to the error correction circuit 331 via the demodulation circuit 330. The signal input to the error correction circuit 331 is the packet signal P as in FIG.
Signals with 1, 1, P2, ... packed. Figure 11
(3) shows the reproduced input signal of the error correction circuit. The error correction circuit 331 also has a memory (not shown) having a capacity corresponding to a signal for one track period. Figure 11 (3)
The input signal shown in is input to the memory in the error correction circuit 331. FIG. 12 is a block diagram showing an embodiment of a time axis adjusting circuit for restoring the intervals of the reproduction packet signals P1, P2, ... FIG. 11 (4) shows the signal after the intervals of the reproduced packet signals P1, P2, ... Are restored.

In FIG. 12, 510 is the error correction circuit 3.
31 is a memory, reference numeral 500 is an input terminal of the memory 510, 5
20 is a memory, 501 is a read clock input terminal of the memory 520, 502 is a write clock input terminal of the memory 520, 503 is a time axis adjusted signal output terminal, 551 is a counting circuit, and 504 is a clock of the counting circuit 551. A signal input terminal, 530 is a time stamp gate circuit, 540 is a control circuit, 550 is a time stamp reading circuit, 552 is a match detection circuit, 560 is a circuit block built in the error correction circuit 331, and 570 is built in the interface circuit 305. Circuit block.

The reproduction signal shown in FIG. 11C input from the terminal 500 shown in FIG. 12 is input to the memory 510. The signal output from the memory 510 for each packet of the packet signals P1, P2, ... Is input to the memory 520 and the time stamp reading circuit 550. Reading control of the memory 510, writing of the memory 520, and reading control are performed by control signals from the control circuit 540. A control signal from the control circuit 540 is also input to the time stamp reading circuit 550, a signal indicating the position of the time stamp signal is output with respect to the signal from the memory 510, and the time stamp signal at the correct position is read. The read time stamp signal is input to the coincidence detection circuit 552.

From the terminal 504, the terminal 400 shown in FIG.
A clock signal having the same frequency as that input from is input to the counting circuit 551. The counting circuit 551 counts the input clock signals and outputs the count value to the coincidence detection circuit 552. The coincidence detection circuit 552 outputs a coincidence signal when the two input signals coincide with each other, and inputs the coincidence signal to the control circuit 540.

The control circuit 540 reads the packet signal from the memory 520 based on the coincidence signal. Figure 11
The read signal is shown in (4). The reading is performed based on the read clock signal input from the terminal 501. At the same time, a new packet is input from the memory 510 and written in the memory 520 based on the write clock input from the terminal 502. The frequency of the clock signal input from the terminal 501 may be determined so as to correspond to the signal rate between the terminal 203 and the VTR 53 shown in FIGS.

The time-adjusted packet signals P1, P2, ... From the memory 520 are input to the time stamp gate circuit 530. The time stamp gate circuit 530 gates the time stamp signal as necessary, and fixes all the time stamp signals to 0 level or 1 level, for example. As shown in FIG. 11 (5), the terminal 300 shown in FIG.
A signal corrected at the same time interval as the signal shown in FIG. 11 (1) input from the terminal 503 is output from the terminal 503.

As described above, the signal having the same packet interval as shown in FIG. 9C is input to the interface circuit 290 from the terminal 203 shown in FIGS. The interface circuit 290 removes header information as necessary and inputs it to the switch circuit 240. As a result, the tuner 210 input from the other input terminal of the switch circuit 240 is input.
The same signal from can be recovered.

A VTR for recording a digital signal has a characteristic that image quality is not deteriorated even if dubbing is repeated because error correction is sufficiently performed as shown in FIG. However, on the other hand, if the dubbing is repeated without image quality deterioration, there is a fear that the rights of the copyright holder cannot be sufficiently protected. In order to avoid this, the present invention provides a technique in which dubbing cannot be performed.

As shown in FIG. 12, the time axis adjusted packet signals P1, P2, ... Output from the memory 520 are input to the time stamp gate circuit 530. In the time stamp gate circuit 530, as described above, all signals in the period corresponding to the time stamp shown in FIG. 9C are set to 0 level or 1 level, for example. As a result, FIG.
In the packet signals P1, P2, ... Of the output signals from the interface circuit 305 shown in FIG. Therefore, when the output signal from the terminal 300 is input to the VTR shown in FIG. 7 and recorded, the signal shown in FIG. 11C is reproduced, and even if the signal at the time stamp position included in each packet is read, It does not show the time interval, so it cannot be restored to the original time interval. When the signals at the positions corresponding to the time stamps are all 0 level or 1 level, one packet is read out by the circuit shown in FIG. 12 and the next packet is read out is the number of bits of the time stamp. After the time corresponding to, the number of bits of the time stamp is generally set to be longer than one track period. Therefore, before reading all packet signals from the memory 510, the signal of the next track is stored in the memory. Since it is written in 510, it is no longer possible to output a signal corresponding to the input signal. As a result, dubbing can be prohibited.

The above description is an example of the case where all the signals at the position corresponding to the time stamp are set to 0 level or 1 level, but at least the signal at the time stamp position is set by the time stamp gate circuit 530 shown in FIG. 1
Change the signal of one bit. As a result, even if the reproduced signal is recorded in the next VTR, it is no longer possible to return the packet position to the original position. As a result, dubbing can be prohibited.

As the header information added in addition to the time stamp shown in FIG. 9A, the signal at the position corresponding to the output time stamp is set to all 0 levels or 1 described above.
A signal for controlling whether to change the level or the signal of at least one bit may be added in advance by the receiver decoder, and the time stamp information may be changed by this control signal.

[0078]

According to the present invention, the input digital information can be efficiently recorded, and the reproduction of the reproduced signal can be easily prohibited.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital broadcasting and analog broadcasting system according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a program distribution center according to the present invention.

FIG. 3 is a block diagram showing an embodiment of a program distribution center according to the present invention.

FIG. 4 is a block diagram showing an embodiment of a transmission processing device according to the present invention.

FIG. 5 is a block diagram showing an embodiment of a receiver decoder according to the present invention.

FIG. 6 is a block diagram showing an embodiment of a receiver decoder according to the present invention.

FIG. 7 is a block diagram showing an embodiment of a VTR according to the present invention.

FIG. 8 is a waveform diagram of signals in the present invention.

FIG. 9 is a waveform diagram of signals in the present invention.

FIG. 10 is a block diagram showing an embodiment of a time information adding circuit according to the present invention.

FIG. 11 is a waveform diagram of signals in the present invention.

FIG. 12 is a block diagram showing an embodiment of a time information changing circuit according to the present invention.

[Explanation of symbols]

 52 ... Receiver decoder 53 ... VTR 121, 130, 171-173 ... Bit compression device 140, 180 ... Transmission processing device 181-184 ... Encryption device 185 ... Time division multiplexing device 186 ... Error correction code addition device 187 ... Modulation device 220, 331 ... Error correction circuit 230 ... Program division circuit 250 ... Encryption / decryption circuit 290, 305 ... Interface circuit 311 ... Parity addition circuit 530 ... Time stamp gate circuit

Continuation of front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H04N 7/24 H04N 7/13 Z 7/167 7/167 Z (72) Inventor Keiji Noguchi Inada, Hitachinaka City, Ibaraki Prefecture 1410 Hitachi, Ltd. Personal Media Equipment Division

Claims (6)

[Claims] 1. A recording / reproducing apparatus for recording a packet signal with time information, wherein digital information is packetized, and a packet signal with time information, to which time information of arrival of the packet is added, is input, and the packet signal with time information is recorded. A method for recording / reproducing a digital signal, wherein a packet signal with time information is reproduced from a reproducing device, and at least one bit of the time stamp information included in the reproduced packet signal is changed and output. 2. The digital information according to claim 1, wherein at least one of packetized video information, bit-compressed video information, bit-compressed audio information, video program information, and viewing permission information is included. How to record and reproduce signals. 3. A method for recording / reproducing a digital signal, wherein all the time stamp information contained in the regenerated packet signal is output as 0 level. 4. A recording / reproducing method for a digital signal, wherein all the time stamp information contained in the regenerated packet signal is output as one level. 5. A plurality of programs are respectively bit-compressed, the bit-compressed programs are respectively encrypted, the encrypted programs are packetized and time-division multiplexed, and the time-division multiplexed programs are made single. Modulating with a carrier, transmitting the modulated signal, receiving the transmitted signal, demodulating the received signal, selecting at least one program in packet form from the demodulated signal, A packet signal with time information, which is obtained by decoding the encryption of the selected packet format program and adding time information of arrival of the packet to each packet of the decrypted packet format signal, is input with the time information In the method for recording / reproducing the digital information for recording the packet signal, the packet signal with the recorded time information is reproduced, and is recorded in the reproduced packet signal. Method of recording and reproducing a digital signal and outputs by changing at least one bit of information in the time stamp information. 6. A recording / reproducing apparatus for recording a packet signal with time information, which is made by inputting a packet signal with time information, in which digital information is packetized, and time information of arrival of the packet is added for each packet. The reproducing apparatus has means for reproducing a packet signal with time information, and means for changing at least one bit of the time stamp information included in the reproduced packet signal. A digital signal recording / reproducing apparatus characterized by outputting.