JPH083017Y2 - Semiconductor device container - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a container for a semiconductor device.

[Conventional technology]

In a semiconductor device container, in order to electrically insulate the back surface of the semiconductor chip from the leads, a structure is used in which the insulating substrate is metallized and the leads are brazed. Beryllia, alumina, aluminum nitride, ceramics, etc. are used as the material of the insulating substrate, and the metallization of the substrate is formed by firing a thick film material such as Mo-Mn to a thickness of several tens of μm, and then the metallized surface Apply Ni plating around 10 μm and activate by sintering at 800-1000 ° C. The lead is usually an alloy system of iron and Ni, for example, Kovar or 42 alloy, which is brazed to the insulating substrate with Ag-Cu or the like. Generally, after this, Ni plating is applied (this will be referred to as secondary Ni plating), and then 0.2-5 μm Au plating is applied to form a semiconductor container. Considering the semiconductor chip mounting area, as shown in FIG. 4, the Si chip 27 is Au plated on the secondary Ni plating 25.
-Si eutectic part 26 will be attached. 1 is an insulating substrate, 2 is a thick metalized layer, 5 is a Ni sintering layer, and 25 is Ni
It is plating. Since the secondary Ni plating 25 is performed after the Ag-Cu brazing which is performed at about 780 ° C, the sintering cannot be performed at a higher temperature than the first Ni plating, and the sintering is performed at 400 to 600 ° C. The Ni-Si alloy is easily formed. When the Ni-Si alloy is formed, the adhesion between the semiconductor chip 27 and the insulating substrate 1 deteriorates, the thermal resistance deteriorates, and in the worst case, the chip 27 peels off. This phenomenon is caused by the 1994 National Conference of the Institute of Electronics and Communication Engineers, 352, "Countermeasures against Chip Delamination Failure of Ultra High Frequency Transistors and Temperature Dependence".
As a countermeasure against this, as shown in FIG. 5, a method in which the secondary Ni plating 25 is not applied to the mounting portion of the semiconductor chip 27 is adopted.

In order to realize the chip mounting structure as shown in FIG. 5, two types shown in FIGS. 2 (a), (b), (c) and FIGS. 3 (a), (b), (c) are conventionally used. The method of constructing the container of the semiconductor device has been used. 2 (a), (b),
(C) is a figure which shows an example of the conventional manufacturing method.
As shown in FIG. 3A, thick film metallization layers 2, 3 and 4 are formed on both front and back surfaces 1 of the insulating substrate, and Ni plating is applied to the surfaces thereof to form Ni sintering layers 5, 6 and 7. Next, as shown in FIG. 2 (b), the leads 8 and 10 are adhered by Ag-Cu brazing 12 and 13, and secondary Ni plating 17, 18 and 19 are partially applied. Au plating 20,2 on the entire metallized surface as shown in c)
Give 1,22. The chip mounting portion 24 is not subjected to secondary Ni plating, and the structure shown in FIG. 5 is realized.

FIG. 3 is a view showing another example of the conventional manufacturing method, and FIG. 3 (a) shows the same state as FIG. 2 (a). Next, as shown in FIG. 3 (b), the leads 8 and 10 are brazed with Ag-Cu 12,13.
Then, as shown in FIG. 3 (c), Au plating 20, 21, 22 is applied to the entire metallized surface. That is, the structure of FIG. 5 is realized by omitting the secondary Ni plating.

[Problems to be solved by the device]

The above-mentioned conventional methods for manufacturing a semiconductor container have the following drawbacks. In the conventional manufacturing method shown in FIG. 2,
Partial Ni plating must be applied in the step (b), but this requires the step of applying resin or resist to the semiconductor pellet mounting part as a plating mask and then removing the resin or resist after secondary Ni plating. This leads to an increase in manufacturing cost. Further, in the conventional manufacturing method shown in FIG. 3, since the leads 8 and 10 are directly plated with Au and there is no underlying Ni plating, Apr.1969 / SOLID STATE TECHNO-LOGY p
p36-38 “Stress Corrosion Cracking of Gold Plated K
It has a structure that causes stress corrosion of leads as reported in "ovar Transistor Leads".

SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide a semiconductor container that solves the structural cost increase due to partial Ni plating and the risk of stress corrosion due to the omission of lead base Ni plating.

[Means for solving the problem]

To achieve the above object, a semiconductor container according to the present invention comprises an insulating substrate formed by forming a Ni sintering layer on a thick film metallized layer, and a Ni-plated part. The parts subjected to are brazed on the insulating substrate except for the semiconductor chip mounting portion.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a view showing Embodiment 1 of the present invention.

In the figure, a thick metallization layer is formed on the front and back surfaces of the insulating substrate 1.
2,3,4 are selectively formed, and each thick film metallized layer 2,3,4
Ni sintering layers 5, 6 and 7 are formed on the top.

In the present invention, the iron-nickel alloy leads 8 and 10 are pre-plated with Ni, and the leads 8 and 10 are brazed 12 and 13 on the insulating substrate 1 (Fig. 1 (b), (See (c)).

Next, a method of manufacturing the container of the semiconductor device according to the present invention will be described.

First, as shown in FIG. 1A, the leads and the semiconductor chip mounting patterns are fired on the insulating substrate 1 with thick film metallization layers 2, 3 and 4 having a thickness of several tens of μm, and then the thick film metallization is performed. Ni plating is applied to the layers 2, 3 and 4 to a thickness of about 10 μm, and sintering is performed at 800 to 1000 ° C. to form Ni sintering layers 5, 6 and 7.

Next, as shown in FIG. 1 (b), a pre-plated Ni of about 1 to 20 μm 9 or 11 is used for iron bars such as kovar or 42 alloy.
Leads 8 and 10 made of a Ni-based alloy are brazed 12 and 13 to Ag-Cu solder at the lead connection points except the semiconductor chip mounting portion 24 of the insulating substrate.

Finally, as shown in FIG. 1 (c), Au plating 14, 15, 16 is applied to the metallized surface and the entire lead. The container of the semiconductor device manufactured in this way has the structure shown in FIG. 5 without the secondary Ni plating in the semiconductor chip mounting portion 24, and the place where the leads 8 and 10 on the insulating substrate are connected is the underlying Ni plating + Au. It has a plated structure.

As described above, according to the present invention, a pre-Ni-plated iron-Ni alloy lead is Ag-Cu brazed to an insulating substrate with a Ni sintering layer formed on a thick metalized layer, so that it can be mounted on a semiconductor chip mounting portion. Is a metallized structure without secondary Ni plating, and the lead part has an underlying Ni + Au plated structure.
It can be formed without using the complicated and costly process of partial Ni plating. Further, according to the present invention, it is possible to structure the container of the semiconductor device which suppresses the manufacturing cost, does not cause the chip peeling failure, and improves the stress corrosion resistance of the lead.

(Embodiment 2) FIG. 6 is a longitudinal sectional view showing Embodiment 2 of the present invention. In this embodiment, the metallic heat dissipation plate 29 such as Cu or Cu-W is a spare.
Similar to the leads 8 and 10 with the Ni plating 9 and 11, they are pre-plated with Ni and then brazed with Ag-Cu on the secondary Ni plating 28. This embodiment is essentially the same as that of FIG. 1, but regardless of the appearance difference such as mounting a heat sink,
It shows that the present invention can be implemented.

[Effect of device]

As described above, according to the present invention, since the base plating is present, stress corrosion is not caused, and
Since the parts to be brazed are pre-plated with Ni, it is possible to omit a complicated plating process such as Ni plating using a resin or a resist as a mask on the substrate, and it is possible to reduce the manufacturing cost. .

[Brief description of drawings]

1 (a), (b), and (c) are sectional views showing Embodiment 1 of the present invention in the order of manufacturing steps, and FIGS. 2 (a), (b), and (c).
3 (a), (b), and (c) are cross-sectional views showing a conventional example in the order of manufacturing steps, and FIG. 4 is a vertical cross-sectional view showing the case where secondary Ni plating is provided on the mounting portion of the Si chip. FIG. 5 is a sectional view showing a metallized structure without Ni plating, and FIG. 6 is a sectional view showing a second embodiment of the present invention. 1 ... Insulating substrate, 2,3,4 ... Thick film metallization layer 5,6,7 ... Ni sintering layer, 8,10 ... Lead 9,11 ... Ni plating on lead 12,13 ...... Ag-Cu brazing 14,15,16,20,21,22,23 …… Au plating 17,18,19,28 …… Secondary Ni plating 24 …… Semiconductor chip mounting part, 26 …… Au-Si Crystal part 27 …… Semiconductor chip, 29 …… Heat sink

Claims (1)

[Scope of utility model registration request] 1. An insulating substrate having a Ni sintering layer formed on a thick metallized layer and a Ni-plated part, wherein the Ni-plated part is a semiconductor on the insulating substrate. A container for a semiconductor device, characterized by being brazed to a portion excluding a chip mounting portion.