JPH08308094A - Circuit breaker apparatus - Google Patents

Circuit breaker apparatus

Info

Publication number
JPH08308094A
JPH08308094A JP12702595A JP12702595A JPH08308094A JP H08308094 A JPH08308094 A JP H08308094A JP 12702595 A JP12702595 A JP 12702595A JP 12702595 A JP12702595 A JP 12702595A JP H08308094 A JPH08308094 A JP H08308094A
Authority
JP
Japan
Prior art keywords
current
load
igbt
current path
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12702595A
Other languages
Japanese (ja)
Inventor
Tatsuya Murofushi
達也 室伏
Katsuhisa Kato
勝久 加藤
Toshihiko Onozawa
俊彦 小野沢
Shunichi Matsuda
俊一 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Japan Ltd
Original Assignee
Sony Tektronix Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Tektronix Corp filed Critical Sony Tektronix Corp
Priority to JP12702595A priority Critical patent/JPH08308094A/en
Priority to US08/639,180 priority patent/US5637990A/en
Publication of JPH08308094A publication Critical patent/JPH08308094A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/12Modifications for increasing the maximum permissible switched current
    • H03K17/127Modifications for increasing the maximum permissible switched current in composite switches
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10Modifications for increasing the maximum permissible switched voltage
    • H03K17/107Modifications for increasing the maximum permissible switched voltage in composite switches

Landscapes

  • Emergency Protection Circuit Devices (AREA)
  • Protection Of Static Devices (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE: To prevent generation of noise by suppressing a sudden change of current at the time of cutting off the current flowing into a current path of a load. CONSTITUTION: Output current paths of IGBT 10 to 16 are inserted into a current path of a load 20. Upon detection of a current higher than the predetermined current in the current path of the load, detecting means 22 to 26 change an output signal status. Control means 28 to 48 control IGBT to the conductive condition under the normal condition and when the detecting means controls such IGBT to the non-conductive condition after IGBT is saturated when the output signal status is changed. Namely, when IGBT is saturated, a current flowing into this IGBT becomes a constant current. Therefore, when an over- current flows into the load, such current sequentially increases and becomes constant for a certain period and thereafter it is decreased. Thereby, a sudden change can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、負荷に過大電流が流れ
た際に、負荷の電流路を遮断するブレーカ装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a breaker device for breaking a current path of a load when an excessive current flows through the load.

【0002】[0002]

【従来の技術】例えば、半導体測定装置において、パワ
ーMOSFETや、絶縁ゲート・バイポーラ・トランジ
スタなどの大電流半導体素子の短絡試験を行う場合、コ
レクタ及びエミッタ間の電圧を順次上昇させ、コレクタ
及びエミッタ間が短絡する状態を試験する。ここで、被
試験半導体素子が短絡すると、過大電流が半導体測定装
置に流れ、半導体測定装置自体を破壊する可能性があ
る。なお、この場合、被試験半導体素子が、電流路にお
ける負荷となる。また、負荷がモータの場合、このモー
タの故障により主電流路の両端間が短絡すると、過大電
流が流れ、モータ制御回路を破壊する可能性がある。
2. Description of the Related Art For example, in a semiconductor measuring device, when conducting a short-circuit test for a high-current semiconductor element such as a power MOSFET or an insulated gate bipolar transistor, the voltage between the collector and the emitter is increased in order to increase the voltage between the collector and the emitter. Test for short circuit. Here, if the semiconductor device under test is short-circuited, an excessive current may flow into the semiconductor measuring device, which may damage the semiconductor measuring device itself. In this case, the semiconductor device under test becomes a load in the current path. Further, when the load is a motor, if a short circuit occurs between both ends of the main current path due to a failure of the motor, an excessive current may flow and the motor control circuit may be destroyed.

【0003】このように種々の電気回路において、負荷
の短絡や地落(負荷の電流路が接地に落ちる)により過
大電流が流れると、負荷自体を更に破壊したり、負荷の
周辺回路や制御回路も破壊する可能性がある。よって、
負荷に過大電流が流れた場合、負荷の電流路を瞬時に遮
断するブレーカ装置が必要となる。なお、家庭用のブレ
ーカ装置は、電磁リレーを用いており、高速な遮断動作
には適さない。
As described above, in various electric circuits, when an excessive current flows due to a short circuit of the load or a ground drop (the current path of the load drops to the ground), the load itself is further destroyed, and peripheral circuits and control circuits of the load. Can also be destroyed. Therefore,
If an excessive current flows through the load, a breaker device that instantaneously cuts off the current path of the load is required. Note that the home breaker device uses an electromagnetic relay and is not suitable for high-speed breaking operation.

【0004】過大電流に対して瞬時に遮断を行う従来の
ブレーカ装置の1つに、ラピット・ヒューズやスーパー
・ラピット・ヒューズがある。しかし、これら特殊なヒ
ューズは、高価であり、1回ずつの使い捨てとなる。特
に、半導体素子の短絡試験のように、その度毎に過大電
流が流れる場合は、非常に不経済となる。
A rapid breaker or a super rapid fuse is one of conventional breaker devices for instantaneously breaking off an excessive current. However, these special fuses are expensive and are single-use disposables. In particular, when an excessive current flows each time as in a short circuit test of a semiconductor device, it becomes very uneconomical.

【0005】従来の別の高速ブレーカ装置には、本願出
願人が提案している絶縁ゲート・バイポーラ・トランジ
スタ(IGBT)を用いたブレーカ装置がある。このI
GBTブレーカ装置では、N個のIGBTを並列に配置
し、各IGBTのコレクタ及びエミッタ間の主電流路を
負荷の電流路に挿入する。また、各IGBTのゲートに
は、制御回路からのゲート・バイアス電圧が供給され、
常態でIGBTを導通常態にする。よって、各IGBT
には、負荷に流れる電流の約N分の1の電流が流れるの
で、全体として大電流に耐えられる。負荷の電流路に挿
入された小抵抗器が負荷に流れる電流を電圧に変換し、
この電圧が基準値を超えた場合を過大電流として、制御
回路に各IGBTを非導通にさせる。なお、N個のIG
BTの組合せを複数組だけ直列接続にすれば、IGBT
全体としての耐圧を高くできる。このIGBTブレーカ
装置は、何度でも使用でき非常に経済的である。
Another conventional high-speed breaker device is a breaker device using an insulated gate bipolar transistor (IGBT) proposed by the present applicant. This I
In the GBT breaker device, N IGBTs are arranged in parallel, and the main current path between the collector and the emitter of each IGBT is inserted in the current path of the load. The gate bias voltage from the control circuit is supplied to the gate of each IGBT,
In the normal state, the IGBT is guided to the normal state. Therefore, each IGBT
Since about 1 / N of the current flowing through the load flows through the device, it can withstand a large current as a whole. A small resistor inserted in the current path of the load converts the current flowing in the load into a voltage,
When this voltage exceeds the reference value, an excessive current is used to cause the control circuit to make each IGBT non-conductive. In addition, N IG
If multiple BT combinations are connected in series, the IGBT
The withstand voltage as a whole can be increased. This IGBT breaker device can be used many times and is very economical.

【0006】[0006]

【発明が解決しようとする課題】図4は、上述のIGB
Tブレーカ装置の動作を示す図である。なお、この図で
は、横軸が時間で、縦軸がIGBTブレーカ装置及び負
荷に流れる電流を示す。IGBTブレーカ装置が導通状
態で、負荷に電源電圧を供給すると通常電流Isが流れ
始める。時点t0にて負荷が短絡又は地絡すると、電流
路のインダクタンス成分や抵抗成分で決まる傾斜で電流
が増加し始める。時点t1にて、電流がIsat に達する
と、負荷電流路の電流検出用抵抗器の電圧降下も所定値
に達して、制御回路がIGBTを非導通にするので、電
流が急激に低下していく。
FIG. 4 shows the above-mentioned IGB.
It is a figure which shows operation | movement of T breaker apparatus. In this figure, the horizontal axis represents time and the vertical axis represents current flowing through the IGBT breaker device and the load. When the IGBT breaker device is in the conductive state and the power supply voltage is supplied to the load, the normal current Is starts to flow. When the load is short-circuited or grounded at time t0, the current starts to increase with a slope determined by the inductance component and the resistance component of the current path. When the current reaches Isat at the time point t1, the voltage drop of the current detection resistor in the load current path also reaches a predetermined value, and the control circuit makes the IGBT non-conductive, so that the current rapidly decreases. .

【0007】この従来のIGBTブレーカ装置の場合、
図4に示すように、遮断時点t1にて、電流が増加から
減少に急激に変換するため、スパイク・ノイズが発生し
て、負荷の制御回路や周辺回路を誤動作させたり、破壊
させる可能性がある。また、負荷がまだ破壊されていな
い場合は、その負荷自体が破壊される可能性もある。
In the case of this conventional IGBT breaker device,
As shown in FIG. 4, at the cutoff time t1, the current is rapidly converted from an increase to a decrease, so that spike noise may occur, and the load control circuit and peripheral circuits may malfunction or be destroyed. is there. Also, the load itself may be destroyed if the load is not yet destroyed.

【0008】したがって、本発明の目的は、負荷の電流
路に流れる電流を遮断する際に、電流の急激な変化を防
止するブレーカ装置の提供にある。
Therefore, an object of the present invention is to provide a breaker device which prevents a sudden change in the current when the current flowing in the current path of the load is cut off.

【0009】[0009]

【課題を解決するための手段】本発明は、負荷に過大電
流が流れた際に、負荷の電流路を遮断するブレーカ装置
であり、半導体素子の出力電流路が負荷の電流路に挿入
されている。検出手段は、負荷の電流路に所定電流以上
が流れたことを検出すると、出力信号状態を変化させ
る。制御手段は、通常状態で半導体素子を導通状態に制
御し、検出手段の出力信号状態が変化すると、半導体素
子を飽和状態にした後に半導体素子を非導通状態に制御
する。すなわち、半導体素子が飽和状態になると、この
半導体素子に流れる電流が定電流となる。よって、負荷
に過大電流が流れる場合、その電流は、順次増加し、あ
る期間一定値となり、その後減少することになるので、
図4に示すような急激な電流変化を防止できる。急激な
電流変化がなくなるため、スパイク・ノイズの発生も防
止できる。
SUMMARY OF THE INVENTION The present invention is a breaker device for shutting off a current path of a load when an excessive current flows through the load, and an output current path of a semiconductor element is inserted in the current path of the load. There is. The detection means changes the output signal state when it detects that a predetermined current or more has flowed in the current path of the load. The control means controls the semiconductor element to be in a conductive state in a normal state, and when the output signal state of the detection means changes, controls the semiconductor element to be in a non-conductive state after the semiconductor element is saturated. That is, when the semiconductor element is saturated, the current flowing through this semiconductor element becomes a constant current. Therefore, when an excessive current flows through the load, the current increases sequentially, becomes a constant value for a certain period, and then decreases.
It is possible to prevent a rapid current change as shown in FIG. Since sudden current changes disappear, spike noise can be prevented.

【0010】[0010]

【実施例】図1は、本発明の好適な実施例のブロック図
である。この実施例では、半導体素子であるIGBTを
m行n列(m=2、n=2)に配置しており、IGBT
10及び12のコレクタ同士及びエミッタ同士を夫々相
互接続して、並列にする。また、IGBT14及び16
のコレクタ同士及びエミッタ同士も夫々相互接続して、
並列にする。IGBT10及び12のコレクタをIGB
T14及び16のエミッタに接続して、2組の並列回路
を直列接続する。よって、これらIGBT10〜16
は、全体として、単一のIGBTの場合の2倍の最大電
流及び最大耐圧となる。なお、IGBTのコレクタ及び
エミッタ間が半導体素子の主電流路となる。これらIG
BTの主電流路、電源18、負荷20及び電流検出用抵
抗器22を直列接続して、電源18より、負荷20に電
圧を印加する。負荷20は、上述のように、半導体測定
装置の被測定素子であっても、モータであってもよい。
半導体測定装置の場合は、負荷20に供給される電圧を
測定する手段と、抵抗器22の電圧降下を測定する手段
とを設けて、負荷20の電圧−電流特性を測定する。
1 is a block diagram of a preferred embodiment of the present invention. In this embodiment, the IGBTs, which are semiconductor elements, are arranged in m rows and n columns (m = 2, n = 2).
The collectors and emitters of 10 and 12 are interconnected, respectively, in parallel. Also, the IGBTs 14 and 16
The collectors and emitters of are also interconnected,
Make them in parallel. The collectors of the IGBTs 10 and 12 are IGB
Two sets of parallel circuits are connected in series by connecting to the emitters of T14 and T16. Therefore, these IGBTs 10-16
Results in twice the maximum current and maximum breakdown voltage as in the case of a single IGBT. The main current path of the semiconductor element is between the collector and the emitter of the IGBT. These IG
The main current path of the BT, the power supply 18, the load 20, and the current detection resistor 22 are connected in series, and a voltage is applied from the power supply 18 to the load 20. The load 20 may be the device under test of the semiconductor measuring device or a motor as described above.
In the case of a semiconductor measuring device, a means for measuring the voltage supplied to the load 20 and a means for measuring the voltage drop of the resistor 22 are provided to measure the voltage-current characteristic of the load 20.

【0011】差動増幅器24は、抵抗器22の両端の電
圧差、即ち、負荷20に流れる電流に比例する電圧を求
める。比較器26は、差動増幅器24の出力電圧と基準
電圧Vref とを比較し、負荷20に流れる電流が所定値
に達すると、その出力状態を変化する。よって、抵抗器
22、差動増幅器24及び比較器26は、負荷の電流路
に所定電流以上が流れたことを検出すると出力信号状態
を変化させる検出手段となる。
The differential amplifier 24 determines the voltage difference across the resistor 22, that is, the voltage proportional to the current flowing through the load 20. The comparator 26 compares the output voltage of the differential amplifier 24 with the reference voltage Vref, and when the current flowing through the load 20 reaches a predetermined value, changes its output state. Therefore, the resistor 22, the differential amplifier 24, and the comparator 26 serve as detection means that changes the output signal state when detecting that a predetermined current or more has flowed in the current path of the load.

【0012】遅延回路28は、比較器26の出力信号を
遅延させ、光結合器30及び32を介して増幅器34及
び36に遅延比較出力信号を供給する。増幅器34は、
小抵抗器、例えば、100Ωの抵抗器38を介し、更
に、例えば、1KΩの抵抗器40及び42を介して、ゲ
ート制御信号をIGBT10及び12のゲートに夫々供
給する。同様に、増幅器36は、100Ωの小抵抗器4
4を介し、更に、1KΩの抵抗器46及び48を介し
て、ゲート制御信号をIGBT14及び16のゲートに
夫々供給する。これら素子28〜46が、IGBTの導
通及び非導通状態を制御する制御手段となる。光結合器
30及び32を用いており、また、増幅器34及び36
の基準電位がIGBT10(12)及び14(16)の
エミッタに結合しているため、IGBTのゲートの電位
が遅延回路28からフローティングしており、その電位
がエミッタを基準にしている点に留意されたい。
The delay circuit 28 delays the output signal of the comparator 26 and supplies the delayed comparison output signal to the amplifiers 34 and 36 via the optical couplers 30 and 32. The amplifier 34 is
A gate control signal is supplied to the gates of the IGBTs 10 and 12, respectively, through a small resistor, for example, a resistor 38 of 100Ω, and further, for example, resistors 40 and 42 of 1KΩ. Similarly, the amplifier 36 is a small resistor 4 of 100Ω.
The gate control signal is supplied to the gates of the IGBTs 14 and 16 via the resistor 4 and the resistors 46 and 48 of 1 KΩ, respectively. These elements 28 to 46 serve as control means for controlling the conduction and non-conduction states of the IGBT. Optical couplers 30 and 32 are used, and amplifiers 34 and 36 are used.
Note that since the reference potential of is coupled to the emitters of the IGBTs 10 (12) and 14 (16), the potential of the gate of the IGBT is floating from the delay circuit 28 and the potential is referenced to the emitter. I want to.

【0013】次に、図2及び図3を参照して、図1の動
作を説明する。なお、図2は、経過時間に対する負荷に
流れる電流(IGBTの総合電流)を示し、図3は、I
GBT10〜16の総合特性曲線(コレクタ・エミッタ
間電圧−コレクタ電流特性曲線)を示す。定常状態にお
いて、電源18から負荷20を介して流れる電流は、過
大基準値未満、例えば、Is であるので、抵抗器22の
電圧降下も基準電圧Vref 以下であるため、比較器26
は高レベル信号を持続する。この高レベル信号は、光結
合器30及び32を介して増幅器34及び36に夫々供
給される。増幅器34は、IGBT10及び12のエミ
ッタに対して順バイアスをゲートに供給するので、これ
らIGBT10及び12は導通状態になる。また、増幅
器36は、IGBT14及び16のエミッタに対して順
バイアスをゲートに供給するので、これらIGBTは導
通状態になる。
Next, the operation of FIG. 1 will be described with reference to FIGS. 2 shows the current (total IGBT current) flowing through the load with respect to the elapsed time, and FIG.
The general characteristic curve (collector-emitter voltage-collector current characteristic curve) of GBT10-16 is shown. In the steady state, the current flowing from the power source 18 through the load 20 is less than the excessive reference value, for example, Is, and therefore the voltage drop of the resistor 22 is also equal to or less than the reference voltage Vref.
Maintains a high level signal. This high level signal is supplied to amplifiers 34 and 36 via optical couplers 30 and 32, respectively. The amplifier 34 supplies a forward bias to the gates of the IGBTs 10 and 12 at their gates, so that the IGBTs 10 and 12 become conductive. Further, the amplifier 36 supplies a forward bias to the emitters of the IGBTs 14 and 16 at their gates, so that these IGBTs become conductive.

【0014】時点t0において、負荷20に短絡又は地
絡が生じると、負荷20を流れる電流が上昇し始める。
このとき、IGBTにおける動作点は、図3に示す点P
0である。負荷20の電流路のインダクタンス及び抵抗
により決まる傾き(上昇比率)で電流が次第に増えて、
時点t1にて、抵抗器22の電圧降下が基準電圧Vref
に達すると、比較器26の出力信号が低レベルに変化す
る。しかし、遅延回路28の作用により、この低レベル
は、直ちにはIGBT10〜16のゲートに供給されな
い。よって、これらIGBTは、依然として導通状態で
ある。
At time t0, if a short circuit or a ground fault occurs in the load 20, the current flowing through the load 20 will start to rise.
At this time, the operating point of the IGBT is the point P shown in FIG.
0. The current gradually increases at a slope (rate of increase) determined by the inductance and resistance of the current path of the load 20,
At time t1, the voltage drop across the resistor 22 changes to the reference voltage Vref.
The output signal of the comparator 26 changes to a low level. However, due to the action of the delay circuit 28, this low level is not immediately supplied to the gates of the IGBTs 10-16. Therefore, these IGBTs are still conductive.

【0015】この時、負荷20の短絡のため、IGBT
に高電圧が印加されて、コレクタ電流が増えて、IGB
Tは動作点が変わり、この動作点がP1に達する。よっ
て、負荷20を流れる電流は、一定の電流Isat とな
る。なお、IGBTの動作点は、供給電圧が高くなるの
で、P1から動作曲線に沿って、右側に(電圧の高い
方)に移動し、電流が飽和状態になる。
At this time, due to the short circuit of the load 20, the IGBT
High voltage is applied to the collector, the collector current increases and
The operating point of T changes, and this operating point reaches P1. Therefore, the current flowing through the load 20 becomes a constant current Isat. Since the supply voltage is high, the operating point of the IGBT moves from P1 to the right side (higher voltage) along the operating curve, and the current is saturated.

【0016】遅延回路28の遅延作用により、時点t2
で、低レベルが増幅器34及び36に伝搬し、IGBT
10〜16のゲートに低レベルが供給されると、これら
IGBTは非導通状態に順次移行する。なお、時点t2
でIGBTの動作点はP2となる。よって、負荷20に
流れる電流は、図4に示すように、上昇状態から下降状
態に急激に変化することなく、図2に示す如く、上昇状
態から、一定状態を介して下降状態に緩やかに変化す
る。したがって、スパイク・ノイズなどを防止できる。
ところで、上述の実施例では、遅延回路として、専用の
ブロック28を設けているが、IGBTの入力容量と、
ゲート抵抗器38〜46とによる時定数回路を遅延回路
としてもよい。この場合、ゲート抵抗器の値を選択する
ことにより、遅延時間を調整できる。よって、実施例の
場合、専用の遅延回路と、ゲート抵抗器及びIGBTの
入力容量の時定数回路の遅延回路の2個を用いているこ
とになる。
Due to the delay action of the delay circuit 28, the time t2
At the low level propagates to the amplifiers 34 and 36,
When a low level is supplied to the gates of 10 to 16, these IGBTs sequentially shift to the non-conducting state. Note that time t2
Therefore, the operating point of the IGBT becomes P2. Therefore, the current flowing through the load 20 does not suddenly change from the rising state to the falling state as shown in FIG. 4, but gradually changes from the rising state to the descending state via a constant state as shown in FIG. To do. Therefore, spike noise and the like can be prevented.
By the way, in the above-described embodiment, the dedicated block 28 is provided as the delay circuit, but with the input capacitance of the IGBT,
A time constant circuit including the gate resistors 38 to 46 may be a delay circuit. In this case, the delay time can be adjusted by selecting the value of the gate resistor. Therefore, in the case of the embodiment, two of the dedicated delay circuit and the delay circuit of the gate resistor and the time constant circuit of the input capacitance of the IGBT are used.

【0017】上述は、本発明の好適な実施例について説
明したが、本発明の要旨を逸脱することなく種々の変形
及び変更が可能である。例えば、ブレーカ装置に用いる
半導体素子は、IGBT以外の高耐圧半導体でもよい。
さらに、実施例では、半導体素子を2行2列に配置した
が、所望の最大電流及び最大電圧に応じて、任意のm行
n列(m及びnは、1以上の整数)の配置にしてもよ
い。また、過大電流を検出する検出手段は、負荷の電流
路に流れる電流による磁界を検出する方式でもよい。
Although the preferred embodiment of the present invention has been described above, various modifications and changes can be made without departing from the gist of the present invention. For example, the semiconductor element used in the breaker device may be a high breakdown voltage semiconductor other than the IGBT.
Further, in the embodiment, the semiconductor elements are arranged in 2 rows and 2 columns, however, according to the desired maximum current and maximum voltage, any m rows and n columns (m and n are integers of 1 or more) may be arranged. Good. Further, the detecting means for detecting the excessive current may be a method for detecting a magnetic field due to the current flowing in the current path of the load.

【0018】[0018]

【発明の効果】上述の如く、本発明によれば、負荷の電
流路に流れる電流を遮断する際に、電流の急激な変化を
防止するので、スパイク・ノイズの発生を防げる。
As described above, according to the present invention, when the current flowing through the current path of the load is cut off, a sudden change in the current is prevented, so that spike noise can be prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の好適な実施例のブロック図である。FIG. 1 is a block diagram of a preferred embodiment of the present invention.

【図2】本発明の動作を説明する時間対電流の図であ
る。
FIG. 2 is a time-current diagram illustrating the operation of the present invention.

【図3】本発明の動作を説明するための半導体素子の特
性図である。
FIG. 3 is a characteristic diagram of a semiconductor device for explaining the operation of the present invention.

【図4】従来のブレーカ装置の動作を説明する時間対電
流の図である。
FIG. 4 is a time-current diagram illustrating the operation of a conventional breaker device.

【符号の説明】[Explanation of symbols]

10、12、14、16 半導体素子(IGBT) 18 電源 20 負荷 22 電流検出用抵抗器 24 差動増幅器 26 比較器 30、32 光結合器 10, 12, 14, 16 Semiconductor element (IGBT) 18 Power supply 20 Load 22 Current detection resistor 24 Differential amplifier 26 Comparator 30, 32 Optical coupler

フロントページの続き (72)発明者 松田 俊一 東京都品川区北品川5丁目9番31号 ソニ ー・テクトロニクス株式会社内Front Page Continuation (72) Inventor Shunichi Matsuda 5-9-31 Kitashinagawa, Shinagawa-ku, Tokyo Inside Sony Tektronix Co., Ltd.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 負荷に過大電流が流れた際に、負荷の電
流路を遮断するブレーカ装置において、 出力電流路が上記負荷の電流路に挿入された半導体素子
と、 上記負荷の電流路に所定電流以上が流れたことを検出す
ると出力信号状態を変化する検出手段と、 通常状態で上記半導体素子を導通状態に制御し、上記検
出手段の出力信号状態が変化すると、上記半導体素子を
飽和状態にした後に上記半導体素子を非導通状態に制御
する制御手段とを具えたブレーカ装置。
1. A breaker device for shutting off a current path of a load when an excessive current flows through the load, wherein a semiconductor element having an output current path inserted in the current path of the load and a predetermined current path of the load. When detecting that a current or more has flowed, the output signal state is changed, and the semiconductor element is controlled to be conductive in the normal state, and when the output signal state of the detection means is changed, the semiconductor element is saturated. And a control means for controlling the semiconductor element to be in a non-conducting state.
【請求項2】 上記半導体素子は、絶縁ゲート・バイポ
ーラ・トランジスタであり、 上記制御手段は、上記検出手段の出力信号を遅延する遅
延回路を含み、該遅延回路の出力信号を上記絶縁ゲート
・バイポーラ・トランジスタのゲートに供給して、非導
通状態に制御することを特徴とする請求項1のブレーカ
装置。
2. The semiconductor device is an insulated gate bipolar transistor, and the control means includes a delay circuit that delays an output signal of the detection means, and the output signal of the delay circuit is the insulated gate bipolar transistor. The breaker device according to claim 1, wherein the breaker device is supplied to the gate of the transistor and is controlled to be in a non-conductive state.
【請求項3】 上記半導体素子は、nの絶縁ゲート・バ
イポーラ・トランジスタが並列接続され、該並列接続の
n組が直列接続されたこと(n及びmは1以上の整数)
を特徴とする請求項1のブレーカ装置。
3. In the semiconductor device, n insulated gate bipolar transistors are connected in parallel, and n sets of the parallel connection are connected in series (n and m are integers of 1 or more).
The breaker device according to claim 1, wherein:
JP12702595A 1995-04-27 1995-04-27 Circuit breaker apparatus Pending JPH08308094A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP12702595A JPH08308094A (en) 1995-04-27 1995-04-27 Circuit breaker apparatus
US08/639,180 US5637990A (en) 1995-04-27 1996-04-26 High speed, large-current power control apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12702595A JPH08308094A (en) 1995-04-27 1995-04-27 Circuit breaker apparatus

Publications (1)

Publication Number Publication Date
JPH08308094A true JPH08308094A (en) 1996-11-22

Family

ID=14949825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12702595A Pending JPH08308094A (en) 1995-04-27 1995-04-27 Circuit breaker apparatus

Country Status (1)

Country Link
JP (1) JPH08308094A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012127808A (en) * 2010-12-15 2012-07-05 Advantest Corp Test equipment
CN108702080A (en) * 2016-02-08 2018-10-23 Abb瑞士股份有限公司 For high-voltage electric power system switchgear and include the device of this switchgear
JP2019047474A (en) * 2017-08-30 2019-03-22 矢崎総業株式会社 Semiconductor relay and current detector for vehicle

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012127808A (en) * 2010-12-15 2012-07-05 Advantest Corp Test equipment
US8704540B2 (en) 2010-12-15 2014-04-22 Advantest Corporation Test apparatus
TWI467192B (en) * 2010-12-15 2015-01-01 Advantest Corp Test apparatus for testing avalanche breakdown voltage of device under test
CN108702080A (en) * 2016-02-08 2018-10-23 Abb瑞士股份有限公司 For high-voltage electric power system switchgear and include the device of this switchgear
CN108702080B (en) * 2016-02-08 2021-01-12 Abb瑞士股份有限公司 Switching device for a high voltage power system and arrangement comprising such a switching device
JP2019047474A (en) * 2017-08-30 2019-03-22 矢崎総業株式会社 Semiconductor relay and current detector for vehicle

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