JPH0830997B2 - Controller for three-phase reactive power compensator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention detects a reactive power of each phase in order to increase a response speed in a three-phase reactive power compensator in which a capacitor group of a bus bar is controlled to open and close by a thyristor. By maintaining the capacitor group as open or closed for one cycle of three phases by the operation signal of the earliest detected phase, the thyristor can be opened and closed at high speed without stable imbalance of three phases. The present invention relates to a capacitor control device.

[Prior Art] There is known a device (hereinafter referred to as a TSC device) that detects reactive power and controls the opening and closing of a capacitor group with respect to a bus by a thyristor.

The TSC device is a combination of an anti-parallel connection thyristor (TH), a series reactor (SR) and a capacitor group in which a capacitor (SC) is connected in series, as shown in Fig. 4, and the reactive power is gradually increased by controlling the opening and closing of the thyristor. Is adjusted to suppress the fluctuation of the bus voltage and at the same time improve the power factor.

When controlling a capacitor with a thyristor, the difference from the control of other reactor-controlled thyristors is that
Since the rush current is generated when the power is turned on, the thyristor cannot be turned on in an arbitrary phase, and the timing of turning on the thyristor is limited to a phase in which the power supply voltage and the capacitor voltage that do not generate the rush current are equal. FIG. 3 shows a block diagram of the TSC control device. In parallel with the variable load 3 connected to the system 3-phase bus 2, as shown by 4, the unit capacitors SC ₁ ... SC _n for each phase are weighted with, for example, 1, 2, 4, (1), A thyristor-controlled reactive power compensating circuit is formed by dividing the capacitor groups into three groups of (2) and (3), and connecting each of these capacitor groups in series with an antiparallel thyristor and a diode and a series reactor. The thyristor and the thyristor may be connected in antiparallel.

In the figure, the capacitor groups (1), (2), (3)
By switching, the capacity can be changed to 7 stages and input.

 Reference numeral 5 indicates a reactive power (Q) detection circuit.

Bus voltage If you put it u = s · _L = V _L · I _L {Sinφ ₁ + Sin (2ωt−φ
_{1)} v = V L ·} I L {Sinφ 1 + Sin (2ωt-φ 1 -2/3
π)} w = V _L · I _L {Sinφ ₁ + Sin (2ωt−φ ₁ −4/3
π)} Reactive power Q ₀ at the time of three-phase balance is Q ₀ = u + v + w = 3 · V _L · I _L · Sinφ ₁ Now, φ ₁ = π / 2 delay, and the gain of the adder is 1/3 _{, Q 0 = 3 · V L} · I L · Sinπ / 2 · 1/3 = V L · I L next,
A Q control signal (DC) corresponding to one phase is obtained. Thus, the Q control signal can be obtained with a rapid response. Since a double frequency ripple occurs for each phase imbalance, a method such as removing the ripple with a low-pass filter is used.

The reactive power detection circuit 5 takes a voltage signal from the bus voltage Vs by PT, obtains a 90 ° lag voltage V's by the voltage phase shifter 51, detects the current signal I _L from CT connected to this, and detects the current signal IL. Based on the calculation, each phase Q detector 52 calculates each phase Q _u , Q _v , and Q _w , and a three-phase Q adder 53 obtains a Qc control signal corresponding to one phase.

Reference numeral 9 denotes a capacitor control group determination circuit and the like. Here, as shown in FIG. 5, the detected Qc control signal is compared with a preset reactive power reference signal Qs to determine the necessary compensation level by the capacitor. decide. In this case, the compensation level is 1 to 7, and at any level of the compensation levels 1 to 7, the decoder circuit 56 performs logical processing,
Among the capacitors of the capacitors (1) group, the same (2) group, and the same (3) group, which are collected by weighting 1, 2, and 4, the capacitor group to be turned on is determined.

In the block zone determination circuit 10, a signal is sent to the thyristor gate pulse generation circuit 11 of the capacitor group to be turned on, and the firing of the thyristor to turn on the capacitor group is π.
It is implemented with a gate pulse of / 4 section.

[Problems to be Solved by the Invention] By the way, when Qc is made to have a high-speed response as described above, three phases become unbalanced at the moment when the capacitors for one phase of three phases are coupled to the system, and the reactive power calculation signal becomes faster. Therefore, the imbalance was detected, and the capacitors of each phase were turned on and off, resulting in an increasingly more unbalanced three-phase system.

For this reason, normally, as shown by 54 in FIG. 5, an incomplete integration circuit is provided in the preceding stage of the capacitor control group determination circuit, or a comparison circuit shown by 55 is given a hysteresis characteristic. Response time is about several cycles (≒
It was a delay of 100 ms), and as a result, we could not expect an accurate TSC device.

[Configuration of the Invention] The present invention has been made in order to solve the above problems, and in order to compensate reactive power generated in a system load,
In a three-phase reactive power compensator equipped with a compensating circuit that controls the opening and closing of a compensating capacitor with respect to a bus with a thyristor, the reactive reactive power of each phase is detected, and the group of compensating capacitors is determined from this detected reactive power. The signal is held as the capacitor group opening / closing command signal for the phase detected earliest by the three-phase timing pulse, and only the capacitor group corresponding to each phase is closed or moved to open, and each phase is open or closed for one cycle. The other capacitor group is continuously maintained in the open or closed state as it is.

Therefore, the present invention is realized mainly by making an improvement mainly on the capacitor control group determination circuit 9 of the TSC device shown in the block diagram of FIG.

FIG. 1 is a block diagram showing a capacitor control group determination circuit 9 used in the present invention.

A comparator 13 that receives the reactive power signal Qc from the Q adder 53 of the reactive power detection circuit 5 in FIG. 3 is installed. This comparator 13 is provided with a reactive power reference signal Qs which serves as a reference for switching capacitors, and in the case of this example, it is provided with a compensation level by a capacitor group of 1 to 7 stages. The output from the comparator 13 is input to the decoder circuit 14. Decoder circuit 14
Is according to the levels of 1 to 7 indicated by Qc-Qs,
For example, the capacitors (1), the capacitors (2), and the capacitors (2), (2), and (3) can be energized as a combination so that the capacitors can be energized in combination. 3) Generate capacitor group decision signal 20 in any or all of the groups. This signal 20 is a fluctuating reactive power signal
It always changes depending on Qc.

The sample hold circuit 15 is a circuit which holds the signal 20 by a three-phase timing pulse.

Reference numeral 19 shows an OR circuit with differentiator, which is a sample hold circuit
In FIG. 15, for example, when the capacitor (1) group command signal is held, a trigger pulse is generated, and when the signal is released, a trigger pulse is similarly generated.

18 is a monostable circuit, and when a trigger pulse is input from the OR circuit 19, 2/3 × 1 / 50Hz <t ₁ 1 / 50Hz,
Or it produces a high level signal for a period of 2/3 x 1/60 Hz <t ₁ 1/60 Hz. Then, one input of the AND circuit 17 is performed via the inverting circuit.

On the other hand, the three-phase U, V, W is input to the logic circuit 16 and the phase difference is 120 °.
3 phase timing pulse with a lead angle of 30 ° at the voltage peak point
u, v, w are generated and input to the AND circuit 17. Therefore,
When there is no higher level signal than the monostable circuit 18, u, v, w are input to the sample and hold circuit 15, but when there is a high level signal, the input of u, v, w is blocked in the masked state. To be done.

[Operation] FIG. 2 shows an operation time chart of each part of the apparatus shown in FIG. 1 in relation to FIG.

With respect to the three-phase AC bus voltage power supplies U, V, W, the logic circuit 16 outputs timing pulses u, v, w of a three-phase 120 ° phase with a lead angle of 30 ° at the voltage peak point.

It is assumed that the reactive power Qc of the quick response to the comparator 13 starts from 0 and changes to a, b, c, d. Comparator 13
, The varying a, b, c, d are compared with the reactive power signal Qs to vary the compensation levels 1 to 7, which may be capacitor (1) group determination, capacitor (2) group determination, or capacitor ( 3) The signal reaches the sample-hold circuit 15 while generating or extinguishing the group determination signal.

For example, when the timing pulse u is input to the sample hold circuit 15 from the logic circuit 16 via the AND circuit 17 immediately after the compensation level becomes 1, the capacitor (1) group command signal corresponding to this compensation level 1 is directly sampled. It is held by the hold circuit 15.

When the capacitor (1) group command signal is held by this timing pulse u, the OR circuit 19 with differentiator generates a trigger pulse, and as a result, the monostable circuit 18 is at a high level for a time t ₁ of 1 cycle or less. Therefore, u and w following the timing pulse u are masked by the AND circuit 17, so that the sample hold circuit 15 does not have v and w inputs. Even if the timing pulse u is input to the sample-hold circuit 15 after the high level period of t ₁ hours of one cycle or less by the monostable circuit 18 has passed, if the capacitor (1) group command signal remains unchanged, the timing pulse u Does not work.

In the above case, the capacitor (1) group command signal is input to the block zone determination circuit 10 in FIG.
Not only the U-phase corresponding part of the group, but also the V-phase and W-phase corresponding parts are sequentially closed by the firing of the thyristor. During this time, even if there is a level fluctuation signal in the sample and hold circuit 15, the AND circuit
The timing pulses V and W from 17 are not output, and even if the level fluctuates between the timing pulses V and W, it does not respond to this level fluctuation during one sille.

Next, between the timing pulse u and the next v, Qc
Rises to the state of b, and only the capacitor (2) group determination signal appears. Immediately after this, the timing pulse v
Arriving at the sample hold circuit 15 via the AND circuit 17, the sample hold circuit 15 holds the capacitor (2) group command signal as it is, and the capacitor (1) group command signal is released. At the same time, a trigger pulse is generated by the OR circuit 19 with differentiator, and the AND circuit 17 outputs w and u following the timing pulse v.
, And w and u are not input to the sample hold circuit 15.

In the above case, not only the V phase component of the capacitor (2) group but also the W phase component and U phase component of the capacitor (2) group are input.
The U-phase component, the V-phase component, and the W-phase component of the capacitor (1) group are released by the disappearance of the ON signal corresponding to the block zone determination circuit 10.

Further, when wc and w following the timing pulse v are decreased to Q state C (0: no compensation required), a sample hold is performed at the next v that appears after t _{1 has} elapsed from the v. In the circuit 15, since the capacitor (2) group determination signal disappears and becomes 0, the holding value of the sample hold circuit 15 is set to 0 by the input of v. Depending on the hold value 0 in this sample hold circuit 15, one cycle or less
The AND circuit 17 is masked for t ₁ hour, and at the same time, not only the V phase component of the capacitor (2) group but also the W phase and U phase components are opened.

Further, when Qc rises and the capacitor (2) group determination signal appears after all of the capacitor groups have been opened, the time t ₁ less than one cycle from v has passed. After that, the timing pulse v input to the sample and hold circuit 15 for the first time generates a command signal for the capacitor (2) group, and not only the V phase component of the capacitor (2) group but also the W phase and U phase components are input. become. Such an operation is repeated in response to fluctuations in Qc, the capacitor group is opened and closed, and control is continued.

As shown in the figure, when the V level of the reactive power Qc detected by the detected rapid response rises and falls, the timing pulse is t _{1 of} 1 cycle or less before issuing the command to turn on / off each capacitor group. Since it is maintained within the time, there is a delay tL ₁ in the start of sampling, but as is clear from the figure, the response time is within half a cycle.

[Effects of the Invention] In the present invention, the capacitor group is determined by the sampling control for each phase, and therefore, the cycle becomes about half a cycle or less even if the delay of the reactive power calculation is taken into consideration.

After holding the command signal of the capacitor group in one phase,
Since the sampling is blocked for one cycle, the voltage fluctuation can be controlled stably without inducing the three-phase imbalance of the system.

In the present invention, by improving the control circuit of the conventional TSC device, a highly accurate TSC that does not adversely affect the system
Equipment can be expected.

[Brief description of drawings]

FIG. 1 shows a block diagram of the control device of the present invention. FIG. 2 shows an operation time chart of each part of the apparatus shown in FIG.
Shown in relation to the figure. FIG. 3 shows a block diagram of a conventional TSC controller. FIG. 4 is a schematic explanatory diagram of the TSC device. FIG. 5 is a block diagram showing a conventional capacitor control group determination circuit. 13 ... Comparator, 14 ... Decoder circuit, 15 ... Sample-hold circuit, 16 ... Logic circuit, 17 ... AND circuit, 18 ... Monostable circuit, 19 ... OR circuit with differentiator.

Claims (1)

[Claims] 1. A three-phase reactive power in which reactive power is detected and a compensating capacitor group to be injected into the system based on the reactive power signal is determined by a capacitor control group determination circuit and opening / closing control of this capacitor group is performed by a thyristor. In a control device of a compensating device, the capacitor control group determination circuit, a comparator which receives the reactive power signal, compares the reactive power signal and a reactive power reference signal, and outputs a compensation level by a capacitor group, and the comparator. And a decoder circuit which receives the compensation level output of (1) and outputs a capacitor group determination signal, and which receives the capacitor group determination signal of the decoder circuit and holds this signal by a three-phase timing pulse and outputs the output to the block zone determination circuit. A sample and hold circuit, and the capacitor group to which the output of the sample and hold circuit is input An OR circuit with a differentiator that outputs a trigger pulse by holding a decision signal or releasing the decision signal, and a trigger pulse output of the OR circuit with a differentiator are input, and a high level signal is output for a period of one cycle or less of the trigger pulse. A monostable circuit, a logic circuit which inputs a three-phase bus voltage and outputs the three-phase timing pulse, and a timing period during which the three-phase timing pulse and the high-level signal of the monostable circuit are input and the cycle is one cycle or less. A control device for a three-phase reactive power compensator, comprising an AND circuit for masking a pulse and outputting it to the sample-hold circuit.