JPH0831003B2 - Bus occupation circuit - Google Patents

Description

The present invention relates to control of a CPU (microprocessor) peripheral circuit, and more particularly to a bus arbitration circuit of a multiprocessor system in which a plurality of CPUs share a single bus. .

[Conventional technology]

In a multi-CPU system, multiple CPUs use the same bus (common bus), but of the CPU boards used in the multi-CPU system, only one can occupy the common bus at the same time. Therefore, some form of coordination circuit is needed to avoid data collisions on the common bus.

There are two methods of bus arbitration: one that uses an arbitration board that is independent from all CPU boards, and one that adds an arbitration circuit to each CPU board. In either case, the basic idea is as follows. Take action. Note that the terms "assert" and "negate" in the following text refer to "positive logic (active High)" and "negative logic (active Low)" of signals.
Regardless of, "assert" means to make the signal "true" or active and "negate" to make the signal "false" or inactive.

That is, the bus arbitration circuit constantly monitors whether or not the bus is in use, and when one of the CPUs tries to use (occupy) the bus and issues a bus occupation request, another CPU has already been in operation.
When the bus is in use, it causes the previous CPU to wait for the bus to occupy the bus, and when the bus becomes available, the CPU that has been waiting waits to use the bus. When the enabled CPU receives the bus use enable signal from the arbitration circuit, it receives the address confirmation signal (Address Stro
be: AS) to occupy the bus and send and receive data. The bus in the CPU board, that is, the internal bus, is connected to the common bus via the tri-state buffer,
The common bus side of the CPU board that does not normally use the bus has high impedance, and only the CPU board that is permitted to use the bus by the arbitration circuit connects the internal bus to the common bus.

FIG. 4 is a diagram showing a conventional example in which each CPU board has an arbitration circuit. In FIG. 4, the left side of the dotted line is the CPU board, and the right side is the common bus side. AS is an address confirmation signal indicating that the address output by the CPU has been confirmed, and DS is also a data confirmation signal. EXTREQ is a request signal for using the common bus.
4 and 5 are tri-state buffers, input G is "L"
In this case, the internal bus and the common bus are connected, and when G is "H", the common bus side becomes high impedance. 4-input NA
ND6 is for multi-CPU arbitration, and its output BGS is BG of other CPU board.
It is connected to the x input (see Figure 3). That is, 4 inputs N
BGS is asserted only when all inputs of AND6 are “H”, and the CPU board can use the common bus. Such C
Since there can be only one PU board, it is possible to avoid data collision on the common bus.

FIG. 3 shows an example of connection when three CPU boards operate as multiple CPUs.

[Problems to be Solved by the Invention]

In the circuit shown in FIG. 4, when the AS signal becomes negated, the bus is immediately opened and the output of the buffer becomes high impedance. It seems that there is no problem at first glance, but a high-speed CPU
When using, it must be taken into consideration that the AS or DS signal is negated after assertion and one cycle is completed, and immediately after that, the next cycle is started and AS or DS is asserted. As an example, 32bit CPU MC68020
When (Motorola) is used with a clock of 20MHz, AS (D
The minimum period during which S) is negated is 38nS. That is, if the AS (DS) on the common bus is not completely negated within 38nS after the AD (DS) negate, it cannot be distinguished from the AS (DS) signal in the next cycle, and it may malfunction. Become. However, the AS (DS) signal (GAS or GDS) on the G bus is usually connected in parallel with another CPU board and pulled up by a resistor, but if AS (DS) is completely negated. If the gate of the tri-state buffer 4 is closed before and GAS (GDS) becomes high impedance, GAS (GDS) will negate ("H") only by the pull-up function of the resistor. Now, the capacitance of the bus line is C (F), pull-up resistance R (Ω), E (V)
If the voltage at the moment when the impedance becomes high is 0V at worst, then t
The voltage after (S) is Et = E (1-EXP (-t / CR)), so E = 5
If V, C = 100 pF and R = 2 kΩ, it takes about 130 nS until Et reaches the threshold voltage of 2.4 V, which means that it completely overlaps with the next cycle.

An object of the present invention is to provide a bus occupation circuit that solves the above problems.

[Means for solving the problem]

To achieve the above object, a bus occupation circuit according to the present invention has a bus arbitration circuit, a tri-state buffer, and a delay circuit, and a plurality of CPUs connected to the same common bus.
Multi-C in which only one of the boards can occupy the common bus
The bus arbitration circuit used for PU, the bus arbitration circuit prevents a common bus occupancy request of one CPU board from colliding with another CPU board on the common bus. It is opened and closed by the control signal of the bus arbitration circuit to connect the low-lying CPU board to the common bus.The delay circuit is
The gate of the tri-state buffer is closed with a certain delay after the control signal of the bus arbitration circuit is completely negated to secure the data on the bus for a certain time.

[Action]

The bus occupation circuit of the present invention inserts a delay circuit into an open / close signal of a 3-state bus buffer that connects an internal bus of each CPU board to an external common bus in a CPU system that performs multiple CPU operation, and the CPU is the common bus. After occupying the CPU
By closing the bus buffer after a short time after the address confirmation signal output by the NEGATE is negated, the GAS negate negates the high speed rising speed of the CPU itself, regardless of the pull-up function of the resistor. Then, the buffer is closed after that, and the above-mentioned problem is solved.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The right side of the dotted line is a portion connected to a common bus, and the left side is a CPU board.

In the figure, 1 is a signal indicating that the address output from the CPU is fixed, 2 is a data fixing signal, 3 is a request signal for the external common bus, 4 and 5 are tristate buffers, and 6 is a 4-input NAND. . 7 is a shift register,
The D input is shifted at the rising edge of CK, and the two-stage shift is input to QB, which constitutes a delay circuit 8 which delays only the end of the common bus occupation request. Common bus side BG
S and BG0 to BG2 are signals for controlling multiple CPUs and are connected to other CPU boards as shown in FIG.

FIG. 2 is a time chart showing the operation of the present invention.
A and B are address (data) confirmation signals (GAS, GDS) on the common bus side, where A is according to the present invention and B is according to the conventional method.

In FIG. 1, due to the function of the shift register 7 of the delay circuit 8, there is no delay when the AS signal is asserted, and only the negate is delayed.

The time chart of FIG. 2 shows the timing when AS is continuously asserted. A is GAS, B of the present invention
Is the GAS signal from the conventional circuit. The waveform of B is blunted at the negate and is delayed in the next cycle, but is negated almost simultaneously with the AS negate by the function of the delay circuit 8.

[Effect of the Invention] As described above, the bus occupying circuit of the present invention operates by opening the bus after the address (data) confirmation signal is completely negated by the function of the delay circuit inserted in the bus arbitration circuit. , GAS (GDS) signal is completely negated at the same time when the bus is released, and high-speed C is achieved in a multi-CPU system.
Even when the PU is used, the control signal is completely separated for each bus cycle, and it is possible to realize a system without malfunction.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the present invention, FIG. 3 is a diagram showing the configuration of a multi-CPU system, and FIG. 4 is a configuration showing a conventional example. It is a figure. 1 ... Signal indicating that the address output by the CPU has been decided 2 ... Data decision signal 3 ... External common bus request signal 4,5 ... Tri-state buffer 6 ... 4 input NAND, 7 ... Shift register 8 ... Delay circuit

Claims (1)

[Claims] 1. A multi-CPU having a bus arbitration circuit, a tri-state buffer and a delay circuit, wherein only one CPU board among a plurality of CPU boards connected to the same common bus can occupy the common bus. The bus arbitration circuit is a bus arbitration circuit that prevents a common bus occupancy request of one CPU board from colliding with another CPU board on the common bus. It is opened / closed by the control signal of the arbitration circuit and connects the low-level CPU board to the common bus. A bus occupation circuit, characterized in that the gate of the tri-state buffer is closed after a certain delay to secure data on the bus for a certain time.