JPH0831175A - Semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] To prevent contention of read data and prevent level inversion when an IO mask is used in a block write mode of a synchronous DRAM or the like. As a result, the reliability of the synchronous DRAM or the like is improved without impeding the cost reduction. In a synchronous DRAM or the like having a block write mode capable of IO masking, for example, between a power supply voltage of a circuit and a non-inversion of an inter-mat complementary common data line IC00 * and an inversion signal line, an ON state is set when not selected. As a result, P channel type precharge MOSFETs P2 to P4 for precharging the non-inverted and inverted signal lines of the inter-mat complementary common data line IC00 * to a high level are provided,
These MOSFETs are turned on even when the IO mask control signal MIO0 is set to the high level during the IO mask in the block write mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a synchronous DRAM (dynamic random access memory) having a block write mode.
In addition, the present invention relates to a technique that is particularly effective in controlling the IO mask.

[0002]

2. Description of the Related Art There is a so-called synchronous DRAM whose operation is synchronized according to a predetermined clock signal. Further, there is a so-called block write mode in which a common data line and a plurality of bit lines are simultaneously connected to write the same content to a plurality of addresses, and there is a multi-port video RAM having such a block write mode.

Regarding a multi-port video RAM having a block write mode, for example, February 26, 1991.
Published by Hitachi, Ltd., "HM534253A Series 262144-Word x 4-Bit Mult"
iport CMOS Video RAM Data Sheet ”.

[0004]

In recent years, Synchronous D
RAMs are often used in the same fields as video RAMs, and customer demands for a block write mode effective during screen initialization and background coloring are increasing. In order to deal with such a demand, the inventors of the present application have
Prior to the present invention, a synchronous DRAM having a block write mode was developed, and the following problems were encountered. That is, the synchronous D used for the screen display
In the block write mode of RAM, for example, a so-called IO mask function of selectively masking writing in the bit direction of color data and a so-called address mask function of selectively masking in the scanning line direction of the screen, that is, the column address direction are required. It Among them, the address mask function has an in-mat complementary common data line AC0 provided corresponding to each bit of color data, as illustrated in FIG.
* (Here, for example, the common data line AC0 in the non-inversion mat
T and the common data line AC0B in the inverted mat are collectively indicated by an asterisk such as a complementary common data line AC0 * in the mat. Further, a so-called non-inverted signal or the like which is selectively set to high level when it is validated is represented by adding T to the end of the name, and is selectively set to low level when it is validated. A so-called inverted signal or the like is represented by adding B to the end of its name. The same applies hereinafter) can be realized by selectively forming the bit line selection signals YS0 to YS7 for connecting the complementary bit lines B0 * to B7 * of the unit memory array UMA0.
Complementary common data line I between the data input / output circuit IO and the mat
It is necessary to selectively stop the supply of the write signal via C00 * and the complementary common data line AC0 * in the mat.

However, in the synchronous DRAM, in order to achieve high integration of the memory array, the bit line selection signals YS0 to YS7 formed by the column address decoder are used.
Are shared by a plurality of memory mats arranged adjacent to each other in the horizontal direction in the figure, that is, a unit memory array UMA0 and the like and a unit sense amplifier US0 and the like, and the bit line selection signals YS0 to YS7 are It is formed without stopping even during masking. Therefore, particularly in the block write mode in which, for example, eight complementary bit lines are simultaneously connected to the in-mat complementary common data line AC0 *,
The read data of the eight complementary bit lines selected on the complementary common data line AC0 * in the mat compete with each other,
In the worst case where the logic level is biased, there is a possibility that the logic level may be inverted after rewriting the minority data. To deal with this, the inventors of the present application, as shown in FIG. 8, switch MOSFETs that are selectively turned on in accordance with bit line selection signals YS0 to YS7 and the like.
(Metal oxide semiconductor type field effect transistor. In this specification, MOSFETs are collectively referred to as insulated gate field effect transistors.) Between N2 and N3 and the complementary common data line AC0 * in the mat, at the time of IO masking. , Inversion IO
It was considered to provide N-channel MOSFETs N9 and N10 which are selectively turned off in response to the low level of the mask control signal MIO0B. But with this method,
As a result, the required layout area of the unit sense amplifier US0 or the like, which is required to be highly integrated, is increased, the chip size of the synchronous DRAM is increased, and the cost reduction is hindered.

An object of the present invention is to provide a synchronous DRAM.
It is to prevent contention of read data at the time of IO mask in the block write mode, and to prevent level inversion after rewriting. Another object of the present invention is to improve the reliability of a synchronous DRAM or the like without impeding cost reduction.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a synchronous DRAM or the like having a block write mode capable of IO masking,
For example, the non-inverted and inverted signals of the complementary common data line are selectively turned on during non-selection between the power supply voltage of the circuit and the non-inverted and inverted signal lines of the complementary common data line transmitting the write signal. P to precharge the line to high level
Providing channel MOSFETs, these MOSFETs
Is also turned on during the IO mask in the block write mode.

[0009]

According to the above-mentioned means, the switch MOSFET for mask control is not provided for each bit line,
Since the levels of the non-inverted and inverted signal lines of the complementary common data line that is the target of the IO mask can be made sufficiently high to prevent the read data of the plurality of simultaneously selected complementary bit lines from conflicting with each other, the read data of these read data can be prevented. Even if the logic levels are biased, it is possible to prevent the level inversion after rewriting the minority data. As a result, it is possible to enhance the reliability of the synchronous DRAM having the block write mode and the like without impeding the cost reduction.

[0010]

1 shows a block diagram of an embodiment of a synchronous DRAM to which the invention is applied, and FIG. 2 shows a bank BA included in the synchronous DRAM of FIG.
A block diagram of one embodiment of NK0 is shown. Also,
FIG. 3 shows a block diagram of an embodiment of the memory block MB0 included in the bank BANK0 of FIG. 2, and FIG. 4 shows a memory mat MAT of the memory block MB0 of FIG.
A partial circuit diagram of one embodiment of the unit memory array UMA0 and the unit sense amplifier US0 constituting 0 is shown. Further, FIG. 5 shows a partial circuit diagram of an embodiment of the data input / output circuit IO included in the synchronous DRAM of FIG. Based on these figures, the outline of the configuration and operation of the synchronous DRAM of this embodiment will be described first. The circuit elements forming each block in FIG. 1 are formed on a single semiconductor substrate such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique. In the following circuit diagram, the MOSFET whose channel (back gate) part has an arrow is P
Channel type, N channel M without arrow
It is shown separately from the OSFET. Further, in FIG. 2, the banks BANK0 to BANK1 will be described by taking the bank BANK0 as an example, and in FIG. 3, the memory blocks MB0 to MBF will be taken as an example by taking the memory block MB0 as an example. (Displayed in a decimal number. The same shall apply hereinafter.), The memory mats MAT0 to MAT7 will be described with reference to FIG. 4 as an example, and the write amplifiers WA0 to W will be described with reference to FIG.
AF will be described.

In FIG. 1, the synchronous DRAM of this embodiment includes banks BANK0 and BANK1, each of which serves as a memory array MARY occupying most of its layout area and a direct peripheral circuit. Row address decoder RD, sense amplifier S
A and column address decoder CD.

In this embodiment, the synchronous DRA
M has a 16-bit configuration and includes 16 data input / output terminals D0 to DF. Further, the memory arrays MARY forming the banks BANK0 and BANK1 respectively have 16 memory arrays MARY0 to MAR corresponding to the data input / output terminals D0 to DF as illustrated in FIG.
The sense amplifier SA and the row address decoder RD are also divided into YFs, and the sense amplifier SA and the row address decoder RD are also provided with 16 sense amplifiers SA0 to SAF and the row address decoder R, respectively.
It is divided into D0 to RDF. These memory array, sense amplifier, and row address decoder form memory blocks MB0 to MBF, respectively. In addition, eight columns each corresponding to the upper or lower eight bits of the input / output data are arranged adjacent to each other in the bit line extension direction, and a column address decoder CD divided into two columns, that is, column address decoders CD0 and CD1 is provided at the left end thereof. Are arranged respectively. As a result, the column address decoder CD
0 and CD1 correspond to eight corresponding memory blocks MB0
To MBF, bit line selection signals YS0 to YS0 output from these column address decoders are shared.
YSn also has eight corresponding memory blocks MB0 to MB
Shared by F respectively.

On the other hand, the memory blocks MB0 to MB shown in FIG.
The memory arrays MARY0 to MARYF forming F are
As illustrated in FIG. 3, the unit memory array is further divided into eight unit memory arrays UMA0 to UMA7 which are the minimum units, and the sense amplifier SA0 and the row address decoder RD0 also correspond to the eight unit sense amplifiers US0 to US0. It is divided into US7 and unit row address decoders URD0 to URD7. These unit memory array, unit sense amplifier and unit row address decoder form memory mats MAT0 to MATF, respectively. Hereinafter, the memory mat MAT0, the unit memory arrays UMA0 to UMA7 and the unit sense amplifiers US0 to US0 to
US7 and unit row address decoders URD0 to URD
Taking the RD7 as an example, a specific description of the memory mats MAT0 to MAT7 will be given.

The unit sense amplifiers US0 to US7 forming the memory mat MAT0 include timing generation circuits TG.
To the internal control signal PA in common, and the mat selection circuit MS supplies corresponding mat selection signals MS0 to MS7. Further, the unit row address decoders URD0 to URD0
The URD7 is commonly supplied with the internal control signal RG from the timing generation circuit TG, the common address signals X0 to Xi-4 from the row address buffer RB, and the mat selection circuit MS with the corresponding mat selection. The signals MS0 to MS7 are supplied.

Here, each of the unit memory arrays UMA0 to UMA7 forming the memory mat MAT0 is, as illustrated in FIG. 4, m + 1 word lines W0 to Wm arranged in parallel in the vertical direction of the drawing. And n + 1 sets of complementary bit lines B0 * to Bn * arranged in parallel in the horizontal direction.
And An information storage capacitor Cs and an address selection MOSF are provided at the intersections of these word lines and complementary bit lines.
(M + 1) × (n + 1) dynamic memory cells made of ETQa are arranged in a grid pattern. The drains of the address selection MOSFETs Qa of the m + 1 memory cells arranged in the same column of the unit memory arrays UMA0 to UMA7 alternate with the non-inversion or inversion signal lines of the corresponding complementary bit lines B0 * to Bn * with a predetermined regularity. Be combined with. Further, the gates of the address selection MOSFETs Qa of the n + 1 memory cells arranged in the same row are commonly coupled to the corresponding word lines W0 to Wm. A predetermined internal voltage HV is commonly supplied to the other electrodes of the information storage capacitors Cs of all the memory cells forming the unit memory arrays UMA0 to UMA7. The internal voltage H
V is set to a half potential between the power supply voltage of the circuit and the ground potential.

The word lines W0 to Wm forming the unit memory arrays UMA0 to UMA7 of the memory mat MAT0 are
Corresponding unit row address decoders URD0 to URD7
Are connected to each other, and each of them is selectively put into a selected state. These unit row address decoders are supplied with the internal address signals X0 to Xi-4 of i-3 bits excluding the upper 4 bits from the row address buffer RB and the internal control signal RG from the timing generation circuit TG. ,
Further, corresponding mat selection signals MS0 to MS7 are supplied from the mat selection circuit MS. Row address buffer R
B is supplied with X address signals AX0 to AXi in a time division manner via address input terminals A0 to Ai, and an internal control signal RL is supplied from a timing generation circuit TG.

The row address buffer RB has an X address signal A input via address input terminals A0 to Ai.
X0 to AXi are fetched and held according to internal control signal RL, and internal address signals X0 to Xi are formed based on these X address signals. Of these, the internal address signal Xi of the most significant bit is the bank selection circuit BS.
And an internal address signal Xi-3 of the next 3 bits.
~ Xi-1 are supplied to the mat selection circuit MS. Further, the remaining i-3 bit internal address signals X0 to Xi-
4 are banks BANK0 and BANK1 as described above.
Memory blocks MAT of memory blocks MB0 to MBF
0 to MAT7 are commonly supplied to all unit row address decoders URD0 to URD7.

The bank selection circuit BS decodes the internal address signal Xi supplied from the row address buffer RB and selectively sets the corresponding bank selection signals BS0 to BS1 to the high level. Further, the mat selection circuit MS is
By decoding the internal address signals Xi-3 to Xi-1,
The corresponding mat selection signals MS0 to MS7 are alternatively set to the high level. The bank selection signals BS0 to BS1 are used for the data input / output circuit IO and the column address decoder CD.
0 and CD1 supplied to each part of the synchronous DRAM, and the mat select signals MS0 to MS7 are stored in the bank BAN.
It is commonly supplied to the unit sense amplifiers US0 to US7 and the unit row address decoders URD0 to URD7 forming the corresponding memory mats MAT0 to MAT7 of the memory blocks MB0 to MBF of K0 to BANK1.

On the other hand, the unit row address decoders URD0 to URD7 forming the memory mat MAT0 are selectively activated by setting the internal control signal RG to the high level and the corresponding mat selection signals MS0 to MS7. Is activated. In this operation state, each unit row address decoder decodes the internal address signals X0 to Xi-4 to selectively select the high level selected state of the word lines W0 to Wm of the corresponding unit memory arrays UMA0 to UMA7. And

Next, the complementary bit line B0 forming the unit memory arrays UMA0 to UMA7 of the memory mat MAT0.
* To Bn * are the corresponding unit sense amplifiers US0 to US
7 corresponding unit circuits, respectively. These unit sense amplifiers have a bit line selection signal YS0 of n + 1 bits from the corresponding column address decoder CD0.
YSn is commonly supplied. Further, as described above, the timing generation circuit TG commonly supplies the internal control signal PA, and the mat selection circuit MS also supplies the corresponding mat selection signals MS0 to MS7.

The unit sense amplifiers US0 to US7 of the memory mat MAT0 correspond to the corresponding unit memory array UMA0.
To UMA7 complementary bit lines B0 * to Bn *, each of which includes n + 1 unit circuits. Each of these unit circuits includes a pair of CMOS inverters cross-coupled as illustrated in FIG. And the complementary bit lines B0 * to Bn * of the corresponding unit memory arrays UMA0 to UMA7.
In-mat complementary common data lines AC0 * to AC7 corresponding to
It includes N-channel type switch MOSFETs N2 and N3 which are respectively provided between and. Hereinafter, a specific description will be given by taking the unit sense amplifier US0 as an example.

The power supply voltage of the circuit is selectively supplied to the unit amplifier circuits USA0 to USAn forming each unit circuit of the unit sense amplifier US0 via the P-channel drive MOSFET P1 and the common source line SP, and the N-channel drive MOSFET N1. And the ground potential of the circuit is selectively supplied via the common source line SN. Drive MOSFE
The inverted internal signal PM0B of the NAND gate G5 is supplied to the gate of TP1, and the inverted signal of the inverter V3 is supplied to the gate of the drive MOSFET N1.
An internal control signal P is applied to one input terminal of the NAND gate G5.
A is supplied, and the corresponding mat selection signal MS0 is supplied to the other input terminal.

As a result, the unit amplifier circuits USA0 to US
When the internal control signal PA is set to the high level and the corresponding mat selection signal MS0 is set to the high level, An is selectively and simultaneously activated, and the selected word of the corresponding unit memory array UMA0 to UMA7 is selected. The minute read signals output from the corresponding n + 1 memory cells coupled to the lines via the corresponding complementary bit lines B0 * to Bn * are amplified and converted into high level or low level binary read signals.

On the other hand, the gates of the switch MOSFETs N2 and N3 forming each unit circuit of the unit sense amplifier US0 are commonly coupled to each other, and the column address decoder C is used.
Corresponding bit line selection signals YS0 to YSn are supplied from D0. As a result, the switch MOSFETs N2 and N3 are selectively turned on in response to the high level of the corresponding bit line selection signals YS0 to YSn, and the corresponding complementary bit lines B0 * to Bn * of the unit memory array UMA0.
And the complementary common data line AC0 * in the mat are selectively connected. The bit line selection signals YS0 to YS
n is alternatively set to a high level when the synchronous DRAM is set to the normal operation mode, and the synchronous DRA
When M is set to the block write mode, for example, YS0
8 bits are simultaneously set to a high level by a combination of ~ YS7. At this time, in the unit sense amplifier US0, 8
A pair of complementary bit lines B0 * to B7 * are simultaneously selected and simultaneously connected to the in-mat complementary common data line AC0 *.

In this embodiment, the unit sense amplifier U
S0 further includes three N-channel MOSFETs N4 to N6 that are provided between the non-inverted and inverted signal lines of the complementary common data line AC0 * in the mat to form an equalizing circuit,
It includes two sets of transfer gates T1 and T2 provided between corresponding inter-mat complementary common data line IC00 * and corresponding in-mat complementary common data line AC0 *. Of these, the transfer gates T1 and T2 are
Upon receiving the high level of the corresponding mat selection signal MS0, it is selectively turned on, and the corresponding in-mat complementary common data line AC0 * and inter-mat complementary common data line IC00 * are selectively connected. In addition, MOSFETN
4 to N6 are selectively turned on in response to the low level of the corresponding mat selection signal MS0, and the non-inversion and inversion signal lines of the mat in-mat complementary common data line AC0 * at the time of non-selection are set to an intermediate level such as the internal voltage HV. Level.

Next, the column address decoders CB0 and CD1 of the banks BANK0 and BANK1 are commonly supplied with the internal address signals Y0 to Yi of i + 1 bits from the column address buffer CB. Further, the internal control signals CG and BW are commonly supplied from the timing generation circuit TG, and the corresponding bank selection signals BS0 to BS1 are supplied from the bank selection circuit BS. The column address buffer CB is supplied with the Y address signals AY0 to AYi in a time division manner via the address input terminals A0 to Ai, and is supplied with the internal control signal CL from the timing generation circuit TG.

The column address buffer CB fetches the Y address signals AY0 to AYi supplied via the address input terminals A0 to Ai in accordance with the internal control signal CL,
The internal address signals Y0 to Yi are formed based on these Y address signals while being held and supplied to the column address decoders CD0 and CD1 of each bank. Also, the column address decoders CD0 and CD of each bank
1 is selectively activated by receiving the high level of the corresponding bank selection signals BS0 to BS1 and the internal control signal CG, decodes the internal address signals Y0 to Yi, and outputs the bit line selection signals YS0 to YSn. Select high level for each.

In this embodiment, each of the column address decoders CD0-CD1 is provided with four NAND gates G1-G1 corresponding to the bit line selection signals YS0-YSn, as shown in FIG. Including G4. Of these, one of the input terminals of the NAND gate G4 is supplied with the corresponding decode signals CDS0-CDSn from the decoder circuit (not shown) at the preceding stage, and the other input terminal is provided with the inverter V2 for the corresponding block selection signal BWS0 or the like. Eight inversion signals are sequentially supplied in common. Further, the corresponding inverted address mask control signals MC0B to MC7B are supplied from a mask register (not shown) to one input terminal of the NAND gate G3, and the corresponding block selection signal BW is supplied to the other input terminal.
S0 and the like are sequentially supplied commonly to each eight. On the other hand, the output signals of the NAND gates G3 and G4 are supplied to the two input terminals of the NAND gate G2, respectively. The output signal of the NAND gate G2 is supplied to one input terminal of the NAND gate G1, and the internal control signal CG is commonly supplied to the other input terminal. The output signal of the NAND gate G1 passes through the inverter V1 and the bit line selection signal YS.
0 to YSn, which are commonly supplied to all the unit sense amplifiers US0 to US7 constituting the memory mats MAT0 to MAT7 of the corresponding eight memory blocks MB0 to MB7 or MB8 to MBF of the banks BANK0 and BANK1.

From these facts, the bit line selection signal YS
0 to YSn, when the synchronous DRAM is in the normal operation mode and the internal control signal BW is at low level,
When the corresponding decode signals CDS0 to CDSn are respectively set to the high level to be set to the high level, the synchronous DRAM is set to the block write mode, and the internal control signal BW is set to the high level, the corresponding block selection signal BWS0. In response to a high level such as 8 bits, 8 bits are simultaneously set to a high level. It goes without saying that the bit line selection signals YS0 to YSn are formed on the condition of the high level of the internal control signal CG. Also,
At the same time, the 8-bit bit line selection signal to be set to the high level is the corresponding inverted address mask control signal MC0B.
When the low level of MC7B is received, the low level is selectively maintained and the address mask control in the column direction in the block write mode is performed.

By the way, when the synchronous DRAM is set to the normal operation mode and the bit line selection signals YS0 to YSn are alternatively set to the high level, the memory blocks MB0 to MBF of the banks BANK0 and BANK1 are as described above. , The word lines W0 to Wm forming the unit memory arrays UMA0 to UMA7 of the memory mats MAT0 to MAT7 designated by the mat selection signals MS0 to MS7 are alternatively set to a high level, and a total of 16 selected word lines are formed. 16 × (n + 1) memory cells to be coupled are coupled to corresponding unit circuits of corresponding unit sense amplifiers US0 to US7 via corresponding complementary bit lines B0 * to B7 *. At this time, the unit sense amplifiers US0 to U
S7 are selectively activated by 16 in response to the high level of the internal control signal PA and the corresponding mat selection signals MS0 to MS7. Further, a total of 16 × (n + 1) memory cells selected in the 16 unit memory arrays are respectively selected as corresponding in-mat complementary common data lines AC0 * to AC7 * according to bit line selection signals YS0 to YSn. And mat selection signals MS0 to MS
Inter-mat complementary common data lines IC00 * to IC0F * or IC10 * selectively corresponding to S7, respectively.
~ Connected to IC1F *.

Inter-mat complementary common data lines IC00 * to I
C0F * and IC10 * to IC1F * are coupled to the data input / output circuit IO. The data input / output circuit IO is supplied with bank selection signals BS0 and BS1 from the bank selection circuit BS and internal control signals WT and RD from the timing generation circuit TG. The internal control signal WT is selectively set to a high level at a predetermined timing when the synchronous DRAM is in the write mode, and the internal control signal RD is at a predetermined timing when the synchronous DRAM is in the read mode. Selectively set to high level.

The data input / output circuit IO includes complementary mat common data lines IC00 * to IC0F * and IC10 *.
.About.IC1F * includes 16 write amplifiers WA0 to WAF, main amplifiers MA0 to MAF, a data input buffer and a data output buffer. Of these, the output terminals of the write amplifiers WA0 to WAF and the input terminals of the main amplifiers MA0 to MAF are, as illustrated in FIG. 5, a transfer gate T3 and a transfer gate T3 which are selectively turned on in accordance with the bank selection signal BS0 or BS1. T
5 or corresponding inter-mat complementary common data lines IC00 * to IC0F * and IC10 via T4 and T6
* To IC1F *, respectively. Further, the input terminals of the write amplifiers WA0-WAF are coupled to the output terminals of the corresponding data input buffers, and the main amplifiers MA0-MA0 are connected.
The output terminal of the MAF is coupled to the input terminal of the corresponding data output buffer. The input terminal of each data input buffer and the output terminal of each data output buffer are commonly coupled to the corresponding data input / output terminals D0 to DF. The write amplifiers WA0 to WAF have internal control signals WT and R.
D is commonly supplied, and internal input data DI0 to DIF are supplied from corresponding data input buffers.
Corresponding IO mask control signal MIO from the mask register
0 to MIOF are supplied. Main amplifier MA0-MA
An internal control signal RD is commonly supplied to F, and its output signal is supplied to corresponding data output buffers as internal output data DO0 to DOF.

Each data input buffer of the data input / output circuit IO fetches 16-bit input data supplied via the corresponding data input / output terminals D0-DF when the synchronous DRAM is selected in the write mode. ,
The internal input data DI0 to DIF are transmitted to the corresponding write amplifiers WA0 to WAF. At this time, the write amplifiers WA0 to WAF are selectively activated by receiving the high level of the internal control signal WT, and based on the internal input data DI0 to DIF transmitted from the data input buffer, a predetermined complementary write signal. And corresponding mat complementary common data lines IC00 * to IC0F * or IC10.
* ~ IC1F * via bank BANK0 or BANK
Write to 16 selected memory cells of 1. In addition,
The data input / output circuit IO includes a color register (not shown) whose output signal is the internal input data D when the synchronous DRAM is set to the block write mode.
I0 to DIF are supplied to the write amplifiers WA0 to WAF.

By the way, each of the write amplifiers WA0-WAF constituting the data input / output circuit IO has its non-inverted output terminals WM0T-WMF, as illustrated in FIG.
T and the inverted output terminals WM0B to WMFB, that is, the non-inverted and inverted signal lines of the complementary common data lines IC00 * to IC0F * or IC10 * to IC1F * and the ground potential of the circuit (the second power supply voltage supply point). ) And N-channel type output MOSFE respectively provided between
Includes TN7 and N8. The write amplifiers WA0 to WAF will be described below using the write amplifier WA0 as an example.

The gate of the output MOSFET N7 is supplied with the inverted signal of the output signal of the NAND gate G6 by the inverter V8, and the gate of the output MOSFET N8 is supplied with the inverted signal of the output signal of the NAND gate G8 by the inverter V9. The internal control signal WT is commonly supplied to the first input terminals of the NAND gates G6 and G8, and the corresponding IO mask control signal M is supplied to the third input terminal thereof.
An inversion signal from the inverter V6 of IO0 is commonly supplied. In addition, the second input terminal of the NAND gate G8,
Corresponding internal input data DI0 is supplied, and the inverted signal of the inverter V5 is supplied to the second input terminal of the NAND gate G6.

In this embodiment, the write amplifier WA0
Is the circuit power supply voltage (first power supply voltage supply point)
And the non-inverting output terminal WM0T and the inverting output terminal WM0B, that is, the non-inverting and inverting signal lines of the inter-mat complementary common data line IC00 *, that is, precharge means, that is, a P-channel type precharge MOSFET.
Complementary common data line IC between P2 and P4 and between the non-inverting output terminal WM0T and the inverting output terminal WM0B, that is, between mats
00 * non-inverted and another P-channel type precharge MOSFET P3 provided between the inverted signal lines. The output signals of the NAND gates G9 and G11 are supplied to the gates of the MOSFETs P2 and P4, respectively.
The output signal of the NAND gate G10 is supplied to the gate of the MOSFET P3. Of these, the output signals of the NAND gates G6 and G8 are supplied to one input terminals of the NAND gates G9 and G11, respectively.
The output signal of the NAND gate G7 is supplied to one input terminal of 0. An inverted signal of the internal control signal RD from the inverter V7 is commonly supplied to the other input terminals of the NAND gates G9 to G11. The internal control signal WT is supplied to one input terminal of the NAND gate G7, and the inverted signal of the IO mask control signal MIO0 by the inverter V6 is supplied to the other input terminal.

From these facts, the output signal of the NAND gate G6 makes the corresponding IO mask control signal MIO0 low and the corresponding internal input data DI0 low when the internal control signal WT is high. As a result, the output signal of the NAND gate G6 is selectively set to the low level, and the output MOS receives the low level of the output signal.
The FET N7 is selectively turned on. The output signal of the NAND gate G8 is selectively output when the corresponding IO mask control signal MIO0 is set to low level and the corresponding internal input data DI0 is set to high level when the internal control signal WT is set to high level. Low level,
Upon receiving the low level of the output signal of the NAND gate G8, the output MOSFET N8 is selectively turned on.

On the other hand, the output signal of the NAND gate G9 is selectively set to the low level by setting the output signal of the NAND gate G6 to the high level and the internal control signal RD to the low level, and the output signal of the NAND gate G9 is set to the low level. Then, the precharge MOSFET P2 is selectively turned on. The output signal of the NAND gate G11 is selectively set to the low level by setting the output signal of the NAND gate G8 to the high level and the internal control signal RD to the low level, and receives the low level of the output signal of the NAND gate G11 to precharge the output signal. The MOSFET P4 is selectively turned on. The output signal of the NAND gate G7 is selectively set to low level by setting the internal control signal WT to high level and the corresponding IO mask control signal MIO0 to low level. Further, the output signal of the NAND gate G10 is selectively set to the low level by setting the output signal of the NAND gate G7 to the high level and the internal control signal RD to the low level.
Precharge MO in response to the low level of the output signal of 10
The SFET P3 is selectively turned on.

That is, the non-inverted and inverted signal lines of the inter-mat complementary common data line represented by IC00 * are written in the write amplifier WA0 when the synchronous DRAM is in the non-selected state and the internal control signal RD is at the low level. When the precharge MOSFETs P2 to P4 are turned on, both are precharged to a high level like the power supply voltage of the circuit. However, when the synchronous DRAM is selected in the write mode and the internal control signal WT is set to the high level, the precharge MOSFETs P2 to P4 are turned off, and instead the output MOSFETs N7 and N8 correspond to the corresponding internal input data DI0. It is selectively turned on according to the logic level. As a result, the non-inverted or inverted signal lines such as the inter-mat complementary common data line IC00 * are selectively set to the low level like the ground potential of the circuit, and the logic "0" or "1" for the selected memory cell is thereby obtained.
Writing is selectively realized.

In this embodiment, the write amplifier WA0
Of the precharge MOSFETs P2 to P4 that make up the above are selectively used even when the corresponding IO mask control signal MIO0 is at a high level, in other words, when the corresponding bit is IO masked during a write operation such as a block write mode. Is turned on. At this time, in the column address decoders CD0 and CD1, the bit line selection signals YS0 to YSn shared by the eight memory blocks MB0 to MB7 or MB8 to MBF are selectively set to a high level under a predetermined condition, and the bank BANK0.
Alternatively, in the corresponding memory block MB0 or the like of BANK1, particularly in the block write mode, the unit memory array U designated by the mat select signals MS0 to MS7.
Eight complementary bit lines B0 designated by MA0 to UMA7
Complementary common data line AC0 in mat corresponding to * to Bn *
* To AC7 *, that is, complementary complementary common data line IC0 between mats
0 * to IC0F * or IC10 * to IC1F * are simultaneously connected. Therefore, the levels of the complementary common data lines AC0 * and the like in the mat are contended by the binary read signals on the eight pairs of complementary bit lines that are simultaneously connected, and the levels of the high level such as the power supply voltage of the circuit or the ground potential of the circuit are high. I try to concentrate on such a low level.

However, in this embodiment, as described above,
Even during the IO mask in the block write mode, the precharge MOSFETs P2 to P4 of the write amplifier WA0 are turned on, so that the inter-mat complementary common data line IC00
The levels of the non-inverted and inverted signal lines such as * and the complementary common data line AC0 * in the mat are kept at a stable high level via these MOSFETs. As a result, it is simultaneously connected to the complementary common data line AC0 * in the mat 8
Even if the logical levels of the binary read signals on the complementary bit lines of the set are biased, the level inversion after the rewriting of the minority read data in the IO mask of the block write mode is prevented, and the reliability of the synchronous DRAM is thereby prevented. Can be increased.

Next, the main amplifiers MA0 to MAF of the data input / output circuit IO are selectively activated by receiving the high level of the internal control signal RD when the synchronous DRAM is selected in the read mode. It In this operating state, the main amplifiers MA0 to MAF operate in the bank B
From the 16 memory cells selected in ANK0 or BANK1, the corresponding inter-mat complementary common data line IC00 * to
The binary read signal output via IC0F * or IC10 * to IC1F * is further amplified and transmitted to the corresponding data output buffer as internal output data DO0 to DOF. These internal output data are output from the respective data output buffers to the outside of the synchronous DRAM via the corresponding data input / output terminals D0 to DF.

The timing generation circuit TG has a clock signal CLK supplied from the outside, a clock enable signal CKE serving as a start control signal, a chip selection signal CSB, a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB. In addition, the above various internal control signals are selectively formed based on the special function signal DSF and are supplied to each unit.

FIG. 6 shows a signal waveform diagram of an embodiment of the block write mode of the synchronous DRAM of FIG. Based on the figure, the synchronous DR of this embodiment
The details and features of the AM block write mode will be described. The block write mode of the synchronous DRAM of this embodiment has two special mode register set cycles for setting color data in the color register and IO mask data in the mask register, and a memory cell to be written. A row active command cycle for designating a row address and starting a selection operation of the word lines W0 to Wm, and a write command cycle for designating a column address of a memory cell to be written and executing a substantial block write. However, only the write command cycle is shown in FIG. Further, in FIG. 4, a cycle A without an IO mask and a cycle B with an IO mask are consecutively shown, but in practice, a special mode for rewriting a mask register is provided between these cycles. It goes without saying that a register set cycle is required. Further, in this embodiment, the memory block MB
8 memory mats MAT0 to M that compose 0 to MBF
The memory mat MAT0 corresponding to the mat select signal MS0 is selected from AT7 and is coupled to the complementary bit lines B0 * to B7 * of the unit memory array UMA0 forming each memory mat MAT0 as a target of the block write mode. Each memory cell is selected. The following detailed description of the IO mask in the block write mode will be given in the data input / output terminal D0, that is, the memory block MB0
And its related parts as an example.

In FIG. 6, the synchronous DRAM is
Although not particularly limited, the row address strobe signal RA (not shown) is not shown at the rising edge of the clock signal CLK.
When the SB is set to the high level and the chip selection signal CSB, the column address strobe signal CASB and the write enable signal WEB are set to the low level, the write command cycle is started, and the special function signal DS is generated at the rising edge of the clock signal CLK.
The block write mode is designated by setting F to the high level. The address input terminals A0 to Ai are
Prior to the rise of the clock signal CLK, the Y address signals AY except the lower 3 bits, that is, AY3 to AYi are supplied in a combination designating the first block BWS0 of the complementary bit lines, and the data input / output terminals D0 to DF are supplied in the column direction. The address mask data for selectively performing the write mask of is supplied. Since the address mask has no direct relation to the present invention, detailed description thereof will be omitted.

Memory block M of the synchronous DRAM
In B0, the mat select signal MS0 is alternatively set to the high level in the row active command cycle executed immediately before. Further, in response to the high level of the mat selection signal MS0, the unit row address decoder URD0 of the memory mat MAT0 is activated, and the designated word line Ws of the unit memory array UMA0 is selectively set to the high level. Unit sense amplifier U
In-mat complementary common data line AC0 corresponding to S0
* Is connected to the inter-mat complementary common data line IC00 *. In the unit sense amplifier US0, the internal control signal PA is set to the high level when the selecting operation of the word line Ws is completed, and the complementary bit line B0 * of the unit memory array UMA0 is set.
A binary read signal according to the data held in the memory cells coupled to the word line Ws is established in the memory cells B7 * to B7 *. In the data input / output circuit IO, the transfer gates T3 and T5 are turned on in response to the high level of the bank selection signal BS0, and the inter-mat complementary common data line I
The C00 * and the write amplifier WA0 are connected. Immediately before the write command cycle is executed, the internal control signals WT and RD are set to the low level, and the bit line selection signals YS0 to YSn are all set to the low level. Therefore, the preamplifier of the write amplifier WA0 of the data input / output circuit IO is set. The charge MOSFETs P2 to P4 are turned on, and the non-inverted and inverted signal lines of the inter-mat complementary common data line IC00 * and the in-mat complementary common data line AC0 * are both precharged to a high level like the power supply voltage of the circuit.

In the synchronous DRAM in which the write command cycle in the block write mode is identified at the start of cycle A, the internal control signal BW is first set to the high level and the IO mask control signals MIO0 to MIOF are set in accordance with the output of the mask register. Selectively set to high level. Incidentally, these IO mask control signals MIO0
~ MIOF is set to a high level when the corresponding bit is a target of the IO mask, and is a low level when the corresponding bit is not a target of the IO mask. Therefore, in the cycle A in which the IO mask for the first bit of the color data is not performed, the IO
The mask control signal MIO0 is at low level. In the synchronous DRAM, the internal control signal W
T is set to the high level, and the 8-bit bit line selection signal YS0 corresponding to the block selection signal BWS0 is set at a predetermined timing while the internal control signal WT is set to the high level.
~ YS7 are simultaneously set to high level.

As a result, first, in the data input / output circuit IO, the write amplifiers WA0-WAF are activated simultaneously upon receiving the high level of the internal control signal WT, and the corresponding I
On condition that the O mask control signals MIO0 to MIOF are at the low level, the MOSFETs N7 and N8 have corresponding bits of the color data, that is, the internal input data DI0 to D0.
It is selectively turned on according to IF. At this time, IO
In the inter-mat complementary common data line IC00 * which is not the object of masking, the non-inverted and inverted signal lines are selectively set to a low level like the ground potential of the circuit according to the first bit of the color data, that is, the internal input data DI0. Then, a complementary write signal is output. This complementary write signal is supplied to the selected eight complementary bit lines B of the unit memory array UMA0 via the complementary common data line AC0 * in the mat.
0 * to B7 * are transmitted, and the level of the binary read signal is inverted if necessary. As a result, the word line Ws of the unit memory array UMA0 and the complementary bit lines B0 * to B0
For 8 memory cells located at the intersection with 7 *,
Writing of the same data is realized.

On the other hand, in cycle B, the IO mask for the first bit of the color data is performed, so that the IO mask control signal MIO0 is set to the high level following the high level of the internal control signal BW. Therefore, the write amplifier WA0 of the data input / output circuit IO receives the high level of the IO mask control signal MIO0 and outputs the output MOSFETN.
7 and N8 remain in the off state, and instead the precharge MOSFETs P2 to P4 are turned on. Therefore, the non-inverted and inverted signal lines of the inter-mat complementary common data line IC00 * are both brought to a high level like the power supply voltage of the circuit via these MOSFETs, and the non-inverted mat common data line AC0 * of the corresponding in-mat complementary common data line AC0 * is not set. Both the inversion and the inversion signal line are set to the high level.

By the way, the synchronous DR of this embodiment
In the AM, as described above, the column address decoder CD
0 or the bit line selection signal YS0 output from CD1
Eight memory blocks MB0 to MB7 corresponding to YSn
Alternatively, it is shared by MB8 to MBF and is formed regardless of the IO mask. Therefore, even in the cycle B in which the first bit of the color data is the target of the IO mask, the bit line selection signals YS0 to YS7 are set to the high level at a predetermined timing, and the complementary bit lines B0 * to B7 * of the unit memory array UMA0. And the complementary common data line AC0 * in the mat are connected. Therefore, the levels of the non-inverted and inverted signal lines of the complementary common data line AC0 * in the mat are set to the eight complementary bit lines B0 * to B7 selected.
* Attempts to change according to the binary read signal above. However, in the synchronous DRAM of this embodiment, as described above, the corresponding bits of the color data are the targets of the IO mask and the corresponding IO mask control signals MIO0 to M0.
When the IOF is high level, the data input / output circuit I
Precharge MOS of O write amplifiers WA0 to WAF
Since the FETs P2 to P4 are turned on, the level changes of the non-inverted and inverted signal lines of the in-mat complementary common data line AC0 * are suppressed. As a result, the complementary bit lines B0 * to
Even if the logical level of the binary read signal on B7 * is biased, the level inversion after rewriting the minority read data is eliminated, and thereby the reliability of the synchronous DRAM can be improved.

FIG. 7 is a block diagram of an embodiment of a computer system to which the synchronous DRAM of FIG. 1 is applied. Further, FIG. 8 shows an application example of the block write mode of the synchronous DRAM in the computer system of FIG. 7 and its conceptual diagram. Based on these figures, an application example of the synchronous DRAM of this embodiment and its block write mode and its features will be described.

In FIG. 7, the synchronous DRAM of this embodiment has a so-called stored program type central processing unit CPU as its basic constituent element. The central processing unit CPU is provided with a random access memory RA composed of an ordinary static RAM via a system bus SBUS.
M1 and random access memory RAM2, which is a synchronous DRAM to which the present invention is applied, are coupled.
The system bus SBUS is further coupled with a read-only memory ROM including a mask ROM and the like, a display control device DPYC and a peripheral device controller PERC. The display control device DPYC includes an image memory VRAM including a synchronous DRAM to which the present invention is applied. A display device DPY is connected to the display control device DPYC, and a keyboard KBD and an external storage device EXM are connected to the peripheral device controller PERC.

The central processing unit CPU performs step operations according to a control program stored in advance in the read-only memory ROM, and controls / controls each unit of the computer system. The random access memory RAM1 is used as, for example, a cache memory, and the random access memory RAM2 is, for example, a read-only memory R.
It is used as a buffer memory for temporarily storing and relaying control programs, operation data, etc. transmitted from the OM to the central processing unit CPU. Further, the display control device DPYC is used for display control of the display device DPY, and the peripheral device controller PERC controls the keyboard K.
Controls various peripheral devices such as BD and external storage device EXM
Govern. The computer system is a power supply POWS
This power supply device POWS forms a stable predetermined DC power supply voltage based on a predetermined input AC voltage and supplies it to each unit of the computer system.

In this embodiment, the synchronous DRAM constituting the random access memory RAM2 and the image memory VRAM of the display control device DPYC has the IO maskable block write mode as described above, and its data input / output. Since the write amplifiers WA0 to WAF configuring the circuit IO include precharge MOSFETs P2 to P4 which are selectively turned on when the corresponding bits of the input data are targeted for the IO mask, eight sets of simultaneously connected sets. Even if the logical levels of the binary read signals on the complementary bit lines are biased, there is no level inversion after the rewriting of the minority data at the time of IO masking, and there is high reliability. As a result, the reliability of the random access memory RAM2 and the image memory VRAM is improved without impairing the cost reduction, and the reliability of the computer system is improved.

In the block write mode of the synchronous DRAM, as shown in the application example to the image memory VRAM in FIG. 8, for example, at the time of screen initialization or background coloring,
It is used to rewrite the display screen of the display device DPY at a high speed in units of 8 pixels. The address mask is used to selectively stop the rewriting of the color data C0 to C7 in the column address direction, which is the target of the block write mode, for each column address, and the IO mask is the color data of each pixel. It is used to selectively stop direction rewriting bit by bit.

The operational effects obtained by the above embodiment are as follows. That is, (1) In a synchronous DRAM or the like having a block write mode capable of IO masking, for example, between the power supply voltage of the circuit and the non-inverted and inverted signal lines of the complementary common data line is selectively turned on when not selected. Therefore, P-channel MOSFETs for precharging the non-inverted and inverted signal lines of the complementary common data line to the high level are provided respectively, and these MOSFETs are turned on even during IO mask in the block write mode. , It is possible to sufficiently increase the levels of the non-inverted and inverted signal lines of the complementary common data line to be IO masked without providing a switch MOSFET for controlling the IO mask for each bit line. Even if the logic level of the read data of the complementary bit line of B is biased, rewriting of the minority data It is possible to obtain an effect that it is possible to prevent the level inversion after the completion.

(2) According to the above item (1), the reliability of the synchronous DRAM or the like can be improved without impeding cost reduction. (3) Synchronous DRAM according to the above items (1) and (2)
Is used as a buffer memory or an image memory that configures a computer system, an effect is obtained that the cost of the buffer memory and the image memory, and eventually the computer system including the same can be reduced, and the reliability thereof can be improved. .

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the synchronous DRAM can have an arbitrary bit configuration such as a so-called x1 bit configuration or x8 bit configuration, and can have an arbitrary number of banks. In addition, complementary common data lines IC00 * to I between mats
C0F * and IC10 * to IC1F * can be separated for writing and reading by use, and the data input / output terminals D0 to DF can also be separated for use as data input terminals and data output terminals. further,
Various embodiments can be adopted for the block configuration of the synchronous DRAM, the combination of the activation control signal and the internal control signal, the logic level, and the like.

In FIG. 2, the correspondence between the column address decoder and the memory blocks MB0 to MBF is not restricted by this embodiment. In FIG. 3, the memory blocks MB0 to MBF can include any number of memory mats. Further, one unit sense amplifier can be associated with two or more sets of complementary common data lines in the mat, and unit memory arrays can be arranged on both sides of each unit sense amplifier to adopt the shared sense system. FIG.
In FIG. 5, MOSFETs P2 to P4 for holding the level of the complementary common data line AC0 * in the mat at the high level during the IO mask are the unit memory array UMA.
It may be provided inside the transfer gates T1 and T2 such as 0, that is, on the complementary common data line AC0 * side in the mat. In this case, the IO mask control signal MIO0 and the like need to be ANDed with the mat select signal MS0 and the like. The in-mat complementary common data lines AC0 * and the like and the inter-mat complementary common data lines IC00 * and the like may correspond to each other in a one-to-one correspondence, and the unit memory array UMA0 and the like, the unit sense amplifier US0 and the write amplifier WA0 and the like Various embodiments can be adopted for the configuration, the polarity and absolute value of the power supply voltage, the conductivity type of the MOSFET, and the like. In FIG. 6, the logic levels of the start control signal and the internal control signal and the combination thereof are not restricted by this embodiment. In FIG. 7, the block configuration of the computer system can adopt various embodiments, and the application range of the synchronous DRAM of this embodiment is not restricted by this embodiment.

In the above description, the case where the invention made by the present inventor is applied to the synchronous DRAM and the computer system to which the invention is applied, which is the background of the invention, has been mainly described. However, the invention is not limited thereto. Not, for example, multiport video R
It can be applied to various memory integrated circuits such as AM and various digital systems including similar memory integrated circuits. The present invention can be widely applied to at least a semiconductor memory device having an IO maskable block write mode, and a device and a system including such a semiconductor memory device.

[0061]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a synchronous DRAM or the like having an IO maskable block write mode, for example, between the power supply voltage of the circuit and the non-inverted and inverted signal lines of the complementary common data line for transmitting the write signal, when not selected, A P-channel MOSFET for precharging the non-inverted and inverted signal lines of the complementary common data line to a high level by being turned on is provided, and these MOSF
By keeping ET on during the IO mask in the block write mode, the non-inversion and inversion signal lines of the complementary common data line to be the IO mask are not provided without providing the switch MOSFET for mask control for each bit line. Since the read data of multiple complementary bit lines selected simultaneously can be prevented from conflicting with each other by sufficiently increasing the level of, even if the logical levels of these read data are biased, the level after rewriting the minority data Inversion can be prevented. As a result, the synchronous D having the block write mode can be realized without impeding the cost reduction.
The reliability of RAM and the like can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

2 is a block diagram showing an embodiment of a bank included in the synchronous DRAM of FIG.

FIG. 3 is a block diagram showing an embodiment of a memory block included in the bank of FIG.

FIG. 4 is a partial circuit diagram showing an embodiment of a unit memory array and a unit sense amplifier which form each memory mat of the memory block of FIG.

5 is a partial circuit diagram showing an embodiment of a data input / output circuit included in the synchronous DRAM of FIG.

6 is a signal waveform diagram showing an embodiment of a block write mode of the synchronous DRAM of FIG.

7 is a block diagram showing an embodiment of a computer system to which the synchronous DRAM of FIG. 1 is applied.

8 is an application example of a block write mode of a synchronous DRAM in the computer system of FIG. 7 and its conceptual diagram.

FIG. 9 is a partial circuit diagram showing an example of a unit memory array and a unit sense amplifier included in a synchronous DRAM developed by the inventors of the present application prior to the present invention.

[Explanation of symbols]

BANK0-BANK1 ... Bank, MARY ...
Memory array, RD ... Row address decoder, SA
... Sense amplifier, CD ... Column address decoder, BS ... Bank selection circuit, MS ... Mat selection circuit, RB ... Row address buffer, CB ... Column address buffer, IO ... Data input / output circuit,
TG ... Timing generation circuit. MB0 to MBF ...
Memory block, MARY0 to MARYF ... Memory array, RD0 to RDF ... Row address decoder,
SA0-SAF ... sense amplifier, CD0-CD1
..Column address decoders, IC00 * to IC0F
*, IC10 * to IC1F * ... Complementary common data line between mats. MAT0 to MAT7 ... Memory mat, UM
A0 to UMA7 ... Unit memory array, US0 to US
7 ... Unit sense amplifier, URD0-URD7 ...
Unit row address decoder. Cs ... Information storage capacitor, Qa ... Address selection MOSFET, W0-W
m: word line, B0 * to Bn * ... complementary bit line, USA0 to USAn ... unit amplifier circuit, YS0 to
YSn ... bit line selection signal, AC0 * to AC7 *
..Complementary common data line in mat. WA0 ... write amplifier, MA0 ... main amplifier. P1-P4 ... P
Channel MOSFET, N1 to N10 ... N channel MOSFET, T1 to T6 ... Transfer gate, V1 to V9 ... Inverter, G1 to G11 ...
NAND gate. CPU ... Central processing unit, SBUS ... System bus, RAM0-RAM2
・ ・ ・ Random access memory, ROM ・ ・ ・ ・ Read only memory, DPYC ・ ・ ・ Display control device, VRAM ・ ・ ・ Image memory, DPY ・ ・ ・ Display device, PERC ・ ・ ・ Peripheral device controller, KB
D ... Keyboard, EXM ... External storage device, PO
WS: Power supply device.

Claims (3)

[Claims] 1. The same content can be written to a plurality of addresses by simultaneously connecting a plurality of bit lines to each of the common data lines, and the writing of the same content to the plurality of addresses can be selectively performed for each common data line. Precharge means having a block write mode that can be masked, and is provided between each of the common data lines and a predetermined potential supply point and is selectively turned on during non-selection and during masking in the block write mode. A semiconductor memory device comprising: 2. The semiconductor memory device comprises: a plurality of memory mats; and an in-mat common data line which is provided corresponding to the memory mats and to which designated bit lines of the corresponding memory mats are selectively connected. An inter-mat common data line to which the designated in-mat common data line is selectively connected; and a write amplifier whose output terminal is coupled to the corresponding inter-mat common data line. The potential supply point is a first power supply voltage supply point, and the precharge means comprises a P-channel MOSFET provided between each of the mat common data lines and the first power supply voltage supply point. Therefore, the write amplifier is provided between each of the inter-mat common data lines and the second power supply voltage supply point, and according to the corresponding bit of the write data. 2. The semiconductor memory device according to claim 1, including an N-channel MOSFET that is selectively turned on. 3. The semiconductor memory device comprises a synchronous D
In the RAM, a bit line selection signal for selectively connecting a bit line designated to each of the common data lines in the mat is shared by the plurality of memory mats. Claim 1 or Claim 2
Semiconductor memory device.