JPH11265571A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To increase the speed of a dynamic RAM or the like using a boost sense system while suppressing the increase in cost. SOLUTION: In a dynamic RAM or the like employing a boost sense system and a shared sense system, boost capacitors C1 to C4 for boost sense are not provided in a sense amplifier SA and memory arrays ARY and ARY are provided.
R, and these boost capacities are adjusted by an address selection MO constituting a dynamic memory cell of the memory array.
MOSFE having the same element structure as SFET
It is configured based on T. Also, during the operation of boosting the potential of the complementary bit line by the boost capacitance, the shared amplifier M of the sense amplifier SA, for example, on the selected memory array ARYL side
The OSFETs N4 and N5 are kept on, the sense amplifier SA is of an overdrive sense type, and the potential of the high-potential side common source line CSP is set to the non-inverted or inverted input / output of each unit amplifier circuit for a predetermined period at the beginning of driving. Overdrive to a potential VCC higher than the final high level VDL at the node.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic RAM (random access memory) employing a boost sense system and a technique particularly effective when used for speeding up and reducing power consumption. is there.

[0002]

2. Description of the Related Art A memory array including word lines and complementary bit lines arranged orthogonally, dynamic memory cells arranged in a lattice at the intersections of these word lines and complementary bit lines, and each complementary bit line of the memory array There is a semiconductor memory device such as a dynamic RAM including a sense amplifier including a unit amplifier circuit provided corresponding to the above. In such a dynamic RAM or the like, a pair of boost capacitors are provided between the non-inverting and inverting input / output nodes of each unit amplifier circuit constituting the sense amplifier and the boost control signal line, and the selected word line of the memory array is provided. After the minute read signal of the memory cell coupled to the corresponding complementary bit line is output, the potential of the non-inverting and inverting input / output nodes of each unit amplifier circuit is raised to reduce the voltage of the dynamic RAM or the like. So-called CABS method (Charge Amp) which can accelerate the read operation.
living-Boosted Sensing S
scheme), for example, 19
May 1997, IEE Journal of Solid State Circuits (J
OURRNAL OF SOLID-STATE CIR
CUITS), VOL. 32, no. 5, from page 642
Page 648.

[0003]

Prior to the present invention, the inventors of the present invention have noticed the following problems while studying the dynamic RAM employing the CABS method. That is, a CABS dynamic RAM
Includes a sense amplifier SA including n + 1 unit circuits provided corresponding to the complementary bit lines BL0 * to BLn * and BR0 * to BRn * of the memory arrays ARYL and ARYR, as illustrated in FIG. Each of these unit circuits includes a unit amplifier circuit UA in which a pair of CMOS (complementary MOS) inverters are cross-coupled.
The non-inverting input / output nodes S0T to SnT of each unit amplifier circuit UA of the sense amplifier SA (here, a so-called non-inverting signal or the like which is selectively set to a high level when it is enabled is added to the end of its name. T. The same applies to the following, and inverted input / output nodes S0B to SnB (here, a so-called inverted signal or the like which is selectively set to a low level when it is enabled is suffixed with B at the end of its name).
And is represented by The same applies to the following) and the boost control signal line BST
Are provided with a pair of boost capacitors C5 and C6.

The boost control signal line BST to which the drain-source electrodes of the boost capacitors C5 and C6 constituting each unit circuit of the sense amplifier SA are coupled has, as illustrated in FIG. 6, a normal ground potential VSS. And the selected word line WL of the memory array ARYL, for example.
The complementary bit line BL0 * to which the minute read signal corresponding to the data held in the (n + 1) memory cells coupled to 0 corresponds
To BLn * (here, for example, the non-inverted bit line BL0T and the inverted bit line BL0B
It is represented by adding * like 0 *. The same applies to the following), that is, the signals are output to the complementary input / output nodes S0 * to Sn * of the corresponding unit amplifier circuit UA of the sense amplifier SA, and these complementary input / output nodes and the memory arrays ARYL and ARYR on both sides are output.
When the shared MOSFETs N4 and N5 and NB and NC provided between the complementary bit lines BL0 * and BR0 * to BRn * are all turned off, the power supply voltage is set to a high level like the power supply voltage VCC. In response to the rise of the boost control signal BST to a high level, the boost capacitors C5 and C6 simultaneously boost the potentials of the non-inverting input / output nodes S0T to SnT and the inverting input / output nodes S0B to SnB of each unit amplifier circuit UA. , To increase the level difference a little.

[0005] As a result, the amplification operation of the unit amplifier circuit UA is accelerated, but, for example, after the word line WL0 of the memory array ARYL is selected and before the boost control signal BST is set to the high level, the selected word line is changed. The signal amount of the minute read signal of the (n + 1) memory cells coupled to WL0 is equal to the complementary bit line BL0 * of the memory array ARYL.
To BLn *, ie, the complementary input / output nodes S0 * to Sn * of the sense amplifier SA, and are shared MOSFETs N4 and N5 corresponding to the memory array ARYL.
It is necessary to allow a relatively long time for all the devices to be turned off, and this does not speed up the operation of the dynamic RAM as desired.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic RAM employing a boost sense system while suppressing an increase in cost.
And to speed up the operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a dynamic RAM or the like that employs a boost sense system and a shared sense system, a boost capacitance for boost sense is provided in a memory array without being provided in a sense amplifier, and these boost capacitances are provided by the dynamic type of the memory array. It is constructed based on MOSFETs having basically the same element structure as the address selection MOSFETs constituting the memory cell. In addition, while the potential boosting operation of the complementary bit line by the boost capacitance is performed, the shared MOSFET on the selected memory array side of the sense amplifier is kept on, and the sense amplifier is set to the overdrive sense method,
The potential of the high-potential-side common source line is overdriven to a potential higher than the final high level at the non-inverted or inverted input / output node of each unit amplifier circuit for a predetermined period at the beginning of driving.

According to the above means, the boosting of the potential of the complementary bit line by these boost capacitors can be started at an early stage while suppressing the increase in the chip size due to the provision of the boost capacitors for the boost sense. Increase the high level of the non-inverted or inverted signal line of each complementary bit line, and pull-up MOSFET
The voltage between the drain and the source can be increased to speed up the amplification operation. As a result, the operation of the dynamic RAM can be sped up while suppressing the cost increase of the dynamic RAM, and the operating power supply of the dynamic RAM or the like is sufficiently lowered to suppress the rise of the chip temperature. The refresh characteristics as described above can be greatly improved.

[0010]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM (semiconductor memory device) to which the present invention is applied. First, an outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. Although the circuit elements constituting each block in FIG. 1 are not particularly limited, a well-known MOSFET (metal oxide semiconductor type field effect transistor. In this specification, a MOSFET is a generic name of an insulated gate type field effect transistor). Is formed on one semiconductor substrate surface, such as single crystal silicon, by an integrated circuit manufacturing technique.

In FIG. 1, the dynamic RAM of this embodiment includes, but is not limited to, eight memory mats MAT0 to MAT7. Dynamic type R
AM adopts a shared sense system and uses a memory mat MAT.
0 to MAT7, as represented by the memory mat MAT0, a pair of memory arrays ARYL and ARYR sandwiching the sense amplifier SA, and a pair of X address decoders XDL provided corresponding to each memory array.
And XDR. Memory mats MAT0-MAT
7 further includes a Y address decoder YD provided commonly to both memory arrays, a write amplifier WA and a main amplifier MA.

The memory arrays ARYL and ARYR of the memory mats MAT0 to MAT7 have a predetermined number of word lines arranged in parallel in the vertical direction and a predetermined number of complementary bit lines arranged in parallel in the horizontal direction. And respectively.
At the intersections of these word lines and complementary bit lines, a large number of dynamic memory cells composed of information storage capacitors and address selection MOSFETs are arranged in a grid.
The boost control signal BSTL is supplied from the timing generation circuit TG to the memory array ARYL, and the boost control signal BSTR is supplied to the memory array ARYR.

In this embodiment, a dynamic RA
M employs a boost sensing method. Boost capacitances required for boost sensing are provided not at the sense amplifier SA but at predetermined positions of the memory arrays ARYL and ARYR. These boost capacitances are composed of MOSFETs having basically the same element structure as the address selection MOSFETs constituting the memory cells of the memory arrays ARYL and ARYR. When the boost control signal BSTL or BTL is output to the non-inversion or inversion signal line of the line,
When STR is changed from a low level such as the ground potential VSS to a high level such as the power supply voltage VCC, the potentials of the corresponding complementary bit lines are boosted. The specific configuration of the memory arrays ARYL and ARYR including the boost capacitance, the specific operation at the time of boost sensing, and the characteristics thereof will be described later in detail.

The word lines constituting the memory arrays ARYL and ARYR of the memory mats MAT0 to MAT7 are coupled to corresponding X address decoders XDL or XDR below them, and each of them is alternatively selected. To the X address decoders XDL and XDR of the memory mats MAT0 to MAT7, the i + 1-bit internal address signals X0 to Xi are commonly supplied from the X address buffer XB, and the internal control signal XG (not shown) is commonly supplied from the timing generation circuit TG. Supplied to Also,
The X address buffer XB receives an X address signal A from an external access device through address input terminals A0 to Ai.
X0 to AXi are supplied in a time-division manner, and an internal control signal XL is supplied from the timing generation circuit TG.

An X address buffer XB is provided with an X address signal AX supplied through address input terminals A0 to Ai.
0 to AXi are taken in according to the internal control signal XL, held, and based on these X address signals, internal address signals X0 to Xi are formed to generate a memory mat MAT.
0 to MAT7 to the X address decoders XDL and XDR. At this time, the memory mats MAT0 to MAT7
The X address decoders XDL and XDR selectively operate when the internal control signal XG is set to the high level and the internal address signal Xi of the most significant bit is set to the low level or the high level, for example. Address signals X0 to X supplied from
i to decode the memory array ARYL or ARYR
Is alternatively set to a selected level such as the internal voltage VPP. Note that the internal address signal Xi of the most significant bit output from the X address buffer XB is
It is also supplied to a timing generation circuit TG described later.

Next, the complementary bit lines forming the memory arrays ARYL and ARYR of the memory mats MAT0 to MAT7 are respectively connected to corresponding unit circuits of the sense amplifier SA on the inside. The sense amplifier SA is supplied with n + 1-bit bit line selection signals YS0 to YSn (not shown) from the Y address decoder YD, and shared control signals SHL and SHR, a precharge control signal PC, and a sense amplifier drive from the timing generation circuit TG. Signals PA1, PA2B and PA3 are provided. The Y address decoder YD supplies the i + 1 bit internal address signal Y from the Y address buffer YB.
0 to Yi, and the timing generation circuit T
G supplies an internal control signal YG (not shown). Y
Address buffer YB is supplied with i + 1-bit Y address signals AY0 to AYi in a time-sharing manner from an external access device via address input terminals A0 to Ai, and is supplied with an internal control signal YL from timing generation circuit TG. .

The Y address buffer YB is provided with a Y address signal AY supplied via address input terminals A0 to Ai.
0 to AYi in accordance with the internal control signal YL and hold the same, and form the internal address signals Y0 to Yi based on these Y address signals to obtain the memory mat MAT.
0 to MAT7 to the Y address decoder YD. At this time, the Y address decoders YD of the memory mats MAT0 to MAT7 are selectively activated by receiving the high level of the internal control signal YG, and the internal address signals Y0 to Y
i, and the corresponding bits of the bit line selection signals YS0 to YSn for the sense amplifier SA are alternatively set to the high level.

Each of the sense amplifiers SA of the memory mats MAT0 to MAT7 includes a predetermined number of unit circuits provided corresponding to respective complementary bit lines of the memory arrays ARYL and ARYR. Each of these unit circuits is a pair of CMOs.
A unit amplifier circuit having S inverters cross-coupled;
It includes a bit line precharge circuit in which three channel type precharge MOSFETs are connected in series and parallel, and a pair of N channel type switch MOSFETs. Each unit circuit of the sense amplifier, that is, the complementary input / output node of each unit amplifier circuit has a shared control signal SH
N-channel type shared MOSFET receiving L in common
A corresponding complementary bit line of the memory array ARYR is coupled to the corresponding complementary bit line of the memory array ARYL via a T and another N-channel type shared MOSFET receiving the shared control signal SHR in common on the right side thereof. Respectively.

The shared control signals SHL and SHR
As described later, when the dynamic RAM is set to the non-selected state, it is set to a predetermined high level. When the dynamic RAM is set to the selected state, one of them is set according to, for example, the internal address signal Xi of the most significant bit. One of them is selectively set to a predetermined low level. Thereby, the complementary input / output node of each unit circuit of the sense amplifier SA is connected to the non-selected state of the dynamic RAM.
Both are connected to the corresponding complementary bit lines of the memory arrays ARYL and ARYR via the corresponding shared MOSFETs, respectively. When the dynamic RAM is selected, only one of them is selectively selected according to the internal address signal Xi. Connected.

A precharge MOSFET constituting a bit line precharge circuit of each unit circuit of the sense amplifier SA
When the dynamic RAM is set to the non-selection state, it receives the high level of the precharge control signal PC and is selectively and simultaneously turned on, and the non-inverting and inverting input / output nodes of the corresponding unit circuit, that is, the memory array The non-inverted and inverted signal lines of the complementary bit lines of ARYL and ARYR are precharged to the intermediate voltage HV between the internal voltage VDL and the ground potential VSS.

On the other hand, the unit amplifier circuit of each unit circuit of the sense amplifier SA includes sense amplifier drive signals PA1 and PA3.
Of the memory array ARYL or ARYR and the corresponding complementary bit from a predetermined number of memory cells coupled to the selected word line of the memory array ARYL or ARYR. The small read signals output via the lines are respectively amplified to obtain a binary read signal in which the internal voltage VDL is finally set to a high level and the ground potential VSS is set to a low level. The switch MOSFET of each unit circuit is
In response to the high level of the bit line selection signals YS0 to YSn supplied from the Y address decoder YD, they are selectively turned on, and the complementary input / output nodes of the corresponding unit amplifier circuits of the sense amplifier SA and the complementary common data lines CD * Are selectively connected.

In this embodiment, a dynamic RA
M employs the boost sensing method as described above, and the boost capacitance provided corresponding to each complementary bit line of the memory arrays ARYL and ARYR is set immediately before each unit amplifier circuit of the sense amplifier SA is brought into the operating state. , The potential of the non-inverting and inverting signal lines of the complementary bit line corresponding to is raised. Further, the dynamic RAM of this embodiment employs an overdrive sense system, and a common source line for supplying high-potential-side operation power to the unit amplifier circuit is provided with a non-inverted or non-inverted A final high level at the inverting input / output node, that is, a power supply voltage VCC higher than the internal voltage VDL is temporarily supplied. This speeds up the operation of the dynamic RAM. The specific configuration of the sense amplifier SA, the specific contents of the overdrive sensing operation, and the features thereof, including this, will be described later in detail.

The complementary common data lines CD * of the memory mats MAT0 to MAT7 are commonly connected to the output terminal of the corresponding write amplifier WA and the input terminal of the main amplifier MA, respectively. The input terminal of the write amplifier WA of each memory mat is coupled to the output terminal of the corresponding unit circuit of the data input buffer IB via the corresponding bit of the write data bus WDB0-WDB7, and the output terminal of the main amplifier MA of each memory mat. The terminal is connected to the read data bus RDB0.
RDB7 to the input terminal of the corresponding unit circuit of the data output buffer OB via the corresponding bit. An input terminal of each unit circuit of the data input buffer IB and an output terminal of each unit circuit of the data output buffer OB are commonly coupled to corresponding data input / output terminals D0 to D7, respectively. An internal control signal WP (not shown) is commonly supplied from a timing generation circuit TG to the write amplifiers WA of the memory mats MAT0 to MAT7, and an internal control signal OC is commonly supplied to each unit circuit of the data output buffer OB. .

Each unit circuit of the data input buffer IB includes:
When the dynamic RAM is set to the selected state in the write mode, 8-bit write data input through the data input / output terminals D0 to D7 is fetched and held, and the corresponding data is written via the write data buses WDB0 to WDB7. The signal is transmitted to the write amplifiers WA of the memory mats MAT0 to MAT7. At this time, the write amplifier WA of each memory mat is selectively activated in response to the high level of the internal control signal WP, and the write data buses WDB0 to WDB0 to WDB0 to WDB0 to
After the write data transmitted via DB7 is converted into a predetermined complementary write signal, the corresponding memory array ARYL is supplied from complementary common data line CD * via sense amplifier SA.
Alternatively, data is written into a selected one of ARYR, that is, a total of eight memory cells.

On the other hand, when the dynamic RAM is set to the read mode, the memory mats MAT0 to MAT7 supply complementary common data from a total of eight selected memory cells of the corresponding memory array ARYL or ARYR. The binary read signal output via the line CD * is further amplified and read data buses RDB0 to RDB0
The data is transmitted to the corresponding unit circuit of the data output buffer OB via the RDB 7. At this time, the data output buffer OB
Are selectively operated in response to the high level of the internal control signal OC, and the corresponding main amplifier MA
Read signals transmitted from the data input / output terminals D0 to D0
Output via D7.

The timing generation circuit TG includes a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB supplied as a start control signal from an external access device.
Based on the most significant bit internal address signal Xi supplied from the address buffer XB, the above-mentioned various internal control signals and the like are selectively formed and supplied to each section of the dynamic RAM.

Although not shown in FIG. 1, the dynamic RAM has an internal voltage V based on a power supply voltage VCC and a ground potential VSS supplied through predetermined external terminals.
An internal voltage generation circuit for generating the PP and VDL and the intermediate voltage HV is provided. Among them, the internal voltage VPP is mainly used as a selection level of a word line constituting the memory arrays ARYL and ARYR, and the internal voltage VDL is mainly used as an operation power supply of the memory arrays ARYL and ARYR and its direct peripheral circuits. You. Although not particularly limited, the power supply voltage VCC is set to a positive potential, for example, 2.5 V (volt). The internal voltage VPP is, for example, 4.0 V, and the internal voltage VDL and the intermediate voltage HV are:
They are 1.5V and 0.75V, respectively.

FIG. 2 is a partial block diagram of one embodiment of the memory arrays ARY and ARYR of the memory mats MAT0 to MAT7 included in the dynamic RAM of FIG. 1 and the sense amplifier SA. FIG. 3 is a partial circuit diagram of an embodiment of the memory arrays ARYL and ARYR and the sense amplifier SA of FIG. 2, and FIG. 4 is a signal waveform diagram of the embodiment. I have. With reference to these figures, the specific configurations and operations of the memory arrays ARYL and ARYR and the sense amplifiers SA constituting the memory mats MAT0 to MAT7 of the dynamic RAM of this embodiment will be described.

In FIG. 2, a set of memory arrays AR
The block configuration will be described with reference to the YL and ARYR and the sense amplifier SA as an example.
A and the memory array ARYL disposed on the left side thereof will be used as an example to explain the specific configuration.
YR has a symmetric configuration with the memory array ARYL, and the memory mats MAT0 to MAT7 have memory arrays ARYL and ARYR and a sense amplifier S
A is provided. FIG. 4 illustrates a case where the word line WL0 of the memory array ARYL provided on the left side of the sense amplifier SA is alternatively selected, and is arranged at the intersection of the word line WL0 and the complementary bit line B0 *. The description of the operation proceeds with a focus on the memory cell that holds the data of logic "1". In the following circuit diagram, the MOSFET with an arrow at its channel (back gate) portion is a P-channel MOSFET,
It is shown differently from an N-channel MOSFET without an arrow.

In FIG. 2, the memory array ARYL is
M + 1 word lines WL0 to WLm arranged in parallel
And n + 1 sets of complementary bit lines BL0 * to BLn * arranged orthogonal to these word lines and parallel to each other. At the intersection of these word lines and complementary bit lines,
As exemplified in FIG. 3, (m + 1) × comprising an information storage capacitor Cs and an address selection MOSFET Qa.
(N + 1) dynamic memory cells are arranged in a lattice. M + arranged in the same column of the memory array ARYL
One electrode of the information storage capacitor Cs of one memory cell is alternately coupled to the non-inverted or inverted signal lines of the complementary bit lines BL0 * to BLn * through a corresponding address selection MOSFET Qa with a predetermined regularity, Address selection MOSF of n + 1 memory cells arranged on the same row
The gates of ETQa are connected to corresponding word lines WL0 to WLm.
Are commonly connected to each other. The intermediate voltage HV of 0.75 V is commonly supplied as a plate voltage to the other electrodes of the information storage capacitors Cs of all the memory cells constituting the memory array ARYL.

Similarly, the memory array ARYR includes (m + 1) word lines WR0-WRm arranged in parallel and (n + 1) sets of complementary bit lines BR0 * -BRn * arranged orthogonally and in parallel with each other. Including. At the intersection of these word lines and complementary bit lines, an (m + 1) × comprising an information storage capacitor Cs and an address selection MOSFET Qa
(N + 1) dynamic memory cells are arranged in a lattice. M + arranged in the same column of the memory array ARYR
One electrode of the information storage capacitor Cs of one memory cell is alternately coupled to the non-inverted or inverted signal lines of the complementary bit lines BR0 * to BRn * through a corresponding address selection MOSFET Qa with a predetermined regularity, Address selection MOSF of n + 1 memory cells arranged on the same row
The gates of ETQa are connected to corresponding word lines WR0-WRm.
Are commonly connected to each other. An intermediate voltage HV is commonly supplied as a plate voltage to the other electrodes of the information storage capacitors Cs of all the memory cells constituting the memory array ARYR.

In this embodiment, the memory mat MAT
0 to MAT7 memory arrays ARYL and ARYR are:
Further, complementary bit lines BL0 * to BLn * and BR
It includes n + 1 pairs of boost capacitors C1 and C2 and C3 and C4 provided corresponding to 0 * to BRn * and arranged substantially at the center of the bit line extension direction. These boost capacitances are so-called MOSFET capacitances obtained by partially modifying those formed as the address selection MOSFET Qa of the dynamic memory cell, and the size and layout pitch thereof are the same as those of the normal address selection MOSFET.
It is the same as ETQa. The gate electrodes of the boost capacitors C1 and C2 and C3 and C4 are connected to the complementary bit lines B
L0 * -BLn * or BR0 * -BRn * are respectively coupled to non-inverted and inverted signal lines, and their source / drain side electrodes are connected to a boost control signal BSTL or BSTR.
Are commonly connected to each other.

Next, the sense amplifiers SA are connected to the complementary bit lines BL0 * to BLn of the memory arrays ARYL and ARYR.
* And n provided corresponding to BR0 * to BRn *
+1 unit circuits, each of which comprises a P-channel MOSFET P2 and an N-channel M
OSFET N2 and P-channel MOSFET P3
And a pair of CMs comprising an N-channel MOSFET N3
Unit amplifier circuit UA in which OS inverters are cross-coupled
Is the basic component. Each unit circuit of the sense amplifier SA further includes a bit line precharge circuit in which three N-channel type precharge MOSFETs N6 to N8 are connected in series and parallel, a pair of N-channel type switch MOSFETs N9 and NA, and N It includes two sets of channel type shared MOSFETs N4 and N5 and NB and NC, respectively.

Precharge MOSFET constituting bit line precharge circuit of each unit circuit of sense amplifier SA
A precharge control signal PC is commonly supplied from the timing generation circuit TG to the gates of N6 to N8, and an intermediate voltage HV is supplied to the commonly coupled sources of the precharge MOSFETs N7 and N8. The sources of the P-channel MOSFETs P2 and P3 forming each unit amplifier circuit are commonly coupled to a common source line CSP (first common source line), and the sources of the N-channel MOSFETs N2 and N3 are connected to a common source line CSN (first common source line CSN). 2 common source lines). Common source line CSP
Is coupled to power supply voltage VCC via a P-channel type drive MOSFET P1 receiving a sense amplifier drive signal PA2B at its gate, and is an N-channel type drive MOSFET N receiving a sense amplifier drive signal PA3.
1 to internal voltage VDL. The common source line CSN has a sense amplifier drive signal PA1 at its gate.
, And is coupled to ground potential VSS via an N-channel type drive MOSFET N2.

Further, one of the switch MOSFETs N9 and NA of each unit circuit of the sense amplifier SA is connected to the corresponding complementary bit line BL of the memory arrays ARYL and ARYR.
0 * to BLn * and BR0 * to BRn *, respectively, and the other is commonly coupled to a non-inverted or inverted signal line of the complementary common data line CD *. In addition, a common-coupled gate of each switch MOSFET has Y
The corresponding bit line selection signal Y from the address decoder YD
S0 to YSn are supplied, respectively. The shared control signal SHL is commonly supplied from the timing generation circuit TG to the gates of the shared MOSFETs N4 and N5 of each unit circuit, and the shared control signal SHR is commonly supplied to the gates of the shared MOSFETs NB and NC.

Here, the precharge control signal PC is not particularly limited, but as shown in FIG. 4, is normally at a high level like the power supply voltage VCC when the dynamic RAM is in the non-selected state. Dynamic type R
When AM is selected, it is set to a low level such as the ground potential VSS at a predetermined timing. In addition, shared control signals SHL and SHR are usually supplied with power supply voltage VCC.
When the dynamic RAM is set to the selected state, one of them, that is, for example, the shared control signal SHR is set to a low level such as the ground potential VSS according to the internal address signal Xi of the most significant bit. You. In addition, the other who was left at a high level,
That is, for example, the shared control signal SHL is set to a high potential such as the internal voltage VPP at the time when the amplification operation of the sense amplifier SA is completed, and then together with the shared control signal SHR at the time when the dynamic RAM is set to the non-selection state. It is returned to a normal high level such as the power supply voltage VCC.

On the other hand, memory arrays ARYL and ARYR
Word lines WL0-WLm and WR0-WRm are
Normally, it is set to a non-selection level such as the ground potential VSS, and when the dynamic RAM is set to the selected state, it is selectively set to the selection level such as the internal voltage VPP according to the internal address signals X0 to Xi. Also, the boost control signal BSTL
And BSTR are set to the low level such as the ground potential VSS when the dynamic RAM is set to the non-selected state,
When the dynamic RAM is set to the selected state, the minute read signal of n + 1 memory cells coupled to the selected word line is supplied to the complementary bit lines BL0 * to BLn * or BR0.
At a relatively early point in time when the output to * to BRn * is completed, it is alternatively set to a high level like the power supply voltage VCC.

The sense amplifier drive signal PA1 is normally set at a low level such as the ground potential VSS, and when the dynamic RAM is selected, the boost capacitors C1 and C2 are set.
Alternatively, when the boost operation by C3 and C4 ends, the power supply voltage is set to a high level like the power supply voltage VCC. Further, the sense amplifier drive signal PA2B has the normal power supply voltage V
Dynamic RAM with high level like CC
Is set to the selected state, it is temporarily set to the low level such as the ground potential VSS in synchronization with the rise of the sense amplifier drive signal PA1 and for a predetermined period. Further, the sense amplifier drive signal PA3 is normally set to a low level such as the ground potential VSS. When the dynamic RAM is set to the selected state, the sense amplifier drive signal PA2B is returned to the high level and at the same time as the internal voltage VPP. It is set to a high potential high level.

When the dynamic RAM is deselected and the shared control signals SHL and SHR are at a high level such as the power supply voltage VCC, in the sense amplifier SA, the shared MOSFETs N4 and N5 and NB and NC of all unit circuits are They are simultaneously turned on. At this time, the precharge control signal PC is set to a high level such as the power supply voltage VCC, and in response to this, the precharge MOSFE configuring the bit line precharge circuit of each unit circuit.
TN6 to TN8 are simultaneously turned on.

As a result, the non-inverting and inverting input / output nodes of the complementary input / output nodes S0 * to Sn * of each unit circuit of the sense amplifier SA, and the complementary bit lines BL0 * to BLn * and BR0 * of the memory arrays ARYL and ARYR. ~ B
The non-inverted and inverted signal lines of Rn * are all intermediate voltage HV
Precharged. The drive MOSFETs N1 and N2 and P1 of the sense amplifier SA are all turned off in response to the low level of the sense amplifier drive signals PA1 and PA3 and the high level of the sense amplifier drive signal PA2B, and the common source lines CSP and CSN are
It is precharged to an intermediate voltage HV via a common source line precharge circuit (not shown). Memory array AR
The drain-source electrodes of the boost capacitors C1 and C2 and C3 and C4 of YL and ARYR receive the low level of the boost control signals BSTL and BSTR, and are charged to the ground potential VSS.

When the dynamic RAM is set to the selected state, the precharge control signal PC is first set to a low level such as the ground potential VSS at a predetermined timing, and the precharge control signal PC is precharged by the bit line precharge circuit of each unit circuit of the sense amplifier SA. The charging operation is stopped. Subsequently, for example, the unselected memory array AR not including the designated word line WL0
Shared control signal SHR corresponding to YR is at ground potential VS
S, the shared MOSFETs NB and NC of each unit circuit of the sense amplifier SA are simultaneously turned off, and the complementary input / output nodes S0 * to Sn * and the complementary bit lines BR0 * to BRn of the memory array ARYR are turned off. *
The connection to is broken.

In the memory array ARYL, when the decoding operation of the X address decoder XD is completed, the designated word line WL0 is alternatively set to a high potential selection level such as the internal voltage VPP, and the other word lines WL0 are selected. WL1 to W
All Lm are kept at a non-selected level such as the ground potential VSS. Thus, the selected word line WL0 is connected to the complementary bit lines B0 * to Bn * of the memory array ARYL, that is, the complementary input / output nodes S0 * to Sn * of the sense amplifier SA.
, A minute read signal corresponding to the data held in the (n + 1) memory cells is output. Therefore, for example, the complementary bit line B0 * to which the memory cell holding the data of logic "1" is coupled, that is, the sense amplifier SA
Of the non-inverted signal line B0
T, that is, the potential of the non-inverted input / output node S0T slightly increases, and becomes slightly higher than the potential of the corresponding inverted signal line B0B, that is, the inverted input / output node S0B.

When the word line selection operation is completed and, for example, the minute read signal of the (n + 1) memory cells coupled to the selected word line WL0 is output to the complementary bit lines BL0 * to BLn * of the memory array ARYL, sense is still performed. The memory array AR including the selected word line WL0 at a relatively early point in time when a sufficient amount of a small read signal cannot be obtained at the complementary input / output nodes S0 * to Sn * of the amplifier SA.
Without waiting for shared MOSFETs N4 and N5 corresponding to YL to be turned off, boost control signal BS
TL is alternatively set to a high level like the power supply voltage VCC. With a slight delay, the sense amplifier drive signal PA1 is set to a high level such as the power supply voltage VCC, and at the same time, the sense amplifier drive signal PA2B is temporarily set to a low level such as the ground potential VSS. Then, when a predetermined time has elapsed, the sense amplifier drive signal PA2B changes to the power supply voltage VC.
At the same time as returning to a high level such as C, the sense amplifier drive signal PA3 is set to a high level such as the internal voltage VPP.

Memory array A including selected word line WL0
In RYL, the drain-source electrodes of the boost capacitors C1 and C2 are boosted to the power supply voltage VCC in response to the high level of the boost control signal BSTL. In response to this, the non-inverted and inverted signals of the complementary bit lines BL0 * to BLn * are received. Line and complementary input / output nodes S0 * to of sense amplifier SA
The potential of the non-inverting and inverting input / output nodes of Sn * is boosted by an amount corresponding to the charge share between the capacitances of the boost capacitors C1 and C2 and the parasitic capacitance of each complementary bit line. At this time, the capacitance values of the boost capacitors C1 and C2 decrease because the drain / source side potential is higher than the gate potential in a reverse bias state, and the voltage between both electrodes increases accordingly, and the corresponding complementary bit increases. Lines BL0 * to BLn *
And the potential difference between the non-inverted and inverted input / output nodes of the sense amplifier SA and the complementary input / output nodes S0 * to Sn * of the sense amplifier SA.

However, in this embodiment, the conventional CAB
Unlike the S type, the boost capacitors C1 and C2 are provided in the memory array ARYL and the shared MOSFE
TN4 and N5 are kept on, and complementary bit lines BL0 * to BLn * and complementary input / output node S0 * are set.
Since a relatively large parasitic capacitance of .about.Sn * is coupled, an increase in the signal amount due to the boost operation of the boost capacitances C1 and C2 is small.

The sense amplifier SA receives the high level of the sense amplifier drive signal PA1 and receives the drive MOSFET N2
Is turned on, the low-voltage side operation power supply, that is, the ground potential VSS is supplied to the common source line CSN, and the drive MOSFET P1 is turned on in response to the low level of the sense amplifier drive signal PA2B, and the common source line CSN is turned on.
The power supply voltage VCC having an absolute value larger than that of the normal high-potential-side operation power supply is supplied to the SP. As a result, each unit amplifier circuit of the sense amplifier SA enters a so-called overdrive state, and starts an amplification operation in order to rapidly increase the potential difference between the non-inverting and inverting input / output nodes of the complementary input / output nodes S0 * to Sn *. Therefore, for example, the potential of the non-inverting input / output node S0T rapidly increases toward the power supply voltage VCC, and the potential of the inverting input / output node S0B decreases toward the ground potential VSS. However, the sense amplifier drive signal PA
2B, as described above, returns to the high level after the predetermined period, so that the potential rise of the non-inverting input / output node S0T is stopped halfway, and the drive MOSFET N1 is turned on in response to the high level of the sense amplifier drive signal PA3. After that, the internal voltage VDL is slightly reduced with the target potential.

As described above, in the case of this embodiment, the signal amount of the minute read signal on the complementary bit lines BL0 * to BLn * due to the boost operation of the boost capacitors C1 and C2 is small. However, in this embodiment, the boost operation by the boost capacity is performed by the memory array ARYL.
Immediately after the output of the minute read signal to the complementary bit lines BL0 * to BLn * of the sense amplifier SA, at a relatively early point in time when a sufficient signal amount cannot be obtained yet at the complementary input / output nodes S0 * to Sn * of the sense amplifier SA. Selected memory array ARYL
Without waiting for the shared MOSFETs N4 and N5 on the side to be turned off, the operation is started early, and the non-inverting bit line B0T and the non-inverted bit line B0T corresponding to the memory cell holding the data of logic "1" are overdriven. The high level of the inverting input / output node SOT is temporarily raised to exceed the internal voltage VDL. For this reason, the voltage between the drain and source of the MOSFETs N2 and N3 on the pull-down side of each unit amplifier circuit UA increases, so that the amplification operation is accelerated and the MOSFET P2 on the pull-up side is increased.
And the voltage between the drain and source of P3 also increases, and the amplification operation is accelerated. As a result, each unit amplifier circuit UA of the sense amplifier SA has the timing effect.
Is speeded up.

On the other hand, in this embodiment, the boost capacitance C
1 and C2 are provided in the memory array ARYL, and the address selection M which constitutes a dynamic memory cell.
Since the element structure is basically the same as that of the OSFET, the increase in the chip size of the dynamic RAM due to the provision of these boost capacitors is small. As a result, in this embodiment, the operation of the dynamic RAM using the boost sense method can be sped up while suppressing the cost increase, and the operating power supply of the dynamic RAM can be sufficiently lowered to increase the chip temperature. Hold down
The refresh characteristics of the dynamic RAM can be greatly improved.

The operation and effect obtained from the above embodiment are as follows. (1) In a dynamic RAM or the like that uses a boost sense method and a shared sense method, a boost capacitance for boost sense is provided not in a sense amplifier but in a memory array, and a complementary bit line by a boost capacitance is provided. By keeping the shared MOSFET on the selected memory array side of the sense amplifier ON while the potential boosting operation is performed, the potential boosting operation by the boost capacitance is output to the complementary bit line on the selected memory array by a minute read signal. Immediately after the operation is completed, at a relatively early time when a sufficient signal amount cannot be obtained at the complementary input / output node of the sense amplifier, and without delay until the shared MOSFET on the selected memory array is turned off, the operation is started early. The effect that it can be obtained is obtained.

(2) In the above item (1), the sense amplifier is set to the overdrive sense system, and the potential of the high-potential side common source line is set to the non-inverted or inverted input / output of each unit amplifier circuit for a predetermined period at the beginning of driving. By overdriving the potential higher than the final high level at the node, the high level of the non-inverted or inverted signal line of each complementary bit line is increased, and the drain-source voltage of the pull-up MOSFET is increased. The advantage is that the speed of the amplification operation can be increased. (3) According to the above items (1) and (2), the effect of increasing the speed of the read signal amplification operation by the sense amplifier can be obtained. (4) In the above items (1) to (3), the boost capacitance is configured based on a MOSFET having basically the same element structure as the address selection MOSFET of the memory array, so that the boost capacitance is used for boost sensing. The effect that the increase in the chip size due to the provision of the boost capacitance can be suppressed can be obtained.

(5) According to the above items (1) to (4), it is possible to obtain an effect that the operation of the dynamic RAM can be sped up while suppressing an increase in cost. (6) According to the above item (5), it is possible to obtain an effect that the operating power supply of the dynamic RAM or the like is sufficiently reduced in voltage, the chip temperature is prevented from rising, and the refresh characteristics of the dynamic RAM or the like can be greatly improved. Can be

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the dynamic RAM can have an arbitrary number of memory mats, and the memory arrays ARYL and ARYR constituting each memory mat are divided into a plurality of sub-arrays including their immediate peripheral portions. Can be. A dynamic RAM is a × 1 bit or × 1 bit.
An arbitrary bit line configuration such as 6 bits can be adopted, and adopting a shared sense system is not an essential condition. The Y address decoder YD may be provided commonly to all or a predetermined number of memory mats. The dynamic RAM can take an arbitrary block configuration, and the name and combination of the start control signal, the polarity and the absolute value of the power supply voltage and each internal voltage, and the like can take various embodiments.

In FIGS. 2 and 3, the memory array AR
YL and ARYR and the sense amplifier SA can include a predetermined number of redundant elements. Also, the memory array A
RYL and ARYR can adopt a so-called word line division system in which main word lines and sub word lines are hierarchically used. Boost capacitances C1 and C2 and C3 and C4 provided in memory arrays ARYL and ARYR
Can be constituted by a plurality of MOSFETs, respectively. Further, the arrangement position can be replaced with, for example, the near end side or the far end side of the sense amplifier of each memory array,
It may be provided at a plurality of positions in each memory array. The dynamic RAM can have the same boost capacitance provided in the sense amplifier together with the boost capacitance provided in the memory arrays ARYL and ARYR.
Drive MOSFETs P1 and N1 of sense amplifier SA
And N2 are a plurality of drive MOs each in a parallel form.
It may be composed of an SFET or a plurality of driving M
The OSFET may be turned on while shifting in time series. Furthermore, various embodiments can be adopted for the specific configuration of the memory arrays ARYL and ARYR, the sense amplifier SA, the conductivity type of the MOSFET, and the like. In FIG. 4, the absolute potential and time relationship of each signal does not affect the gist of the present invention.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM, which is the application field of the background, has been described.
The present invention is not limited to this, and can be applied to, for example, various memory integrated circuit devices having a dynamic RAM as a basic configuration, and logic integrated circuit devices including such a memory integrated circuit device. INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a semiconductor memory device employing a boost sense method and a device or system including the same.

[0055]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like that employs a boost sense system and a shared sense system, a boost capacitance for boost sense is provided in a memory array without being provided in a sense amplifier, and these boost capacitances are provided by the dynamic type of the memory array. It is constructed based on MOSFETs having basically the same element structure as the address selection MOSFETs constituting the memory cell. In addition, while the potential boosting operation of the complementary bit line by the boost capacitance is performed, the shared MOSFET on the selected memory array side of the sense amplifier is kept on, and the sense amplifier is set to the overdrive sense method,
The potential of the high-potential-side common source line is overdriven to a potential higher than the final high level at the non-inverted or inverted input / output node of each unit amplifier circuit for a predetermined period at the beginning of driving. This makes it possible to start the potential boosting operation of the complementary bit lines by these boost capacitors at an early stage while suppressing an increase in the chip size due to the provision of the boost capacitors for the boost sense, and to overdrive each complementary bit line. By increasing the high level of the non-inverting or inverting signal line and increasing the drain-source voltage of the pull-up MOSFET, the speed of the amplification operation can be increased. As a result, the dynamic RA
The operation speed can be increased while suppressing the increase in the cost of M, and the operating power supply such as a dynamic RAM is sufficiently lowered to suppress the rise in the chip temperature.
Refresh characteristics as a dynamic RAM or the like can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a partial block diagram showing one embodiment of a memory array and a sense amplifier included in the dynamic RAM of FIG. 1;

FIG. 3 is a circuit diagram showing one embodiment of a memory array and a sense amplifier of FIG. 2;

FIG. 4 is a signal waveform diagram showing one embodiment of the memory array and the sense amplifier of FIG. 2;

FIG. 5 is a partial block diagram showing an example of a memory array and a sense amplifier included in a dynamic RAM examined by the present inventors prior to the present invention.

FIG. 6 is a signal waveform diagram illustrating an example of a memory array and a sense amplifier in FIG. 5;

[Explanation of symbols]

MAT0 to MAT7: Memory mat, ARYL, AR
YR memory array, XDL, XDR X address decoder, XB X address buffer, SA sense amplifier, YD Y address decoder, YB Y
Address buffer, WA: Write amplifier, MA: Main amplifier, IB: Data input buffer, OB: Data output buffer, TG: Timing generation circuit. D0
~ D7 ... I / O data or its I / O terminal, RASB
... Row address strobe signal or its input terminal, C
ASB: a column address strobe signal or its input terminal; WEB: a write enable signal or its input terminal; A0 to Ai: an address signal or its input terminal. W
L0 to WLm, WR0 to WRm ... word line, BL0 *
To BLn *, BR0 * to BRn *... Complementary bit line, U
A: Unit amplification circuit, C1 to C4: Boost capacity, C
SP, CSN ... common source line, SHL, SHR ...
Shared control signals, PA1, PA2B, PA3, PA,
PAB: Sense amplifier drive signal, BSTL, BST
R, BST ... boost control signal. Qa: Address selection MOSFET, Cs: Information storage capacitor, S0 *
... Sn * ... sense amplifier complementary input / output node, CD * ...
... Complementary common data line, PC ... Precharge control signal,
YS0 to YSn ... bit line selection signal, P1 to P4 ... P
Channel MOSFETs, N1 to NE ... N-channel MOSFETs. VCC: power supply voltage, VSS: ground potential, VPP, VDL: internal voltage, HV: intermediate voltage.

Claims (5)

[Claims] 1. A memory array comprising: a word line and a complementary bit line; and a dynamic memory cell lattice-arranged at an intersection of the word line and the complementary bit line and each including an information storage capacitor and an address selection MOSFET; A small read signal of a memory cell provided between the non-inverted and inverted signal line of the complementary bit line and the boost control signal line and coupled to the selected word line is output to the corresponding complementary bit line. And a sense amplifier including a unit amplifier circuit provided corresponding to the complementary bit line, and a boost capacitor for boosting the potential of the non-inverting and inverting signal lines of the corresponding complementary bit line at a time point. Storage device. 2. The device according to claim 1, wherein the boost capacitance is constituted by a MOSFET having an element structure basically the same as an address selection MOSFET constituting a dynamic memory cell of the memory array. Semiconductor storage device. 3. The non-inverting and inverting signal line of the complementary bit line corresponding to the boost capacitor at an earlier point in time as compared with the case where the boost capacitor is provided in the sense amplifier. A semiconductor memory device which is controlled to increase a potential. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device employs a shared sense system, and the memory arrays are provided on both sides of the sense amplifier so as to form a pair. Wherein the sense amplifier includes two sets of shared MOSFETs respectively provided between a complementary input / output node of the unit amplifier circuit and a corresponding complementary bit line of the memory array forming the pair. The boost capacitors are provided corresponding to the respective complementary bit lines of the paired memory arrays, and the corresponding shared MOSFET is turned on while the boosting of the potential of the complementary bit lines by the boost capacitors is performed. A semiconductor memory device characterized by being left as it is. 5. A high-potential-side operation power supply and a low-potential-side operation power supply are selectively supplied to a unit amplifier circuit constituting the sense amplifier via first and second common source lines. The potential of the high-potential-side operation power supply should be higher than the final high level after amplification at the non-inverting or inverting input / output node of the unit amplifier circuit during an initial predetermined period when the sense amplifier is driven. A semiconductor memory device which is temporarily overdriven.