JPH08314566A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Purpose] The layout designer can easily change the correlation between the setup time and delay time of the functional module.
To obtain a semiconductor integrated circuit provided with a functional module capable of improving the operating frequency in a relatively short period of time. [Configuration] The functional module 1 includes a flip-flop 2,
Signals are exchanged in the order of the address buffer 5, the decoder 6, the flip-flop 3, the sense amplifier 7, the flip-flop 4 and the output buffer 8. When the flip-flops 2 to 4 receive the timing signal ST as the control signals Sa to Sc, they operate in response to the timing signal ST, and when they receive a fixed voltage of "H" or "L", the input / output thereof is passed through. It Therefore, as the flip-flop that receives the timing signal, the flip-flop 2
One of ~ 4 can be selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a synchronous functional module that outputs a predetermined output signal in response to a timing signal.

[0002]

2. Description of the Related Art As an on-chip system advances, in ASIC (Application Specific IC) design,
The mounting of functional modules having a certain function such as RAM and ROM is increasing more and more. Furthermore, this functional module is a major factor in determining the frequency of the chip. In the case of such an ASIC design, the timing characteristics of the functional module are determined by arranging the peripheral circuits of the functional module.
It has a great influence on the layout designer (chip designer) who designs by wiring.

The influence of the above-mentioned functional module on the layout designer will be described below with reference to the drawings of a conventional semiconductor integrated circuit. FIG. 10 is an explanatory diagram that schematically shows the configuration of a synchronous RAM that is one of the functional modules.

As shown in FIG. 10, the functional module 20
Is composed of a flip-flop (F / F) 2, an address buffer 5, a decoder 6, a sense amplifier 7 and an output buffer 8. The flip-flop 2 has a timing signal S
It receives T, operates in response to the timing signal ST, and takes in the input signal S10 (address signal) and transfers it to the address buffer 5.

The address buffer 5 buffers the signal obtained from the flip-flop 2 and outputs it to the decoder 6. The decoder 6 decodes the output of the address buffer 5 and performs a decoding process such as selectively activating a word line (not shown), and the selected memory cell contents are bit lines or bit line pairs (both shown). Read).

The sense amplifier 7 senses and amplifies the potential appearing on the bit line or the potential difference appearing on the bit line pair, and supplies the output to the output buffer 8. The output buffer 8 outputs the output signal S20 to the outside of the functional module 20 based on the output of the sense amplifier 7.

FIG. 11 shows the timing signal S shown in FIG.
FIG. 6 is a timing diagram of T, an input signal S10, and an output signal S20. The flip-flop 2 shown in FIG. 10 is triggered by the rising edge of the timing signal ST.

As shown in FIG. 11, the timing signal ST
The setup time TS is the difference between the rising timing t10 and the change timing t01 of the input signal S10. That is, the setup time TS means a time difference from the time when the value of the input signal S10 is fixed before the rising time of the timing signal ST. The time difference TD from the time t10 when the timing signal ST rises to the time t12 when the output signal S20 is determined is the functional module 2
The delay time is 0.

As described above, since the internal structure of the synchronous functional module 20 is fixed, the setup time TS and the delay time TD are naturally fixed.

FIG. 12 is an explanatory diagram showing a part of a signal processing circuit configured by combining the functional module having the configuration shown in FIG. 10 and other circuit blocks.

As shown in the figure, the flip-flop 11
Receives the timing signal ST, operates in response to the timing signal ST, and outputs the signal S11 to the circuit block 12. The circuit block 12 receives the signal S12 based on the signal S11.
Is output to the functional module 20.

In the functional module 20, the flip-flop 2 takes in the signal S12 in response to the timing signal ST, performs signal processing on the address buffer 5, the decoder 6, the sense amplifier 7 and the output buffer 8, and then outputs the output signal S20. Output to the circuit block 13.

The circuit block 13 performs signal processing based on the output signal S20 and outputs it as a signal S13. Flip-flop 14 receives timing signal ST and receives signal S13 in response to timing signal ST.

FIG. 13 is a timing chart showing an operation of a part of the signal processing circuit shown in FIG. As shown in the figure, from the rising edge (falling edge) of the timing signal ST to the rising edge (falling edge)
The period is up to 1 cycle. As shown in FIG.
When the timing signal ST rises to "H" at 00, the signal S11 is output from the flip-flop 11 at time t01 after the delay time d1 has elapsed from time t00. And time t
Circuit block 1 at time t02 after delay time d2 from 01
2 outputs the signal S12. Then, the timing signal ST rises to "H" at time t10 after the setup time TS has elapsed from time t02.

When the timing signal ST rises to "H" at time t10, the functional module 20 outputs the output signal S20 at time t11 after the delay time TD elapses from time t10. Then, the signal S13 is output from the circuit block 13 at time t12 after the delay time d4 has elapsed from time t11.
Then, the timing signal ST rises to "H" at time t20 after the setup time s2 of the flip-flop 14 has elapsed from time t12.

Consider the time constraints of the periods T1 and T2 when the period from time t00 to time t10 is the period T1 and the period from time t10 to time t20 is the period T2.

Regarding the period T1, as described above, the output signal S11 of the flip-flop 11 is determined only after the delay time d1 elapses after the timing signal ST rises at time t00. Then, the output signal S12 of the circuit block 12 which receives the signal 11 is determined only after the circuit block delay time d2 has elapsed from the time t01. And
The output signal S12 needs to be determined before the setup time TS of the flip-flop 2 of the functional module 20 with respect to the time t10 when the timing signal ST next rises.

That is, the minimum value of the period T1 is the following (I)
Determined by the formula.

T1 = d1 + d2 + TS (I) On the other hand, regarding the period T2, as described above, the output signal S20 of the functional module 20 has the delay time TD of the functional module 20 after the timing signal ST rises at the time t10. It is first decided at time t11. here,
The delay time of the flip-flop 2 of the functional module 20 is also included in the delay time TD. The output signal S13 of the circuit block 13 that receives the output signal S20 is determined only after the delay time d4 of the circuit block 13 has elapsed from the time t11. The output signal S13 is then the timing signal S
At time t20 when T rises, the flip-flop 14
The setup time s2 must be determined before.

That is, the minimum value of the period T2 is (II)
To decide.

T2 = TD + d4 + s2 (II) At this time, the actual cycle of the timing signal ST is the cycle T
1 or the cycle T2, whichever is larger. At this time, the cycle T1 or T2 including the functional module 20 having a relatively large circuit configuration often becomes the law of the operating frequency of the signal processing circuit. This causes deterioration of chip performance.

In the case of T1> T2 in which the period T1 is rate-determining 1. The operating frequency is determined to satisfy the period T1 without shortening the period T1 at all.

2. The circuit of the circuit block 12 is revised to shorten the cycle T1 by reducing the delay time d2 of the circuit block 12.

3. A part of the circuit of the circuit block 12 is moved to a circuit in the preceding stage of the flip-flop 11 to shorten the cycle T1 by reducing the circuit block delay time d2.

3. When T1 <T2 where the period T2 is rate-determining. The operating frequency is determined to satisfy the period T2 without shortening the period T2 at all.

[5] The circuit of the circuit block 13 is revised to shorten the cycle T2 by reducing the delay time d4 of the circuit block 13.

6. A part of the circuit of the circuit block 13 is moved to a circuit subsequent to the flip-flop 14 to reduce the cycle T2 by reducing the circuit block delay time d4.

Other than that, the delay time d1 of the flip-flop 2, the setup time s2 of the flip-flop 14, the setup time TS of the functional module 20 and the delay time TD can be reduced. However, since the flip-flops 11 and 14 are small-scale cells, the delay time d1 and the setup time s2 have small values themselves, and there is no effect even if they are revised. On the other hand, since the functional module 20 is often a large-scale cell and the setup time TS, especially the delay time TD, has a large value,
From the layout designer's point of view, this is where the freedom is most desired.

However, since the functional module 20 is treated as one cell, it is often difficult to revise the inside of the functional module 20, and the revision by the layout designer is unrealistic. Even for the designer of the functional module itself, it is difficult to revise the delay time TD.

As described above, a layout designer who develops a one-chip IC by utilizing a predetermined cell, who does circuit development without degrading circuit performance, cannot revise the functional module itself. Generally, the above-mentioned measures 2. , 3. , 5. , 6. This is done by trial and error a number of times, which causes a problem of increasing the layout design period.

[0031]

As described above, since the conventional layout designer cannot revise the functional module which is the rule of the cycle, it is possible to use a relatively simple circuit configuration connected before and after the functional block. Only the peripheral circuits were revised so that the operating frequency of the circuits would not be reduced.
Therefore, there is a problem that the layout design period increases.

The present invention has been made to solve the above problems, and a layout designer can easily change the correlation between the setup time and the delay time of a functional module, and the operating frequency can be improved in a relatively short period of time. It is an object of the present invention to obtain a semiconductor integrated circuit including a functional module capable of achieving the above.

[0033]

A semiconductor integrated circuit according to a first aspect of the present invention comprises a plurality of signal processing units for sequentially transmitting signals, receives an input signal, and responds to a predetermined timing signal. It has a synchronous functional module that operates and transmits and receives signals between the plurality of signal processing units to output an output signal based on the input signal. And at least one flip-flop that performs signal processing in response to a signal received at a control input, the plurality of signal processings of the flip-flops receiving the predetermined timing signal at the control input among the at least one flip-flop. There is provided means for variably setting the signal transmission sequence in the section.

According to a second aspect of the semiconductor integrated circuit of the present invention, the at least one flip-flop includes a plurality of flip-flops provided without being adjacent to each other, and the plurality of flip-flops are provided to the control input. It may be configured to perform signal processing that always allows input / output to pass when a predetermined fixed voltage is received.

According to a third aspect of the semiconductor integrated circuit of the present invention, of the plurality of flip-flops, the predetermined timing signal is given to the control input of one flip-flop, and all other flip-flops are provided. It may be configured to apply the predetermined fixed voltage to the control input.

According to another aspect of the semiconductor integrated circuit of the present invention, the variably setting means receives a selection signal, and based on the selection signal, the control of one flip-flop among the plurality of flip-flops. A selection circuit may be provided which applies the predetermined timing signal to the input and applies the predetermined fixed voltage to the control inputs of all other flip-flops.

The semiconductor integrated circuit according to claim 5 is
The at least one flip-flop includes a plurality of flip-flops that are provided so as not to be adjacent to each other, and the plurality of flip-flops are selectively removable, and short-circuit the input and output of the removed flip-flops. It is possible.

According to a sixth aspect of the semiconductor integrated circuit, of the plurality of flip-flops, the predetermined timing signal is given to the control input of one flip-flop, and all the other flip-flops are provided. It may be removed and the input and output may be short-circuited.

[0039]

The semiconductor integrated circuit according to the first aspect of the present invention is provided with the means for variably setting the signal transmission sequence in the plurality of signal processing units of the flip-flop which receives the predetermined timing signal at the control input. The correlation between the setup time and the delay time can be variably set.

Further, since the plurality of flip-flops in the semiconductor integrated circuit according to the second aspect perform signal processing for always allowing input / output to pass when a predetermined fixed voltage is applied to the control input, the control inputs of unnecessary flip-flops are provided. By applying a predetermined fixed voltage, the unnecessary flip-flop can be operated as a mere wiring for signal propagation.

According to a third aspect of the semiconductor integrated circuit, of the plurality of flip-flops, a predetermined timing signal is given to the control input of one flip-flop and the control inputs of all the other flip-flops. The function module is configured to apply a predetermined fixed voltage, and the correlation between the setup time and the delay time of the functional module is selected according to the position on the signal path between the plurality of signal processing units of the flip-flop receiving the predetermined timing signal. Can be set as desired.

The means for variably setting the semiconductor integrated circuit according to claim 4 applies a predetermined timing signal to the control input of one flip-flop among the plurality of flip-flops based on the selection signal, and all the others. Since a selection circuit that applies a predetermined fixed voltage to the control input of the flip-flop of is provided, the position on the signal path between the plurality of signal processing units of the flip-flop that receives the predetermined timing signal can be determined by the selection signal. .

Further, since it is possible to selectively remove a plurality of flip-flops in the semiconductor integrated circuit according to the present invention and short-circuit the input and output of the removed flip-flops, unnecessary flip-flops are deleted. However, by short-circuiting the input and output, unnecessary flip-flops can be physically deleted without impairing the operation of the functional block.

According to the sixth aspect of the semiconductor integrated circuit of the present invention, of the plurality of flip-flops, a predetermined timing signal is given to the control input of one flip-flop, all other flip-flops are removed, and the flip-flop is turned on. Short-circuiting the outputs to selectively set the correlation between the setup time and the delay time of the functional module depending on the position on the signal path between the signal processing units of the flip-flop that receives a predetermined timing signal. You can

[0045]

【Example】

<First Embodiment> FIG. 1 is an explanatory diagram schematically showing the internal structure of a functional module 1 of a semiconductor integrated circuit according to a first embodiment of the present invention.

As shown in FIG. 1, the functional module 1 is
It is composed of flip-flops (F / F) 2 to 4, an address buffer 5, a decoder 6, a sense amplifier 7 and an output buffer 8. A signal path between the input and output of the functional module 1 is established in the order of the flip-flop 2, the address buffer 5, the decoder 6, the flip-flop 3, the sense amplifier 7, the flip-flop 4, and the output buffer 8.

Flip-flop 2 receives control signal Sa at the control input, operates in response to control signal Sa, and takes in the input signal and transfers it to address buffer 5.

The address buffer 5 buffers the signal obtained from the flip-flop 2 and outputs it to the decoder 6. The decoder 6 decodes the output of the address buffer 5 and performs a decoding process such as selectively activating a word line (not shown), and the selected memory cell contents are bit lines or bit line pairs (both shown). Read).

The flip-flop 3 receives the control signal Sb at its control input, operates in response to the control signal Sb, and fetches the content of the memory cell appearing on the bit line or the bit line pair and transmits it to the sense amplifier 7.

The sense amplifier 7 senses and amplifies the potential appearing on the bit line or the potential difference appearing on the bit line pair obtained through the flip-flop 3 and supplies the output to the flip-flop 4.

Flip-flop 4 receives control signal Sc at its control input, operates in response to control signal Sc, and takes in the output of sense amplifier 7 and transfers it to output buffer 8. The output buffer 8 outputs an output signal to the outside of the functional module 1 based on the output of the sense amplifier 7 obtained via the flip-flop 4.

When the flip-flops 2 to 4 receive the timing signal ST as the control signals Sa to Sc, they operate in response to the timing signal ST, and when they receive a fixed voltage of "H" or "L", they are input / output. Will be through.

FIG. 6 is a circuit diagram showing an example of the internal structure of the flip-flop 2 (3, 4). As shown in the figure,
The NOR gate 31 has a data input D and a control signal Sa (S
b, Sc).

The NOR gate 32 receives the output of the NOR gate 31 and the control signal Sa, and the NOR gate 33 outputs NO.
Upon receiving the output of the R gate 31 and the output of the NOR gate 34, the NOR gate 34 outputs the output of the NOR gate 32 and the NO
The output of the R gate 33 is received.

The output of the NOR gate 33 becomes the data output Q, and the output of the NOR gate 34 becomes the inverted data output bar Q.

The flip-flop 2 having the above structure is
The control signal Sa is received as a clock, the rising edge of the control signal Sa is used as a trigger to take in the data input D, and the taken-in data is output as the data output Q and the inverted data output bar Q to the circuit in the next stage.

At this time, if a fixed voltage of "L" (ground level GND) is applied to the control signal Sa, the data input D directly passes through and appears as the data output Q. That is, the flip-flop 2 functions simply as a wiring for signal propagation.

A description will be given of a method in which the layout designer selects the setup time and delay time of the functional module 1 at the time of layout when using the semiconductor integrated circuit of the first embodiment having the functional module 1 having such a configuration.

Since the functional module 1 of the first embodiment is a functional module in which flip-flops are inserted at three internal locations, there are three choices.

In the first selection, as shown in FIG. 2, the timing signal ST is given as the control signal Sa of the flip-flop 2 of the functional module 1, and "L" (L) (as the control inputs Sb and Sc of the flip-flops 3 and 4). GND).

In the second selection, as shown in FIG. 3, the timing signal ST is given as the control signal Sb of the flip-flop 3 of the functional module 1 and "L" (L) (as the control inputs Sa and Sc of the flip-flops 2 and 4). GND).

In the third selection, as shown in FIG. 4, the timing signal ST is supplied as the control signal Sc of the flip-flop 4 of the functional module 1 and "L" (L) (as the control inputs Sa and Sb of the flip-flops 2 and 3). GND).

Here, the setup times of the flip-flops 2 to 4 are s02, s03 and s04, and the delay times are d02, d03 and d04, and the delay of the address buffer 5, the decoder 6, the sense amplifier 7 and the output buffer 8 is delayed. If the time is d05, d06, d07 and d08,
The setup times TS1 to TS3 and the delay times TD1 to TD3 of the functional module 1 according to the third selection are determined as follows.

[0064] - first selection TS1 = s02 TD1 = d02 + d05 + d06 + d03 + d07 + d04 + d08 · second selection TS2 = d02 + d05 + d06 + s03 TD2 = d03 + d07 + d04 + d08 · third selection TS3 = d02 + d05 + d06 + d03 + d07 + s04 TD3 = d04 + d08 where the setup time of the flip-flops 2-4 and the delay time Are equal to each other (s02 = s03 = s04, d02 =
When d03 = d04), the following relationships (III) to (V) are established.

TS1 <TS2 <TS3 ... (III) TD1>TD2> TD3 ... (IV) TS1 + TD1 = TS2 + TD2 = TS3 + TD3. By doing so, even a layout designer who cannot revise a functional module can give a timing signal ST to only one of the flip-flops 2 to 4 and give a ground level GND to the control inputs of all the other flip-flops. Since the signal transmission sequence in each signal processing unit in the functional block of the flip-flop that receives the timing signal ST at its control input can be variably set, the correlation between the setup time TS of the functional module 1 and the delay time TD can be easily performed. Can be changed.

Therefore, when the functional module 1 is inserted in place of the functional module 20 having the circuit configuration shown in FIG. 12, in the timing chart shown in FIG.
Delay time (d1 +
If d2) is considerably larger than the delay time (d4 + s2) due to the circuit after the functional module 1, the first selection is performed, and the delay time (d4 + s)
If 2) is considerably large, the third selection is performed, and if the difference between the delay time (d1 + d2) and the delay time (d4 + s2) is not so large, the second selection is performed to minimize the time difference between the cycle T1 and the cycle T2. Can be limited.

As a result, of the periods T1 and T2,
The operating period of the circuit including the semiconductor integrated circuit of the first embodiment can be improved by minimizing the period of the cycle having a large value.

In the first embodiment, the functional module is not limited as long as it is a synchronous functional module such as a synchronous RAM. In the first embodiment, the case where the flip-flops are inserted into the functional module 1 at three positions has been described, but it can be easily assumed that the flip-flops may be inserted at two or more positions.

<Second Embodiment> FIG. 5 is an explanatory diagram schematically showing the internal structure of a functional module 15 of a semiconductor integrated circuit according to a second embodiment of the present invention and its periphery.

As shown in FIG. 5, the functional module 15
Is composed of flip-flops (F / F) 2 ', 3', an address buffer 5, a decoder 6, a sense amplifier 7 and an output buffer 8. The flip-flop 2'receives the control signal S18 from the selection circuit 16 at the control input, operates in response to the control signal 18, and fetches the input signal and transfers it to the address buffer 5.

The address buffer 5 buffers the signal obtained from the flip-flop 2'and outputs it to the decoder 6. The decoder 6 decodes the output of the address buffer 5 and performs a decoding process such as selectively activating a word line (not shown), and the selected memory cell contents are bit lines or bit line pairs (both shown). Read).

The flip-flop 3'receives the control signal S19 from the selection circuit 16 at the control input and operates in response to the control signal 19 to take in the memory cell contents appearing on the bit line or the bit line pair to the sense amplifier 7. introduce. The internal structure of the flip-flop 2'3 'is similar to that of the flip-flop 2 shown in FIG.

The sense amplifier 7 senses and amplifies the potential appearing on the bit line or the potential difference appearing on the bit line pair obtained through the flip-flop 3 ′, and supplies the output to the output buffer 8. The output buffer 8 outputs an output signal to the outside of the functional module 15 based on the output of the sense amplifier 7.

The flip-flops 2'and 3'operate in response to the timing signal ST when receiving the timing signal ST at their control inputs, and operate at a fixed voltage of "H" or "L"("L" in the example of FIG. 5). ), The input and output are passed through.

The selection circuit 16 includes an inverter 17 and an AND circuit.
It is composed of a gate 18 and an AND gate 19, and AND
The gate 18 receives the signals obtained by the timing signal ST and the selection signal SS via the inverter 17, and outputs the output as a control signal S18 to the control input of the flip-flop 2 '. The AND gate 19 receives the selection signal SS and the timing signal ST, and outputs the output as the control signal S19 to the control input of the flip-flop 3 '.

Flip-flop 11, circuit block 1
2, the circuit block 13 and the flip-flop 14 are the same as those in the conventional example shown in FIG. These constituent parts 11 to 14 may or may not be integrated into one chip together with the functional module 15 and the selection circuit 16. The functional module 15 and the selection circuit 16 are essential components of the semiconductor integrated circuit of the second embodiment.

A description will be given of a method in which the layout designer selects the setup time and delay time of the functional module 15 at the time of layout when using the semiconductor integrated circuit of the second embodiment having the functional module 15 having such a configuration.

Since the functional module 15 of the second embodiment is a functional module in which flip-flops are inserted at two internal locations, there are two choices.

In the first selection, the "L" selection signal SS is supplied, and the timing signal ST is supplied as the control signal S18.
The control signal S19 is fixed at "L".

In the second selection, the "H" selection signal SS is supplied, and the timing signal ST is supplied as the control signal S19.
That is, the control signal S18 is fixed at "L".

Here, the setup times of the flip-flops 2'and 3'are s02 'and s03', and the delay time is d.
02 ', d03', setup times TS1 'and TS of the functional module 15 according to the first and second selections.
2'and the delay times TD1 'and TD2' are determined as follows.

First selection TS1 '= s02' TD1 '= d02' + d05 + d06 + d03 '+ d07 + d08 Second selection TS2' = d02 '+ d05 + d06 + s03' TD2 '= d03' + d07 + d08 Setup of flip-flops 2'and 3'here The time is equal to the delay time (s02 '= s03', d
If 02 '= d03'), the following relationships (VI) to (VIII) are established.

TS1 '<TS2' ... (VI) TD1 '>TD2' ... (VII) TS1 '+ TD1' = TS2 '+ TD2' ... (VIII) The functional module 15 of the second embodiment having such a configuration is laid out. By providing it to the designer, even the layout designer who cannot revise the function module can select the selection signal SS.
“H” / “L” of the timing signal S to one of the flip-flops 2 ′ and 3 ′.
By giving T and giving the ground level GND to the control input of the other flip-flop, the signal transmission sequence in the signal processing unit in the functional block of the flip-flop receiving the timing signal ST at the control input is variably set to function. The correlation between the setup time TS of the module 15 and the delay time TD can be easily changed.

Therefore, when the first delay time by the circuit in the preceding stage of the functional module 15 is larger than the second delay time by the circuit after the functional module 15, the first selection is performed and the first delay time 2, the delay time is large,
Alternatively, if the difference between the first delay time and the second delay time is not so large, the second selection is performed, so that the first delay time and the cycle T1 determined by the timing signal ST of the functional module 15 and the second delay time are determined. The time difference between the delay time and the cycle T2 determined by the delay time TD of the functional module 15 can be minimized.

As a result, of the periods T1 and T2,
The operating period of the circuit including the semiconductor integrated circuit of the second embodiment can be improved by minimizing the period of the cycle having a large value.

In addition, in the semiconductor integrated circuit of the second embodiment, the setup time TS and the delay time TD of the functional module 15 can be changed appropriately by giving the selection signal SS. This is effective even when the magnitude relationship with T2 cannot be clarified without performing actual device evaluation, and when the periodic law changes depending on the process or operating conditions.

In the second embodiment, the functional module is not limited as long as it is a synchronous functional module such as a synchronous RAM. Further, in the second embodiment, the case where the flip-flops are inserted into the functional module 15 at two places has been described, but it is only necessary to insert two or more places such as three places as in the first embodiment. You can easily assume. In addition, the circuit configuration of the selection circuit 16 is not limited to this, and it goes without saying that a plurality of selection signals SS may be set.

<Third Embodiment> In the functional module 1 of the first embodiment, the more flip-flops are inserted, the more unnecessary flip-flops that are not actually used as flip-flops increase, and the setup time of the functional module 1 increases. , The delay time and the circuit area increase.

Therefore, a third embodiment of the semiconductor integrated circuit including the functional module 21 configured to selectively remove the flip-flops inserted in the functional blocks and short-circuit the input and output of the removed flip-flops is performed. Suggest as an example. It should be noted that, except for the above features, all of the first features shown in FIG.
It is similar to the functional module 1 of the embodiment.

Functional module 21 having the above characteristics
When using the semiconductor integrated circuit of the third embodiment including
When the layout designer lays out the function module 21
A method of selecting the setup time and delay time of is explained.

Since the functional module 21 of the third embodiment is a functional module in which flip-flops are inserted at three internal locations as in the first embodiment, there are three choices.

In the first selection, as shown in FIG. 7, the timing signal ST is given as the control signal Sa of the flip-flop 2 of the functional module 21, the flip-flop 3 is removed, and the input and output of the flip-flop 3 are short-circuited. The decoder 6 and the sense amplifier 7 are electrically connected by wiring with the line L2, the flip-flop 4 is removed, and the short-circuit line L3 is provided between the input and output of the flip-flop 4 to sense the amplifier 7 and the output buffer 8. Make an electrical connection between the two.

In the second selection, as shown in FIG. 8, the timing signal ST is given as the control signal Sb of the flip-flop 3 of the functional module 21, the flip-flop 2 is removed, and the input and output of the flip-flop 2 are short-circuited. The output of the circuit in the previous stage of the functional module 21 is electrically connected to the address buffer 5 by wiring with the line L1, the flip-flop 4 is removed, and the short-circuit line L3 is provided between the input and output of the flip-flop 4. Sense amplifier 7, output buffer 8
Make an electrical connection between the two.

In the third selection, as shown in FIG. 9, the timing signal ST is given as the control signal Sc of the flip-flop 4 of the functional module 21, the flip-flop 2 is removed, and the input and output of the flip-flop 2 are short-circuited. The output of the circuit in the preceding stage of the functional module 21 and the address buffer 5 are electrically connected by wiring with the line L1, the flip-flop 3 is removed, and the input and output of the flip-flop 3 are wired with the short-circuit line L2. The decoder 6 and the sense amplifier 7 are electrically connected.

By providing the layout designer with the function module 21 of the third embodiment having such a configuration,
Even layout designers who can't revise function modules
The timing signal ST is given to only one of the flip-flops 2 to 4, all the other flip-flops are removed, and the front and rear stages of the removed flip-flops are short-circuited, as in the first embodiment. The correlation between the setup time TS of the functional module 1 and the delay time TD can be easily changed.

As a result, of the period T1 in which the timing signal ST of the functional module 21 is involved and the period T2 in which the delay time TD is involved, the period of the one having a larger value is minimized, and the period of the second embodiment is reduced. The operating frequency of a circuit including a semiconductor integrated circuit can be improved.

In addition, since unnecessary flip-flops can be physically deleted, unnecessary delay time generated when a signal propagates between unnecessary flip-flops can be omitted, thereby further improving the circuit operating frequency. Can be made. It is possible to minimize the increase in the circuit scale due to the insertion of the flip-flop in the functional module 21.

Further, since unnecessary flip-flops are removed, the flip-flops 2 to 4 are arranged so that their input and output are passed through when a fixed voltage of "H" or "L" is received.
Need not be configured.

[0099]

The semiconductor integrated circuit according to the first aspect of the present invention is provided with means for variably setting the signal transmission sequence in the plurality of signal processing units of the flip-flop which receives the predetermined timing signal at the control input. The correlation between the module setup time and the delay time can be variably set.

As a result, when there is an input-side circuit connected to the input side of the functional module and an output-side circuit connected to the output side of the functional module, there is provided a first signal transfer between the input-side circuit and the functional module. By changing the correlation between the setup time of the functional module and the delay time so that the time constraint of 1) and the second time constraint relating to signal transmission / reception between the output side circuit and the functional module are almost the same, It is possible to improve the operating frequency by minimizing the rate-determining time of the circuit including the circuit, the functional block, and the output side circuit.

Further, since the plurality of flip-flops in the semiconductor integrated circuit according to the second aspect perform signal processing for always allowing input / output to pass when a predetermined fixed voltage is applied to the control input, the control inputs of unnecessary flip-flops are provided. By applying a predetermined fixed voltage, the unnecessary flip-flop can be operated as a mere wiring for signal propagation.

Further, as in the semiconductor integrated circuit according to the third aspect, a predetermined timing signal is given to the control input of one of the plurality of flip-flops and the control input of all the other flip-flops. The function module is configured to apply a predetermined fixed voltage, and the correlation between the setup time and the delay time of the functional module is selected according to the position on the signal path between the plurality of signal processing units of the flip-flop receiving the predetermined timing signal. Can be set as desired.

As a result, when the input side circuit and the output side circuit exist, the first time constraint and the second time constraint are considered in consideration of the first and second time constraints. In order to optimize the correlation between the setup time and delay time of the functional module under almost the same conditions, one of the flip-flops is given a predetermined timing signal and all other flip-flops are given. By applying a fixed voltage to the circuit, it is possible to minimize the rate-determining time of the circuit composed of the input side circuit, the functional block and the output side circuit, and improve the operating frequency thereof.

The means for variably setting in the semiconductor integrated circuit according to claim 4 applies a predetermined timing signal to the control input of one of the plurality of flip-flops based on the selection signal, and all the others. Since a selection circuit that applies a predetermined fixed voltage to the control input of the flip-flop of is provided, the position on the signal path between the plurality of signal processing units of the flip-flop that receives the predetermined timing signal can be determined by the selection signal. .

As a result, when the input side circuit and the output side circuit are present, by giving an appropriate selection signal, the setup time and delay of the functional module are taken into consideration in consideration of the first and second time constraints. A predetermined timing signal is given to one of the plurality of flip-flops so that the correlation with time is optimal,
A fixed voltage can be applied to all the other flip-flops, and the rate-determining time of the circuit composed of the input side circuit, the functional block and the output side circuit is minimized, and the operating frequency thereof is improved.

Since it is possible to selectively remove a plurality of flip-flops in the semiconductor integrated circuit according to the present invention and short-circuit the input and output of the removed flip-flops, unnecessary flip-flops are deleted. However, by shorting the input and output, unnecessary flip-flops can be physically deleted without impairing the operation of the functional block.

In the semiconductor integrated circuit according to the present invention, a predetermined timing signal is given to the control input of one flip-flop among the plurality of flip-flops, all other flip-flops are removed, and the flip-flop is turned on. Short-circuiting the outputs to selectively set the correlation between the setup time and the delay time of the functional module depending on the position on the signal path between the signal processing units of the flip-flop that receives a predetermined timing signal. You can

As a result, when the input side circuit and the output side circuit are present, the first time constraint and the second time constraint are considered in consideration of the first and second time constraints. In order to optimize the correlation between the setup time and delay time of the functional module under almost the same conditions, one of the flip-flops is given a predetermined timing signal and all other flip-flops are given. By deleting the loop and short-circuiting its input and output, the rate-determining time of the circuit composed of the input side circuit, the functional block, and the output side circuit can be minimized to improve its operating frequency.

At this time, since unnecessary flip-flops are physically deleted, useless delay time generated when a signal propagates between unnecessary flip-flops can be omitted, and the circuit operating frequency is further improved. Can be made.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an internal configuration of a functional module in a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a usage example of the functional module of the first embodiment.

FIG. 3 is an explanatory diagram showing a usage example of the functional module according to the first embodiment.

FIG. 4 is an explanatory diagram showing a usage example of the functional module according to the first embodiment.

FIG. 5 is an explanatory diagram showing an internal configuration of a functional module and its periphery in a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of an internal configuration of a flip-flop.

FIG. 7 is an explanatory diagram showing a usage example of a functional module according to a third embodiment.

FIG. 8 is an explanatory diagram showing a usage example of a functional module according to a third embodiment.

FIG. 9 is an explanatory diagram showing a usage example of a functional module according to a third embodiment.

FIG. 10 is an explanatory diagram showing an internal configuration of a conventional functional module.

FIG. 11 is a timing diagram showing the operation of the functional module.

FIG. 12 is an explanatory diagram showing a circuit of a conventional functional module and its peripheral portion.

13 is a timing diagram showing an operation of the circuit shown in FIG.

[Explanation of symbols]

2 to 4 flip-flops, 5 address buffers, 6
Decoder, 7 sense amplifiers, 8 output buffers, 1
6 Selection circuit.

Claims (6)

[Claims] 1. By comprising a plurality of signal processing units to which signals are sequentially transmitted, receiving an input signal, operating in response to a predetermined timing signal, and exchanging signals between the plurality of signal processing units. A semiconductor integrated circuit having a synchronous functional module that outputs an output signal based on the input signal, wherein the plurality of signal processing units have a control input and perform signal processing in response to a signal received by the control input. A means for variably setting the signal transmission sequence in the plurality of signal processing units of the at least one flip-flop that receives the predetermined timing signal at the control input among the at least one flip-flop, A semiconductor integrated circuit comprising: 2. The at least one flip-flop includes a plurality of flip-flops that are provided so as not to be adjacent to each other, and the plurality of flip-flops always pass input / output when a predetermined fixed voltage is applied to the control input. 2. The semiconductor integrated circuit according to claim 1, wherein signal processing is performed. 3. Of the plurality of flip-flops, the predetermined timing signal is applied to the control input of one flip-flop, and the predetermined fixed voltage is applied to the control inputs of all other flip-flops. , Claim 2
The semiconductor integrated circuit described. 4. The variably setting means receives a selection signal, supplies the predetermined timing signal to the control input of one of the plurality of flip-flops, and outputs the predetermined timing signal based on the selection signal. 3. The semiconductor integrated circuit according to claim 2, further comprising a selection circuit that applies the predetermined fixed voltage to the control inputs of all flip-flops. 5. The at least one flip-flop includes a plurality of flip-flops provided without being adjacent to each other, the plurality of flip-flops being selectively removable, and the removal of the removed flip-flops. The semiconductor integrated circuit according to claim 1, wherein the outputs can be short-circuited. 6. A flip-flop of the plurality of flip-flops is provided with the predetermined timing signal to the control input, all other flip-flops are removed, and the inputs and outputs thereof are short-circuited. Item 5. The semiconductor integrated circuit according to item 5.