JPH0831463B2 - Semiconductor device - Google Patents

Description

The present invention relates to the structure of a semiconductor device, and in particular, compared with a conventional structure, the current dependence of the current gain such as the current amplification factor and the cutoff frequency is high under high current conditions. And a semiconductor device suitable for improving high-speed operation characteristics.

[Conventional technology]

FIG. 2 is a schematic sectional view showing the vicinity of an emitter and a base region in a semiconductor device having a base sidewall contact structure (hereinafter referred to as SICOS) constructed according to the spirit described in JP-A-56-1556. .

In the figure, 1 is a P-type silicon single crystal substrate, 2 is an N-type high-concentration buried layer (N ⁺ buried layer) formed on the surface of the substrate 1 by diffusion, and 3 is a substrate on which a buried layer 2 is formed. 1. The emitter / base formation region of the N-type epitaxial silicon layer 4 grown on 1 is left as a square convex shape and the periphery thereof is removed by etching until it reaches the buried layer 2. Then, a silicon oxide film formed by thermal oxidation, Is a P-type polycrystalline silicon layer for side wall base contact provided on the silicon oxide film 3 around the upper side surface of the square convex N-type epitaxial silicon layer 4,
6 is SiO formed on the substrate including the polycrystalline silicon layer 4.
₂ film, 7 is an emitter hole provided on the square convex epitaxial layer 4 of the SiO ₂ film 6, 8 is a P type intrinsic base layer formed through the emitter hole 7, and 9 is an intrinsic base through the emitter hole 7. An emitter layer formed in contact with the layer 8 is a base, and a diffusion layer formed in the N-type epitaxial silicon layer 4 by impurities from the P-type polycrystalline silicon layer 5 at the time of heat treatment during formation of the base (hereinafter, referred to as Graft Base layer,
It is called GB layer for short).

Although not shown in the figure, in reality, the emitter electrode, the polycrystalline silicon layer 5 extending leftward from the side surface of the square convex N-type silicon epitaxial layer 4 on the emitter layer 9 through the emitter opening 7. The base electrode and the N ⁺ buried layer 2 extending to the right from the bottom of the silicon epitaxial layer 4 through the holes formed in the SiO ₂ film on the N ⁺ layer extending upward from the polycrystalline silicon layer 5 while avoiding the polycrystalline silicon layer 5. _{2 A} collector electrode is provided through a hole formed in the film.

A drawback of such a semiconductor device having the conventional structure is that the GB layer 10 extends to the bottom of the emitter layer 8, and the current amplification factor h _FE and the cutoff frequency f _T fall off in a particularly high current region.
This is the point that the SICOS structure cannot fully utilize the characteristics that the SICOS structure should have.

Further, as shown by B in FIG. 2, the GB layer 10
Depending on the amount of protrusion of the above into the convex epitaxial layer 4,
The base-emitter voltage V _BE also tends to fluctuate, which has been an obstacle to the application of this device to large-scale integrated circuits.

In addition, GB, as shown by A in Fig. 2,
There is a drawback that the lower end of the layer 10 is likely to come into contact with the high-concentration buried layer 2, which causes the lateral component of the base-contact capacitance C _TC to be very large.

[Problems to be solved by the invention]

As described above, the problem of the conventional technique arises from the areas A and B shown in FIG. The basis is that the GB layer 10 has a deep junction, and it is necessary to make a shallow junction, but the heat treatment temperature required in the manufacturing process to achieve this is lowered. It is difficult.

The object of the present invention is to measure the shallow junction of the GB layer of a semiconductor device having a base contact using a polycrystalline silicon layer, such as SICOS, thereby improving the high current characteristics of h _FE and f _T. It is to provide a semiconductor device having a new structure that can realize the above.

Another object of the present invention is to provide a semiconductor device having a structure that enables reduction of the side surface portion of the C _TC.

[Means for solving problems]

In the semiconductor device having a sidewall-based contact structure, the above-mentioned object is to determine the impurity concentration to be added to the polycrystalline silicon layer for sidewall-based contact from the contact point of the polycrystalline silicon layer with the sidewall of the base layer. This is achieved by controlling so that the density becomes lower from the position where a predetermined distance is maintained in the direction, as the contact point is approached.

As described above, in order to form the impurity concentration gradient in the polycrystalline silicon layer, the impurity is added into the polycrystalline silicon layer at a position apart from the contact point by a predetermined distance, and then the heat treatment is performed. It is preferable to employ a means for redistributing. Such means will be referred to as GB layer offset diffusion hereinafter.

The GB layer offset diffusion is effective because the diffusion coefficient of ion-implanted impurity atoms in the polycrystalline silicon layer is larger than that in the single crystal silicon substrate. FIG. 3 shows experimental data showing the above facts. FIG. 3A shows a cross-sectional view of the sample used in the experiment, and FIG. 3B shows the experimental result. In the figure (a), 101 is N
Conductive type 10Ω-cm single crystal silicon substrate, 102 is SiO
_Two films, 103 is a window provided in the SiO ₂ film 102, and 104 is a polycrystalline silicon layer having a thickness of 7,000 Å. This sample is subjected to B ⁺ ion implantation at 30 keV from the polycrystalline silicon layer 104 side, and after annealing at an annealing temperature of 950 ° C. for different treatment times, a region corresponding to the GB layer formed in the silicon substrate 101. The measurement result of the junction depth X _j of 105 is shown in FIG. In FIG. (B), the straight line 106 is a dose of 1 × 10 ¹⁶ cm ^-2, straight 107 is a result of performing experiments in a dose of 1 × 10 ¹⁵ cm ^-2. The diffusion coefficient of boron in the polycrystalline silicon layer is 1 × with respect to that in the single crystal silicon layer by performing a computer analysis on the result of FIG.
It was found that it was 300 times when the dose was 10 ¹⁶ cm ^-2 and 30 times when the dose was 1 × 10 ¹⁵ cm ^-2 . As described above, the phenomenon in which the diffusion coefficient increases under the high-dose condition also occurs with impurities other than boron.

As described above, since the impurity atoms in the polycrystalline silicon layer have a fairly large diffusion coefficient, although not infinite, under the high dose condition, according to the present invention, the primary effect of the offset amount and the There is also a secondary effect that some variations are mitigated. It should be noted that impurities in the offset region are larger than those in the region where the outer edge is not offset,
It does not require any special explanation for the low concentration as it approaches the active region formation surface.

However, the concentration gradient of the offset diffusion region generated here is not constant and depends on the process conditions such as the dose amount of ion implantation into the polycrystalline silicon layer and the total heat treatment amount (temperature and time) performed during the manufacturing process. It goes without saying that it will fluctuate.

[Function] GB offset diffusion is the junction depth of the GB layer formed by diffusion of impurities from the polycrystalline silicon layer into the single crystal silicon layer forming the base region connected to the polycrystalline silicon layer by selecting the offset amount. Can be easily controlled, and thus it is possible to prevent deterioration of the characteristics of the semiconductor device due to the GB layer.

Incidentally, referring to the sample drawing of FIG. 3A, the offset amount of the offset diffusion is equivalent to changing the thickness of the deposited polycrystalline silicon layer 104.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to examples.

Embodiment 1. FIG. 1 is a schematic sectional view showing a portion similar to FIG. 2 in the first embodiment of the present invention.

In the figure, 1 is a P-type silicon substrate, 2 is an N ⁺ buried layer,
3 is a silicon oxide film, 4 is a square convex N-type epitaxial silicon layer, 5 is a high concentration polycrystalline silicon layer, 5'is an offset diffusion region formed by diffusion of impurities from the high concentration polycrystalline silicon layer 5, 6 is a polycrystalline silicon layer 5,
5'is a silicon oxide film formed by thermal oxidation, 7 is an emitter hole provided in the silicon oxide film 6 on the epitaxial silicon layer 4, 8 is an intrinsic base layer, 9 is an emitter layer, 10
Is a GB layer formed on the side surface of a square convex N-type epitaxial layer by diffusion of impurities from the offset diffusion layer 5 '. In this case, the emitter opening 7 is formed from the periphery of the upper surface of the N-type epitaxial silicon layer 4 having a 2 × 3 μm ² square convex shape.
There was an aperture around the inside by 2 μm, and an offset diffusion region 5 ′ was provided with a width of 0.6 μm.

Compared with the conventional semiconductor device shown in FIG. 2, the semiconductor device of the above-described embodiment of the present invention is configured so that the GB layer 10 does not reach immediately below the emitter layer 9, so that the current amplification factor h
Good characteristics were obtained for both the _FE and the cutoff frequency f _T.

Further, by setting the dimensions of the offset region 5'and the emitter opening 7 as described above, the GB layer 10 overhanging from the polycrystalline silicon offset region 5'into the epitaxial silicon layer 4 is 0.5 μm in the past. Was
It could be 0.1 μm.

As a result, the maximum f _T value is 7.7 GHz for conventional semiconductor devices.
However, in the case of the present invention, it is improved to 10.3 GHz, and the base-collector capacitance C _TC is 16 fF in the conventional value.
However, in the present invention, it was improved to 11fF. From these facts, the one-input, delay time t _qd of the ECL (Emitter Coupled Logic) circuit was 87 ps / gate on average in the conventional device, but was improved to 78 ps / gate by the present invention.

 FIG. 4 is a drawing explaining the manufacturing process of the first embodiment.

FIG. 4 (a): A high-concentration N-type buried layer 22 is formed by diffusion in a predetermined region of a P-type Si single crystal substrate 21, and then an N-type epitaxial Si layer 23 is formed on the entire surface and SiO 2 is formed on the N-type epitaxial Si layer 23. ₂ film 24, Si ₃
After depositing the N ₄ film 25, the remainder is removed by etching only in the emitter-base formation region leaving the Si ₃ N ₄ film 25, SiO ₂ film 24. Then, the epitaxial Si layer 23 is dry-etched by using the remaining SiO ₂ film 24 and Si ₃ N ₄ film 25 as a mask to form a square-convex N-type Si layer 23. A SiO ₂ film 26 extending from the middle of the side surface of the N-type Si layer 23 to the N ⁺ buried layer 22 and the P-type substrate 21 is formed, and a polycrystalline Si layer is deposited on the entire surface, followed by patterning. , SiO ₂ film 24, Si ₃ N ₄ film
The polycrystalline Si layer on 25 was removed, and a polycrystalline Si layer 27 to be an external base region connected to the side surface of the N-type Si layer 23 having a square convex shape was formed.

FIG. 4 (b): A photoresist film is formed on the entire surface of the crystal, and this is processed to leave a resist film 28 protruding from the square-convex N-type Si layer 23 by a distance d ₃ to the periphery thereof. . At this time, the d ₃ was set to 0.6 μm. This 0.6 μm
Is the offset amount. Then, using the resist film 28 as a mask, B ⁺ ions were implanted in the polycrystalline Si layer 27. 29 is an ion implantation layer. Implant conditions are 30 keV, 1 × 10 ¹⁶ cm
^-2 dose. The thickness of the polycrystalline Si layer 27 is 7,000Å
Is.

FIG. 4 (c): The resist film 28 was removed, and the sample was thermally oxidized to form an Si oxide film 30 on the polycrystalline Si layer 27. Due to the heat treatment at this time, boron in the B ⁺ implantation layer 29 becomes a polycrystalline Si layer.
High concentration impurity polycrystalline Si layer 2 diffused downward and laterally of 27
7'and offset diffusion region with impurity concentration gradient (width
0.6μm) 27 ″ is formed and at the same time a square convex N-type Si layer 2
A GB layer 31 having a depth of 0.05 μm was formed from the side wall of No. 3 inside. After that, a thin SiO ₂ film on the surface of the square convex N-type Si layer 23 is formed.
When the 24, Si ₃ N ₄ film 25 is removed, an emitter opening 32 is opened on the square-convex N-type Si layer 23. At this time, the periphery of the emitter opening 32 is formed by entering about 0.2 μm from the outer periphery of the surface of the N-type Si layer 23 having a square convex shape.

Following this, although not shown in FIG. 4, a transistor structure is formed by forming a linear base layer emitter layer as shown in FIG. 1 by diffusion in a square convex N-type Si layer 23. can do. Since the subsequent steps and the like are known techniques, the description thereof will be omitted.

The GB layer is used to form the base and emitter regions above.
No. 31 was increased by 0.05 μm in the lateral direction to 0.1 μm, which is under the condition that the effect of the present invention is sufficiently exhibited.

FIG. 5 shows another manufacturing process example of the first embodiment.

FIG. 5 (a): Similar to FIG. 3 (a), an N ⁺ buried amount 22 is formed on a P-type Si single crystal Si substrate 21, and an N-type epitaxial Si layer 23 is further formed thereon. A mask composed of the SiO ₂ film 24 and the Si ₃ N ₄ film 25 is formed on the emitter / base formation region of the epitaxial Si layer 23, and the epitaxial Si layer 26 is etched using the mask until the N ⁺ buried layer 22 is reached. After forming the square convex N-type epitaxial Si layer 23, the square convex N-type epitaxial Si layer 23 is formed by thermal oxidation and etching.
SiO ₂ extending from the middle of the side surface of the N ⁺ buried layer 22 onto the P-type Si substrate 21
The film 26 is formed. Then, a thick SiO ₂ film 33 is formed on the Si ₃ N ₄ film 25 used as a mask.

FIG. 5 (b): A polycrystalline silicon layer 34 without impurities is formed on the entire upper surface to a thickness of 6000Å, and then on the entire surface.
B ⁺ ions were implanted to form a B ⁺ implant dose of 35.

FIG. 5 (c): Next, a polycrystalline silicon layer 35 is formed by using a photoresist trench burying technique and a dry etching technique.
The flattening process of the polycrystalline silicon layer 34
It was possible to form a polycrystalline Si layer 34 ′ with no impurity with a thickness of 6000 Å on the side wall portion of the N-type Si layer 23 having a square convex shape by removing the convex portion.

In this case, as in the manufacturing process example shown in FIG.
Square convex N without being affected by mask alignment error
Type impurity-free polycrystalline Si layer with an offset distance of exactly 6000Å from the sidewall of the epitaxial epitaxial Si layer 23
34 'can be formed.

It should be noted that, in the above-described structure, the high-concentration boron ion implantation layer 35 connecting the square convex N-type Si layer 23 to the outside of the impurity-free polycrystalline Si layer 34 connected to the upper portion of the side wall is used. An added polycrystalline Si layer 34 is formed. This is the fourth
The structure can be substantially similar to that shown in FIG. After that, the semiconductor device having the structure shown in FIG. 1 can be manufactured by the method described with reference to FIG.

FIG. 6 shows a further different manufacturing process example of the first embodiment.

In FIG. 6 (a), a polycrystalline silicon layer 34 without impurities is formed on the crystal in the state of FIG. 5 (a) to a thickness of 3000Å which is half of 6000Å in FIG. 5 (b).

When B ⁺ implantation is performed in this state, the offset amount is 3000Å. However, since the offset of 3000 Å is not sufficient, in this manufacturing process, a SiO ₂ film with a thickness of 3000 Å is formed on the entire surface of the sample by the CVD method, and then a dry etching process is performed, as shown in FIG. ), It was possible to leave the SiO ₂ film 36 having a thickness of 3000 Å on the side surface of the polygonal Si layer having no convex shape and no added impurities.
After that, a B ⁺ ion-implanted B ⁺ ion-implanted layer 35 is formed in the polycrystalline Si layer 34, and SiO ₂ is added as in the case of FIG. 5 (c).
By removing the film 36 and the polycrystalline Si layer 34 in the convex portion, the offset amount indicated by 34 'can be set to 6000Å.

Embodiment 2. FIG. 7 is a schematic sectional view showing a second embodiment of the present invention. In FIG. 7, 41 is a P-type silicon single crystal substrate,
42 is an N ⁺ buried layer, 43 and 44 are SiO ₂ films, 45 is a square convex N-type epitaxial Si layer, and 46 and 47 are emitter openings 48, respectively.
With SiO ₂ film, Si ₃ N ₄ film, 49 'is a high-concentration polycrystalline Si layer, 4
9 ″ is an offset diffusion region, 50 is a SiO ₂ film, 51 is an intrinsic base region, 52 is an emitter region, and 53 is a graft base region.

A transistor having such a structure is described in JP-A-56-142667, but in this case, it is difficult to make the GB layer 53 into a shallow junction.

In this embodiment, the GB extraction polycrystalline Si layer 49 undergoes offset diffusion in the region 49 '. 46,50 SiO ₂ film, 47 S
The i ₃ N ₄ film enables insulation between the emitter electrode (not shown) and the offset polysilicon layer 49.

With such a structure, it is possible to achieve a shallow junction of the GB layer 53 by the offset region 49 '. That is, even if the polycrystalline silicon layer is extracted from the intrinsic base region to the side surface of the active region having the emitter region and the base region as in the first embodiment, the active region of the active region is formed as in the present embodiment. Even from the surface, the spirit of the invention is unchanged.

In the second embodiment, the breakdown voltage between the emitter and the base BV _EBO
Has been improved from 4.0V to 7.0V. Also,
h _FE was improved from 40 when the collector current I _C was 1 mA to 60.

 FIG. 8 shows a second manufacturing process example of this embodiment.

FIG. 8 is a schematic explanatory view of an example of the manufacturing process of the semiconductor device of the second embodiment. That is, N ⁺ is formed on the P-type silicon substrate 41.
After the buried layer 42 is formed and an N-type epitaxial Si layer is formed on the buried layer 42, the buried layer 42 is processed to form a convex N-type Si layer 45, and SiO ₂ films 43 and 44 are formed on both sides thereof. After that, the square convex N
The SiO ₂ film 46 and the Si ₃ N ₄ film 4 are formed on the predetermined position of the central portion of the Si layer 45.
7 is formed, and a polycrystalline Si layer 49 is deposited on the entire surface of the sample. Then, after forming an emitter hole 48 that extends from the polycrystalline Si layer 49 to the Si ₃ N ₄ film 47, the polycrystalline Si layer 49 is thermally oxidized to form a SiO ₂ film 50 on its surface.

After that, a resist film 51 having a predetermined shape is formed on the SiO ₂ film 50 from the inside of the emitter opening 48 so that the offset amount d ₃ is 0.6 μm, and subsequently, B ⁺ ion implantation is performed at 30 keV, 1 × 10 ¹⁶ c
It was conducted under the condition of m ^-2 . 52 is an ion implantation layer. By annealing this, GB layer 53 shown in FIG.
Was formed.

Of course, in this case, the annealing can be performed simultaneously with the diffusion heat treatment for forming the base and emitter regions, which will be performed later.

Although the offset amount is set to 6000Å in the manufacturing process example of the above-described embodiment, this is an amount that should be selected larger or smaller depending on the process conditions.

〔The invention's effect〕

According to the present invention, a transistor having a structure using a polycrystalline silicon layer for extracting a base sidewall contact is formed.
The shallow junction of the GB layer is facilitated, and along with this, the current amplification factor, breakdown voltage, and capacitance are improved, and the circuit delay time with such devices is reduced, that is, high-speed operation is possible. There is.

Furthermore, in the conventional method, it is difficult to reduce the emitter width due to the deep junction of the GB layer, but according to the present invention, the shallow junction of the GB layer can be freely made. Such a problem does not occur.

[Brief description of drawings]

FIG. 2 is a schematic cross-sectional view of a conventional semiconductor device, FIG. 1 is a schematic cross-sectional view showing an embodiment of the semiconductor device of the present invention, and FIG. 3 is for explaining a diffusion coefficient of boron in a polycrystalline silicon layer. For explaining the experimental results of FIG. 4, FIGS. 4 to 6 are diagrams for explaining the manufacturing process of the embodiment shown in FIG. 1, and FIG. 7 is a schematic explanatory view showing another embodiment of the present invention. FIG. 8 is a diagram for explaining the manufacturing process of the embodiment shown in FIG. In the figure, 1,21,41 ...... P type silicon single crystal substrate 2,22,42 …… N ⁺ type silicon layer 3,26,43,44 …… SiO ₂ film 5 …… High concentration polycrystalline silicon layer 5 ′ …… Offset diffusion region 8 …… Intrinsic base region 9 …… Emitter region 10 …… GS layer 27 …… Polycrystalline silicon layer 27 ′ …… High concentration polycrystalline silicon layer 27 ″ …… Offset diffusion region 28 …… Resist Film 29,35 …… B ⁺ ion implantation layer 31 …… GB layer 36 …… SiO ₂ layer 46 …… SiO ₂ film 47 …… Si ₃ N ₄ film 49 …… Polycrystalline silicon layer 49 ′ …… High concentration Polycrystalline silicon layer 49 ″ …… Offset diffusion region 51 …… Intrinsic base region 52 …… Emitter region 53 …… GB layer

Claims (1)

[Claims] 1. A rectangular convex first conductivity type active region is formed on a surface of a semiconductor substrate, and a first conductivity type region formed on the surface side of the region in the active region and the first conductivity type. A second conductivity type region that is formed immediately adjacent to the mold region and surrounds the first conductivity type region, the second conductivity type region being exposed on a side surface or an upper surface of the square convex active region; A polycrystalline silicon layer doped with impurities of the second conductivity type is drawn out from the second conductivity type region by a predetermined distance in the outer direction through an insulating film formed on the substrate, and the second silicon layer is formed on the polycrystalline silicon layer. In a semiconductor device having a structure in which a conductive type region drawing electrode is formed, the concentration of the second conductive type impurity in the polycrystalline silicon layer is separated from the second conductive type region by a predetermined distance in an outward direction. Higher concentration as you go to the position Wherein a being controlled so.