JPH0831467B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention is a method for manufacturing a bipolar transistor, which is for forming a fine gap between an emitter region and an external base region, which is a semiconductor substrate of one conductivity type. An external base region of opposite conductivity type and high impurity concentration is formed, an impurity introduction mask is formed on the semiconductor substrate, an emitter window is opened on the external base region, and an external region above the emitter window is formed. An impurity of one conductivity type that cancels the base region is introduced, and then an impurity of the opposite conductivity type is introduced from the emitter window, the impurity concentration is lower than that of the external base region, and the thickness thereof is lower than that of the external base region. A thin intrinsic base region is formed, and then an impurity of one conductivity type is introduced from the emitter window to form an emitter region in the intrinsic base region. is there. By doing so, it becomes possible to form the inner edge portion of the external base region and the emitter region in a self-aligned manner.

[Industrial applications]

The present invention relates to a method for manufacturing a semiconductor device, and sometimes a method for manufacturing the bipolar transistor.

[Conventional technology]

A conventional technique will be described with reference to FIG. Figure 3 shows
FIG. 3 is a cross-sectional view showing the structure of a normal NPN bipolar transistor.

As shown in FIG. 3, a normal NPN bipolar transistor has an n-type silicon layer 3 provided on a high-concentration n-type buried layer 2 such as a p-type silicon substrate 1. A high-concentration p-type external base region 6, a p-type intrinsic base region 7, and an n-type emitter region 8 are formed in the interior by ion implantation or thermal diffusion.
[Problems to be Solved by the Invention] As described above, the normal bipolar transistor is provided with the external base region 6 having a high impurity concentration.
By reducing the withdrawal resistance of the intrinsic base region 7, which is a high resistance,
This is to speed up the device.

However, between the external base region 6 and the emitter region 8, there is a margin for preventing the external base 6 from diffusing and expanding in a later heat treatment step and coming into contact with the emitter region 8,
There is a distance a, which is a margin of alignment between the external base region 6 and the emitter region 8, and this is an obstacle to reducing the drawing resistance.

Further, the intrinsic base region 7 tends to be thin (shallowed) in order to improve the cutoff frequency F _{T of the} element,
Therefore, the resistance value of the intrinsic base region 7 becomes higher,
As a result, there has been a problem that the drawing resistance increases more and more.

[Means for solving problems]

In view of the above-mentioned problems, the present invention reduces the pull-out resistance of the intrinsic base region by first forming an extrinsic base region of opposite conductivity type on a semiconductor substrate of one conductivity type and having a high impurity concentration. Then, an impurity of one conductivity type that cancels the external base region is introduced from an impurity introduction mask and an emitter window provided on the surface of the external base region, and then an impurity of the opposite conductivity type is introduced from the emitter window. An intrinsic base region is formed, and then an impurity of one conductivity type is introduced through the emitter window to form an emitter region.

[Action]

According to the present invention, after the extrinsic base region is formed, impurities for canceling it are introduced through the emitter window, and then the intrinsic base region and the emitter region are formed through the emitter window. Can be extremely miniaturized, and as a result, the drawing resistance of the intrinsic base region can be significantly reduced. That is, the inner edge of the external base region and the emitter region are formed in a self-aligned manner through the emitter window.

〔Example〕

Hereinafter, a first embodiment of a method of manufacturing a bipolar transistor according to the present invention will be described in detail with reference to FIG. FIG. 1 is a sectional view showing a method of manufacturing an NPN bipolar transistor according to this embodiment in the order of steps.

First, as shown in FIG. 1 (A), a field oxide film (SiO ₂ ) 4 is formed on the surface of the n-type silicon layer 3 provided on the n ⁺ -type buried layer 2 by a normal selective oxidation method. , Then
Boron (B ⁺ ) is ion-implanted from the opening (introduction window 4a) at a dose amount of 1 × 10 ¹⁴ cm ^-2 and an acceleration energy of 30 Kev to form ap ⁺ -type external base region 6.

Next, as shown in FIG. 1 (B), an insulating film 5 made of, for example, silicon oxide (SiO ₂ ) is formed on the surface by, for example, a CVD method (vapor phase growth method), and then formed on the external Behis region 6. The emitter window 5a is opened.

Then, a conductive type impurity that cancels the external base region 6 is introduced through the emitter window 5a to cancel the external base region 6 directly below the emitter window 5a. In this embodiment, as a result of introducing phosphorus (P ⁺ ) at a dose amount of 2.0 × 10 ¹⁴ cm ^-2 and an acceleration energy of 80 Kev by an ion implantation method, as shown in FIG. 6 was countered.

Next, as shown in FIG. 1 (D), for example, boron (B ⁺ ) is ion-implanted from the emitter window 5a at a dose amount of 1 × 10 ¹³ cm ^-2 and an acceleration energy of 10 Kev to form a p-type The intrinsic base region 7 is formed.

Next, as shown in FIG. 1 (E), for example, arsenic (As ⁺ ) is ion-implanted from the emitter window 5a at a dose amount of 1 × 10 ¹⁶ cm ^-2 and an acceleration energy of 60 Kev to form an n ⁺ -type. To form the emitter region 8.

Finally, as shown in FIG. 1 (F), after opening a contact window in the insulating film 5 on the external base region 6, an electrode material made of aluminum (Al) is formed on the surface by, for example, a sputter growth method, and then patterned. Is formed to form a base electrode 6a contacting the external base region 6 and an emitter electrode 8a contacting the emitter region 8. Further, a collector region contacting the silicon layer 3 is provided in another region (not shown).

As described above, according to this embodiment, the distance a between the emitter region 8 and the external base region 6 is widened in the lateral direction due to the diffusion between the intrinsic base region 7 and the emitter region 8 as shown in FIG. Since it is determined, it can be formed extremely finely, and as a result, the drawing resistance can be significantly reduced.

Next, a second embodiment according to the present invention will be described with reference to FIG. In this embodiment, the present invention is applied to a conventional method for manufacturing a bipolar transistor by a self-alignment method, and FIG. 2 is a sectional view showing it in the order of steps.

First, as shown in FIG. 2A, a field oxide film (SiO ₂ ) 4 is formed on the surface of the n-type silicon layer 3 provided on the n ⁺ -type buried layer 2 by a normal selective oxidation method. After the formation, impurities such as boron (B ⁺ ) are injected through the opening (introduction window 4a) with a dose amount of 1 × 10 ¹⁴ cm ^-2 and an acceleration energy of 30 Kev.
Is ion-implanted to form ap ⁺ -type external base region 6.

Next, as shown in FIG. 2 (B), for example, by a CVD method (vapor phase growth method), a polysilicon 9 to be a lead electrode of the base region is formed on the surface, and after patterning the polysilicon 9, The insulating film 5 is formed by the thermal oxidation method.

Next, as shown in FIG. 2C, after depositing silicon oxide (SiO ₂ ) on the entire surface by, for example, a CVD method, RIE (selective ion etching) is performed to form sidewalls.
10 is formed on the side wall of the insulating film 5, and then, from the emitter window 10a surrounded by the side wall 10, an impurity such as phosphorus (P ⁺ ) having a dose of 2. is formed as in the first embodiment.
Ion implantation at 0 × 10 ¹⁴ cm ^-2 and acceleration energy of 80 Kev,
The external base region 6 directly below the emitter window 10a is canceled.

Next, as shown in FIG. 2 (D), after removing the insulating film 5 in the emitter window by using a hydrofluoric acid-based etching solution or a normal dry etching, the polysilicon is made to have a thickness of about 3000 Å by the CDV method, for example. And then patterned to form polysilicon that will serve as the extraction electrode in the emitter region.

Next, as shown in FIG. 2 (E), impurities such as boron (B ⁺ ) are doped in the polysilicon 11 at a dose of 5 × 10 ^14.
950 after ion implantation at cm ^-2 and acceleration energy of 25 Kev
Polysilicon 11 by heat treatment at ℃ for 30 minutes
Then, the ion-implanted boron is diffused to form an intrinsic base region 7.

Next, as shown in FIG. 2 (F), impurities such as arsenic (As ⁺ ) are doped in the polysilicon 11 at a dose of 5 × 10 ¹⁶ c.
After ion implantation at m ^-2 and acceleration energy of 100 Kev, 900
Polysilicon 1 by heat treatment at ℃ for 30 minutes
The ion-implanted arsenic is diffused from 1 to form an emitter region 8.

Finally, after opening a contact window in the insulating film 5 on the polysilicon 9, aluminum is formed on the surface by, for example, a sputter growth method, and then patterning is performed to contact the polysilicon 9 with the base electrode.
An emitter electrode that contacts 6a and polysilicon 11 is formed. Further, a collector electrode contacting the silicon layer 3 is provided in another region (not shown).

In this embodiment, the intrinsic base region 7 is formed by impurity diffusion from the polysilicon 11. Because of this, its thickness can be reduced, resulting in a cutoff frequency F _{T of the} device.
Can be higher.

Also in the present embodiment, as in the first embodiment,
As shown in FIG. 2 (G), the distance a between the emitter region 8 and the external base region 6 can be determined by the lateral spread due to the diffusion of the intrinsic base region 7 and the emitter region 8. As a result, even if the intrinsic base region 7 is formed thin and its resistance value becomes high as described above, the drawing resistance can be suppressed low. Further, although the present embodiment has been described only for the case of the NPN type bipolar transistor, it is clear that the same effect as above can be obtained even when the conductivity type is the PNP type.

〔The invention's effect〕

As described above in detail, according to the present invention, the distance between the emitter region and the extrinsic base region can be determined by the lateral spread due to the diffusion of the intrinsic base region and the emitter region. The drawing resistance is reduced and the device speed is improved. Further, even when the intrinsic base region is thinned (shallowed) to improve the cutoff frequency F _{T of the} device and the resistance value of the intrinsic base increases, according to the present invention, the external base region and the emitter region are Since the interval between the and is formed to be narrow, the increase of the drawing resistance can be suppressed.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing a second embodiment of the present invention, and FIG. 3 is a diagram showing the structure of a normal bipolar transistor. In the figure, 1 is a silicon substrate, 2 is a buried layer, 3 is a silicon layer, 4 is a field oxide film, 4a is an introduction window, 5 is an insulating film, 6 is an external base region, 7 is an intrinsic base region, and 8 is an emitter. Regions, 9 and 11 are polysilicon, 10 is a sidewall, 5a and 10 are emitter windows, 6a is a base electrode, and 8a is an emitter electrode.

Claims (1)

[Claims] 1. A step of forming an external base region of opposite conductivity type and high impurity concentration on a semiconductor substrate of one conductivity type, an impurity introduction mask is formed on a surface of the semiconductor substrate, and an emitter window is formed on the external base region. A step of opening an opening, a step of introducing an impurity of one conductivity type for canceling the external base region through the emitter window, and an impurity of an opposite conductivity type through the emitter window so that the impurity concentration is lower than that of the external base region. Forming an intrinsic base region that is low in thickness and thinner than the external base region; and introducing an impurity of one conductivity type from the emitter window to form an emitter region in the intrinsic base region. A method of manufacturing a semiconductor device, comprising: