JPH0832019A - Hybrid integrated circuit board and manufacturing method thereof - Google Patents
Hybrid integrated circuit board and manufacturing method thereofInfo
- Publication number
- JPH0832019A JPH0832019A JP6168309A JP16830994A JPH0832019A JP H0832019 A JPH0832019 A JP H0832019A JP 6168309 A JP6168309 A JP 6168309A JP 16830994 A JP16830994 A JP 16830994A JP H0832019 A JPH0832019 A JP H0832019A
- Authority
- JP
- Japan
- Prior art keywords
- bare chip
- electrode
- circuit board
- electrodes
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】
【目的】 導電ペーストで、電極間をショートすること
のないハイブリッド集積回路基板およびその製造方法を
提供することを目的としている。
【構成】 凹部１ａの底部に少なくとも１個のベアチッ
プ３を実装する金属スタッドバンプ２を形成した電極１
ｃと外周に回路基板に接続する端子１ｅを設け、前記凹
部の電極と外周の端子をパターンで接続している多層基
板１と、電極３ａ以外の部分に保護絶縁ペースト４を印
刷し、電極に導電ペースト５を印刷した前記少なくとも
１個のベアチップとで構成し、前記多層基板に設けた凹
部に前記ベアチップを実装し、モールドしている。
(57) [Abstract] [Purpose] It is an object of the present invention to provide a hybrid integrated circuit board which does not short-circuit between electrodes with a conductive paste and a manufacturing method thereof. An electrode 1 having a metal stud bump 2 for mounting at least one bare chip 3 on the bottom of a recess 1a
c and the outer periphery are provided with terminals 1e for connecting to a circuit board, and the protective insulating paste 4 is printed on portions other than the multilayer substrate 1 in which the electrodes of the recesses and the outer terminals are connected in a pattern, and electrodes are printed on the electrodes. It is composed of at least one bare chip on which a conductive paste 5 is printed, and the bare chip is mounted and molded in a recess provided in the multilayer substrate.
Description
【０００１】[0001]
【産業上の利用分野】ハイブリッド集積回路基板および
その製造方法に係わり、特に、キャビティタイプの多層
基板の凹部にベアチップを実装したハイブリッド集積回
路基板およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit board and a manufacturing method thereof, and more particularly to a hybrid integrated circuit board in which a bare chip is mounted in a concave portion of a cavity type multi-layer substrate and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来、ベアチップを多層基板１に設けた
凹部に実装する場合、図３に示すように、前記多層基板
１の電極１ａおよび電極１ｂに、針のように先の尖った
ピン９の先に導電性接着剤ペースト（以下導電ペースト
と略す）５を少量つけて塗布し、電極にＡｕスタッドバ
ンプ２を形成するベアチップ３を、実装する第一の方法
と、図４に示すように、予め導電ペースト５を平滑に印
刷した板１０の上に、電極３ａにＡｕスタッドバンプ２
を形成するベアチップ３の電極面を押しつけ、Ａｕスタ
ッドバンプ２に導電ペースト５を転写し、これを前記多
層基板１に実装する第二の方法があった。しかし、図５
に示すように、これらの方法では導電ペーストを電極に
塗布または転写する際、電極間をショートしてしまうと
いう問題があった。2. Description of the Related Art Conventionally, when a bare chip is mounted in a recess provided in a multi-layer substrate 1, a pin 9 having a sharp point like a needle is attached to an electrode 1a and an electrode 1b of the multi-layer substrate 1 as shown in FIG. A small amount of a conductive adhesive paste (hereinafter abbreviated as a conductive paste) 5 is applied to the tip of the above, and the bare chip 3 for forming the Au stud bumps 2 on the electrodes is mounted, as shown in FIG. , The Au stud bumps 2 are formed on the electrodes 3a on the plate 10 on which the conductive paste 5 is printed in advance.
There is a second method in which the electrode surface of the bare chip 3 forming the is pressed, the conductive paste 5 is transferred to the Au stud bumps 2, and this is mounted on the multilayer substrate 1. However, FIG.
As shown in FIG. 2, these methods have a problem that when the conductive paste is applied or transferred to the electrodes, the electrodes are short-circuited.
【０００３】[0003]
【発明が解決しようとする課題】本発明は以上述べた問
題点を解決し、導電ペーストで、電極間をショートする
ことのないハイブリッド集積回路基板およびその製造方
法を提供することを目的としている。SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a hybrid integrated circuit board which does not short circuit between electrodes with a conductive paste and a method for manufacturing the same.
【０００４】[0004]
【課題を解決するための手段】本発明は上述の課題を解
決するため、凹部に少なくとも１個のベアチップを実装
する金属スタッドバンプを形成した電極と外周に回路基
板に接続する端子を設け、前記凹部の電極と外周の端子
をパターンで接続している多層基板と、電極以外の部分
に保護絶縁ペーストを印刷し、電極に導電ペーストを印
刷した前記少なくとも１個のベアチップとで構成し、前
記多層基板に設けた凹部に前記ベアチップを実装し、モ
ールドしている。また、多層基板に設けた凹部に、ベア
チップを実装するものにおいて、多層基板の凹部の前記
ベアチップの電極に対応する電極に金属スタッドバンプ
を形成し、前記ベアチップの電極面の電極以外の部分に
保護絶縁ペーストを印刷し、硬化後、電極に導電ペース
トを印刷し、該ベアチップを前記多層基板の凹部に実装
するようにしている。In order to solve the above-mentioned problems, the present invention provides an electrode having a metal stud bump for mounting at least one bare chip in a recess and a terminal for connecting to a circuit board on the outer periphery, The multilayer substrate in which the electrode in the recess and the terminal on the outer periphery are connected by a pattern, and the at least one bare chip in which a protective insulating paste is printed on a portion other than the electrode and a conductive paste is printed on the electrode, The bare chip is mounted and molded in the recess provided in the substrate. Further, in a case where a bare chip is mounted in a recess provided in a multilayer substrate, a metal stud bump is formed on an electrode corresponding to the electrode of the bare chip in the recess of the multilayer substrate to protect a portion other than the electrode on the electrode surface of the bare chip. After printing an insulating paste and curing it, a conductive paste is printed on the electrodes to mount the bare chips in the recesses of the multilayer substrate.
【０００５】[0005]
【作用】以上のように構成したので、本発明のハイブリ
ッド集積回路基板およびその製造方法によれば、多層基
板に設ける凹部の電極に、ワイヤーボンディング機等で
金属スタッドバンプを形成し、前記多層基板に電極以外
の電極面に保護絶縁ペーストを印刷し、硬化後、電極に
導電ペーストを印刷したベアチップを実装しているの
で、導電ペーストが印刷できるため電極間のショートを
防止し、さらに、保護絶縁ペーストがその信頼性を向上
している。With the above structure, according to the hybrid integrated circuit board and the method of manufacturing the same of the present invention, metal stud bumps are formed on the electrodes of the recesses provided in the multilayer board by a wire bonding machine or the like, and the multilayer board is formed. A protective insulating paste is printed on the electrode surfaces other than the electrodes, and after curing, a bare chip is printed with conductive paste printed on the electrodes, so conductive paste can be printed to prevent short-circuiting between electrodes. The paste improves its reliability.
【０００６】[0006]
【実施例】以下、図面に基づいて本発明によるハイブリ
ッド集積回路基板およびその製造方法を詳細に説明す
る。図１は本発明によるハイブリッド集積回路基板の一
実施例を示す断面図である。図において、１は凹部を２
段設ける多層基板で、最も深い２段目の凹部１ａの底に
は、電極１ｃが形成され、１段目の凹部１ｂの底に形成
する電極１ｄおよび、基板外周側面に形成する電極１ｅ
と内部パターンで接続されている。２はＡｕスタッドバ
ンプで、前記多層基板の電極１ｃおよび電極１ｄ上に、
ワイヤーボンディング機で熱圧着して形成している。３
はベアチップで、まず、電極３ａ以外の電極面に保護絶
縁樹脂ペースト４を印刷し熱を加えて硬化させ、つぎ
に、電極３ａに導電ペースト５を印刷している。６はベ
アチップ等の部品で、前記ベアチップ３と同じ処理をし
ている。７は回路基板である。８はモールド材である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A hybrid integrated circuit board and a method for manufacturing the same according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of a hybrid integrated circuit board according to the present invention. In the figure, 1 indicates a concave portion 2
An electrode 1c is formed on the bottom of the deepest recess 1a in the second step, and an electrode 1d is formed on the bottom of the recess 1b in the first step and an electrode 1e is formed on the outer peripheral side surface of the substrate.
And are connected by an internal pattern. 2 is an Au stud bump, which is formed on the electrodes 1c and 1d of the multilayer substrate,
It is formed by thermocompression bonding with a wire bonding machine. Three
Is a bare chip. First, the protective insulating resin paste 4 is printed on the electrode surface other than the electrode 3a and cured by applying heat, and then the conductive paste 5 is printed on the electrode 3a. Reference numeral 6 denotes a component such as a bare chip, which is processed in the same manner as the bare chip 3. 7 is a circuit board. Reference numeral 8 is a molding material.
【０００７】以上の構成において、つぎにハイブリッド
集積回路基板の製造方法を図２の流れ図にそって説明す
る。凹部を２段設ける多層基板１は、図２−ａのよう
に、電極１ｃ及び電極１ｄにＡｕスタッドバンプ２をワ
イヤーボンディング機により熱圧着している。ベアチッ
プ３は、まず、図２−ｂに示すように、電極３ａ以外の
電極面に保護絶縁樹脂ペースト４を印刷し熱を加えて硬
化させ、つぎに、図２−ｃに示すように、電極３ａに導
電ペースト５を印刷している。以上の加工の終わった前
記ベアチップ３を、図２−ｃに示すように、加工の終わ
った前記多層基板１の２段目の収納部に電極面を合わせ
て挿着し、所定の温度で熱処理して実装している。つぎ
に、図２−ｄに示すように、前記２段目の収納部に前記
ベアチップ３の実装の終わった多層基板１に、同様に加
工した別のベアチップ等６を実装している。全ての実装
が完了した多層基板１はモールド材８でモールド処理し
た後、図１のように、回路基板７に表面実装している。A method of manufacturing the hybrid integrated circuit board having the above structure will be described below with reference to the flow chart of FIG. As shown in FIG. 2A, the multi-layer substrate 1 having the two recesses has the Au stud bumps 2 thermocompression bonded to the electrodes 1c and 1d by a wire bonding machine. In the bare chip 3, first, as shown in FIG. 2B, the protective insulating resin paste 4 is printed on the electrode surface other than the electrode 3a and hardened by applying heat, and then as shown in FIG. The conductive paste 5 is printed on 3a. As shown in FIG. 2C, the bare chip 3 that has been processed as described above is inserted into the second-stage storage portion of the processed multilayer substrate 1 with its electrode surface aligned and heat-treated at a predetermined temperature. And implemented. Next, as shown in FIG. 2D, another bare chip or the like 6 processed in the same manner is mounted on the multilayer substrate 1 on which the bare chip 3 has been mounted in the second-stage storage section. The multi-layer substrate 1 on which all the mounting is completed is subjected to a molding process with the molding material 8 and then surface-mounted on the circuit board 7 as shown in FIG.
【０００８】[0008]
【発明の効果】以上説明したように、本発明によるハイ
ブリッド集積回路基板およびその製造方法によれば、多
層基板に設ける凹部の電極に、ワイヤーボンディング機
等で金属スタッドバンプを形成し、前記多層基板に電極
以外の電極面に保護絶縁ペーストを印刷し、硬化後、電
極に導電ペーストを印刷したベアチップを実装してお
り、導電ペーストを印刷しているため電極間のショート
が防止でき、さらに、保護絶縁ペーストの印刷がその信
頼性を向上している。As described above, according to the hybrid integrated circuit board and the method of manufacturing the same according to the present invention, metal stud bumps are formed on the electrodes of the recesses provided in the multilayer board by a wire bonding machine or the like, and the multilayer board is formed. A protective insulating paste is printed on the electrode surface other than the electrodes, and after curing, a bare chip is printed with conductive paste printed on the electrodes.Because the conductive paste is printed, short circuits between electrodes can be prevented, and further protection Printing the insulating paste improves its reliability.
【図１】本発明によるハイブリッド集積回路基板の一実
施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of a hybrid integrated circuit board according to the present invention.
【図２】本発明によるハイブリッド集積回路基板の製造
方法の一実施例を示す流れ図である。FIG. 2 is a flow chart showing an embodiment of a method for manufacturing a hybrid integrated circuit board according to the present invention.
【図３】従来のハイブリッド集積回路基板の一製造方法
の流れを示す図である。FIG. 3 is a diagram showing a flow of a method of manufacturing a conventional hybrid integrated circuit board.
【図４】従来のハイブリッド集積回路基板の別の製造方
法の流れを示す図である。FIG. 4 is a diagram showing a flow of another conventional method for manufacturing a hybrid integrated circuit board.
【図５】従来のハイブリッド集積回路基板のショート状
況を示す図である。FIG. 5 is a diagram showing a short circuit situation of a conventional hybrid integrated circuit board.
１ キャビティタイプ多層基板 １ａ電極 １ｂ電極 １ｃ電極 ２ Ａｕスタッドバンプ ３ ベアチップ ３ａ電極 ４ 保護絶縁樹脂ペースト ５ 導電ペースト ６ ベアチップ等 ７ 回路基板 ８ モールド材 1 Cavity Type Multilayer Substrate 1a Electrode 1b Electrode 1c Electrode 2 Au Stud Bump 3 Bare Chip 3a Electrode 4 Protective Insulating Resin Paste 5 Conductive Paste 6 Bare Chip 7 Circuit Board 8 Molding Material
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/12 Ｆ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 23/12 F
Claims (5)
プを実装する金属スタッドバンプを形成した電極と外周
に回路基板に接続する端子を設け、前記凹部の電極と外
周の端子をパターンで接続している多層基板と、電極以
外の部分に保護絶縁ペーストを印刷し、電極に導電ペー
ストを印刷した前記少なくとも１個のベアチップとで構
成し、前記多層基板に設けた凹部に前記ベアチップを実
装し、モールドしていることを特徴とするハイブリッド
集積回路基板。1. An electrode having a metal stud bump for mounting at least one bare chip on the bottom of the recess and a terminal for connecting to a circuit board are provided on the outer periphery, and the electrode of the recess and the terminal on the outer periphery are connected in a pattern. And a bare chip in which a protective insulating paste is printed on a portion other than the electrodes and a conductive paste is printed on the electrodes, and the bare chip is mounted in a recess provided in the multi-layer substrate and molded. A hybrid integrated circuit board characterized in that
実装するものにおいて、多層基板の凹部の前記ベアチッ
プの電極に対応する電極に金属スタッドバンプを形成
し、前記ベアチップの電極に導電ペーストを印刷し、該
ベアチップを前記多層基板に設けた凹部に実装するよう
にしていることを特徴とするハイブリッド集積回路基板
の製造方法。2. In a method of mounting a bare chip in a recess provided in a multilayer substrate, a metal stud bump is formed on an electrode corresponding to the electrode of the bare chip in the recess of the multilayer substrate, and a conductive paste is printed on the electrode of the bare chip. Then, the bare chip is mounted in a recess provided in the multi-layer substrate.
ンディング機で金属線を熱圧着していることを特徴とす
る請求項２記載のハイブリッド集積回路基板の製造方
法。3. The method for manufacturing a hybrid integrated circuit board according to claim 2, wherein the metal stud bump is formed by thermocompression bonding a metal wire by a wire bonding machine.
の印刷は、前記ベアチップの電極面の電極以外の部分に
保護絶縁ペーストを印刷し、硬化後、行っていることを
特徴とする請求項２記載のハイブリッド集積回路基板の
製造方法。4. The printing of the conductive paste on the electrodes of the bare chip is performed after printing the protective insulating paste on a portion other than the electrodes on the electrode surface of the bare chip and curing the paste. For manufacturing a hybrid integrated circuit board.
チップの外形寸法より少し大き目の内形寸法としている
ことを特徴とする請求項２記載のハイブリッド集積回路
基板の製造方法。5. The method of manufacturing a hybrid integrated circuit substrate according to claim 2, wherein the multilayer substrate having the recess has an inner dimension slightly larger than the outer dimension of the bare chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6168309A JPH0832019A (en) | 1994-07-20 | 1994-07-20 | Hybrid integrated circuit board and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6168309A JPH0832019A (en) | 1994-07-20 | 1994-07-20 | Hybrid integrated circuit board and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0832019A true JPH0832019A (en) | 1996-02-02 |
Family
ID=15865642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6168309A Pending JPH0832019A (en) | 1994-07-20 | 1994-07-20 | Hybrid integrated circuit board and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0832019A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100368607B1 (en) * | 2000-04-17 | 2003-01-24 | 주식회사 케이이씨 | semiconductor package |
-
1994
- 1994-07-20 JP JP6168309A patent/JPH0832019A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100368607B1 (en) * | 2000-04-17 | 2003-01-24 | 주식회사 케이이씨 | semiconductor package |
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