JPH0832073A - Thin film transistor array element - Google Patents

Abstract

PURPOSE:To provide a thin film transistor array element having high reliability and excellent performance capable of diminishing deterioration in the off characteristics of TFT caused by longtime driving operation. CONSTITUTION:Within the thin film transistor array element provided with a selfmatching reversed stagger structured thin film transistor forming a picture element electrode formed corresponding to respective intersections of signal lines and scanning lines of an insulating substrate as well as a gate electrode using a protective insulating film pattern of a channel part as masks, the width W1 of a semiconductor layer 3 in the path of current from a source electrode 7a of the thin film to a drain electrode 7b through a semiconductor layer 3 is made narrower than the width W2 and W3 of the source electrode 7a and the drain electrode 7b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array element for realizing a liquid crystal display device having high reliability and excellent display quality.

[0002]

2. Description of the Related Art A liquid crystal display device (hereinafter abbreviated as LCD) using an amorphous silicon thin film transistor (hereinafter abbreviated as a-SiTFT) as a switching element is a CRT.
It has been applied in various fields such as pocket TVs, viewfinders for video cameras, personal computers and word processors as flat displays with display performance comparable to that of the.

Currently, such LCD a-Si TFTs are used.
The structure which is widely put into practical use is a so-called inverted stagger type structure in which a gate electrode is arranged in a lower layer. This structure is a self-aligned type in which the protective insulating film pattern of the channel part is formed by exposing from the back surface of the substrate, and since the gate insulating layer and the semiconductor layer can be continuously formed in vacuum, it is relatively stable. It has an advantage that a transistor can be formed.

An a-Si TFT having such an inverted stagger structure
The structure of a general TFT (Thin Film Transistor) -LCD that uses as a switching element will be described with reference to FIG. In FIG. 9, (a) is a sectional view showing the structure of the LCD, and (b) is a plan view of the TFT. In the figure,
Reference numeral 1 is a gate electrode formed on an insulating substrate 12a, 2 is a gate insulating film, 3 is an a-Si (amorphous silicon) semiconductor layer, and 4 is an insulating film for protecting the semiconductor layer 3. 5 is an n-type a-Si doped with phosphorus as an impurity
The layers 7a and 7b represent a source electrode and a drain electrode, respectively. Reference numeral 6 is a pixel electrode electrically connected to the drain electrode 7b. Reference numeral 8 is an overcoat insulating film for protecting the thin film transistor, and generally silicon nitride (SiNx) is used. 9a, 9b
Indicates an alignment film, and 10 indicates a liquid crystal layer. Reference numeral 11 is a counter electrode formed on the insulating substrate 12b.

Next, a driving method of the TFT-LCD will be described. FIG. 8 shows a drive signal waveform supplied to each electrode of the TFT-LCD. Vg is a scanning signal given to the gate electrode 1 of the TFT, Vs is a display signal given to the source electrode 7a of the TFT, and when the TFT is turned on, the display signal Vs is drain voltage Vd through the TFT.
Is applied to the pixel electrode 6. Vsc indicates the middle point of the display signal voltage amplitude. DC voltage V is applied to the counter electrode 11.
c is applied. Ton is the ON period of the TFT, and Tof
f indicates the off period.

[0006]

At present, it is known that the following image phenomenon appears when a TFT-LCD panel having the above-mentioned structure is driven at a high temperature for a long time. Has been. One is a phenomenon of printing in which the same fixed pattern is displayed as an afterimage when the same fixed pattern is displayed for a long time, and the other is a phenomenon of a decrease in contrast caused by deterioration of off characteristics of the TFT. Is. Hereinafter, these problems will be described in detail with reference to FIGS. 8 and 9.

First, the printing phenomenon will be described. As shown in FIG. 9, in the TFT having such a structure, a parasitic capacitance Cgd between the gate and the drain electrode is formed in a region where the gate electrode 1 and the drain electrode 7b overlap each other in plan view. As can be seen from the signal waveform of FIG.
When the LCD is driven, this parasitic capacitance Cgd causes
The potential drop Δ of the drain voltage Vd applied to the pixel electrode 6
Vd is generated, and a DC voltage is applied to the layer of the liquid crystal 10 on the pixel electrode 6. This potential drop ΔVd can be expressed as ΔVd = Cgd (Vgt-Vgb) / (Clc + Cst + Cgd), and increases as the parasitic capacitance Cgd increases. Here, Clc is a liquid crystal capacitance, Cst is an additional capacitance, Vgt is a potential when the scanning signal Vg is on, and Vgb is a potential when the scanning signal Vg is off.

Therefore, as the potential drop ΔVd increases, the DC voltage component to the layer of the liquid crystal 10 also increases. Such a DC voltage component to the layer of the liquid crystal 10 induces an internal charge in the layer of the liquid crystal 10 and, as a result, causes an image quality problem such as printing. Next, TF
The deterioration of the off characteristic of T will be described. As shown in FIG. 9, in the TFT-LCD, the alignment film 9a and the liquid crystal layer 10 exist on the channel of the TFT. Further, as shown in FIG. 8, in operation, the gate electrode 1 of the TFT has an off period Toff in the off state to which the negative gate bias Vgb is applied except for a slight on period Ton in which the TFT is in the on state. Then, during this period, the drain voltage Vd supplied to the pixel electrode 6 through the TFT is held. That is, between the counter electrode 11 and the gate electrode 1, most of the time,
A direct current voltage having a positive side on the counter electrode 11 side and a negative side on the gate electrode 1 side is applied. Thereby, the alignment film 9a
Causes polarization on the a-Si semiconductor above the TFT, and a-
Electrons are induced in the upper layer of the Si semiconductor layer 3 and the off-characteristics of the TFT are deteriorated (reference: Ogawa et al. 1989 Kansai Branch Joint Conference on Electrical Relations, G31).
3, G10-30).

FIG. 10 shows a TFT in a TFT-LCD configuration.
2 is a result of measuring the change over time of the Id-Vg characteristic representing the switching performance of the TFT in the relationship between the current Id flowing between the source electrode 7a and the drain electrode 7b and the voltage Vg applied to the gate electrode 1. As can be seen from FIG. 10, in comparison with the initial characteristic P ₁ , the characteristic P ₂ after operating for 24 hours shows an increase in the current in the subthreshold region which is the boundary portion from the ON state to the OFF state. Such deterioration of the switching characteristics deteriorates the voltage holding characteristics of the liquid crystal 10 in the TFT-LCD, resulting in image quality problems such as a reduction in contrast and point defects.

The present invention has been made in view of the above problems. First, the deterioration of the off characteristics of the TFT caused by long-time driving is reduced, and secondly, between the gate electrode and the drain electrode. DC to liquid crystal layer due to parasitic capacitance
It is possible to prevent the deterioration of reliability and the occurrence of the burning phenomenon due to the voltage application, and further improve the brightness of the screen with the improvement of the aperture ratio of the TFT-LCD, that is, the ratio of the area displayed by the pixel electrodes to the area of the entire screen. An object of the present invention is to provide a thin film transistor array element having high reliability and excellent performance.

[0011]

According to another aspect of the present invention, there is provided a thin film transistor array element having an insulating substrate having signal lines and scanning lines arranged in a matrix on one main surface, and a signal line and a scanning line of the insulating substrate. A self-alignment type pixel electrode formed corresponding to each intersection and a protective insulating film pattern of the channel portion are formed by performing exposure using the gate electrode as a mask from the other surface different from one main surface of the insulating substrate. A reverse staggered structure having a thin film transistor provided between the pixel electrode and the signal line and the scanning line, the width of the semiconductor layer in the path of the current flowing from the source electrode of the thin film transistor through the semiconductor layer to the drain electrode, It is characterized in that it is narrower than at least one of the widths of the source electrode and the drain electrode.

A thin film transistor array element according to a second aspect of the present invention is the thin film transistor array element according to the first aspect, wherein the difference between at least one of the widths of the source electrode and the drain electrode and the width of the semiconductor layer of the thin film transistor is 4 μm or more. A thin film transistor array element according to a third aspect of the present invention is the thin film transistor array element according to the first aspect, in which the source electrode and the drain electrode are formed so as to be aligned with the gate electrode protruding from the scanning line in the direction of the scanning line, It is located inside at least one of the electrode and the drain electrode.

[0013]

According to the thin film transistor array element of claim 1, the scanning signal is applied to the scanning line and the display signal is applied to the signal line, the thin film transistor is turned on, and the voltage is applied to the pixel electrode to display the liquid crystal on the pixel electrode. To do. In this case, since the width of the semiconductor layer in the path of the current flowing from the source electrode of the thin film transistor to the drain electrode through the semiconductor layer is narrower than at least one of the widths of the source electrode and the drain electrode, The potential in the vicinity of the alignment film is less likely to be affected by the potential of the counter electrode and is controlled by the potentials of the source electrode and the drain electrode. This stabilizes the potential in the vicinity of the alignment film, and can suppress the induction of electrons in the upper layer portion of the a-Si semiconductor due to the polarization described above. Therefore, it is possible to reduce the deterioration of the off characteristics of the thin film transistor caused by driving for a long time, and it is possible to maintain the image quality.

According to the thin film transistor array element of claim 2, the difference between at least one of the widths of the source electrode and the drain electrode and the width of the semiconductor layer of the thin film transistor is set to 4 μm or more. Has the same effect as 1. According to the thin film transistor array element of claim 3, the source electrode and the drain electrode are formed so as to line up in the scanning line direction with respect to the gate electrode protruding from the scanning line, and the tip portion of the gate electrode is formed. Since it is located inside at least one of the source electrode and the drain electrode, the area of the gate electrode can be further reduced without changing the on-current magnitude of the thin film transistor, in addition to the function of claim 1, and thus the gate electrode to the drain electrode. The parasitic capacitance between them becomes small, the DC applied component to the liquid crystal layer is reduced, and the potential drop of the pixel electrode can be suppressed. Therefore, it is possible to prevent the deterioration of reliability and the occurrence of the burning phenomenon, and it is possible to improve the brightness of the screen with the improvement of the aperture ratio, that is, the ratio of the area displayed by the pixel electrodes to the area of the entire screen. Achieves excellent performance with reliability.

[0015]

FIG. 1 shows a thin film transistor array element according to a first embodiment of the present invention. That is, FIG. 1 shows the structure of a thin film transistor array element, (a) is a sectional view thereof,
(B) shows a plan view. In the figure, 1 is a gate electrode,
2 is a first insulating film (gate insulating film), 3 is a semiconductor layer, 4
Is a second insulating film (protective insulating film), 5 is a P-doped semiconductor layer, 6 is a transparent electrode (pixel electrode), 7a is a source electrode, 7
Reference numeral b is a drain electrode, and 8 is a third insulating film (overcoat insulating film).

Here, a specific method of manufacturing the thin film transistor array element of the first embodiment will be briefly described with reference to FIG. 7 (1) to (9), the left side is a plan view and the right side is a sectional view. In addition, in the thin film transistor array element of the first embodiment, an inverted stagger type a-SiT formed by exposing the pattern of the second insulating film 4 as a switching element by exposing from the back surface of the insulating substrate 12a.
FT was used.

(1) After forming a film of Cr as the gate electrode 1 on the transparent insulating substrate 12a and patterning it, (2)
SiNx as the first insulating film 2 and a- as the semiconductor layer 3
Si and SiNx are continuously formed as the second insulating film 4.
(3) In the photolithography process, the insulating substrate 1
After the positive photoresist 15 is applied to the entire surface of 2a, only the second insulating film 4 is applied to the gate electrode 1 from the back surface of the insulating substrate 12a using the pattern of the gate electrode 1 as a mask.
Other parts are exposed in the direction of the arrow. (4) Then,
A portion other than the mask 16 is exposed from the surface of the insulating substrate 12a by using another mask 16 in the direction of the arrow, (5) As a result, the resist 15 is formed on the portion where the pattern of the gate electrode 1 and the mask 16 are two-dimensionally overlapped. Remain, and the second insulating film 4 is patterned by using it as a mask. (6) After forming n + a-Si as the P-doped semiconductor layer 5, the semiconductor layer 3 and P
The doped semiconductor layer 5 is patterned. (7) Pixel electrode 6
After forming ITO and patterning it as, the first insulating film 2 is patterned. (8) An Al film is formed as the source electrode 7a and the drain electrode 7b and patterned. The drain electrode 7b and the pixel electrode 6 are electrically connected.
(9) Finally, SiNx is formed as the third insulating film 8,
By patterning, the thin film transistor array element of the first embodiment was completed.

Next, the characteristics of the thin film transistor array element of the first embodiment will be described. First, the width W1 of the semiconductor layer 3 in the path of the current flowing from the source electrode 7a of the thin film transistor to the drain electrode 7b via the semiconductor layer 3 is narrower than the width W2 of the source electrode 7a and the width W3 of the drain electrode 7b, and The difference between the width W1 of the source electrode 7a and the width W3 of the drain electrode 7b and the width W1 of the semiconductor layer 3 is 4 μm or more. That is, W
2-W1 ≧ 4 μm and W3-W1 ≧ 4 μm. TFT using a thin film transistor array element having such a structure
-For LCDs, the change in TFT characteristics over time was evaluated.
The operation test was performed at 60 ° C. Fig. 2 shows the TFT Id-V
An initial characteristic Q ₁ of the g characteristic and a characteristic Q ₂ after 24 hours of operation are shown. As shown in FIG. 2, in this embodiment, the width W1 of the semiconductor layer 3 of the thin film transistor array is set to the source electrode 7a.
It can be seen that the change over time in the OFF characteristics is sufficiently suppressed by adopting a configuration in which the width is smaller than the width W2 and the width W3 of the drain electrode 7b.

A second embodiment of the present invention is shown in FIG. That is, this thin film transistor array element is one in which the channel portion of the TFT is formed with the gate electrode 1 on the scanning line serving as the gate wiring, and other characteristics are the same as in the first embodiment. Therefore, also in the second embodiment, similarly to the first embodiment, the drain electrode 7 is formed from the source electrode 7a of the thin film transistor via the semiconductor layer 3.
The width W1 of the semiconductor layer 3 in the path of the current flowing to b is
The width W2 of the source electrode 7a and the width W of the drain electrode 7b
The width is narrower than that of 3, and the difference is 4 μm or more. With this configuration, the off characteristic is improved.

In the second embodiment, since the thin film transistor is formed on the gate wiring, the area occupied by the pixel electrode 6 can be increased as compared with the first embodiment, so that the TFT- The aperture ratio of LCD is improved and T
This has the effect of improving the screen brightness of the FT-LCD.
A thin film transistor array element according to a third embodiment of the present invention will be described with reference to FIG. In this embodiment, the width W1 of the semiconductor layer 3 of the thin film transistor is the width W of the drain electrode 7b.
It is narrower than 3 and the difference is 4 μm or more. Even in the thin film transistor array element having such a configuration,
As a result of performing an operation test in the same manner, the off characteristics of the thin film transistor were almost the same as those in the first and second embodiments.

A thin film transistor array element according to a fourth embodiment of the present invention will be described with reference to FIG. In the thin film transistor array element of this embodiment, as shown in FIG. 5, the source electrode 7a and the drain electrode 7b are formed so as to be aligned in the scanning line direction with respect to the gate electrode 1 protruding from the gate wiring which becomes the scanning line. The tip portion of the gate electrode 1, that is, the end portion of the gate electrode pattern extending from the source electrode 7a to the drain electrode 7b is located inside the source electrode 7a and the drain electrode 7b, and the width W1 of the semiconductor layer 3 is
The width W2 of the source electrode 7a and the width W of the drain electrode 7b
It is narrower than 3 and the difference is 4 μm or more.

Also in this thin film transistor array element, an operation test was conducted in the same manner as in the first embodiment, and as a result, the off characteristics of the thin film transistor were almost the same as those in the first, second and third embodiments. Similar results are obtained, and the change with time of the OFF characteristics is suppressed. Further, by adopting the configuration as in the fourth embodiment, the first
Of the gate electrode 1 in comparison with the first embodiment and the third embodiment.
The area occupied by the pixel electrode 6 can be increased, and the aperture ratio can be improved. Further, with such a configuration, the gate electrode 1
The area where the drain electrode 7b and the drain electrode 7b overlap in a plane is reduced.
That is, the parasitic capacitance (Cgd) between the gate electrode 1 and the drain electrode 7b is reduced. Therefore, the DC component in the layer of the liquid crystal 10 of the TFT-LCD can be reduced, the burning phenomenon and the flicker characteristics can be improved, and the reliability can be improved.

A thin film transistor array element according to a fifth embodiment of the present invention will be described with reference to FIG. That is, in this thin film transistor array element, the pattern end of the gate electrode 1 along the source electrode 7a of the thin film transistor along the drain electrode 7b is located inside the drain electrode 7b, and the width W1 of the semiconductor layer 3 is the width of the drain electrode 7a. W3
It is narrower than that of the above, and the difference is 4 μm or more. Also in this thin film transistor array element, an operation test was conducted in the same manner as in the first embodiment, and as a result, the off characteristics of the thin film transistor were almost the same as those in the first to fourth embodiments. , The change in off characteristics with time is suppressed.

Further, even in such a structure, the brightness and reliability of the TFT-LCD can be improved as in the fourth embodiment. Therefore, in any of the above-described embodiments, a thin film transistor array element having high reliability and excellent performance capable of reducing deterioration of off characteristics under drive (voltage) stress, which is an important issue in reliability of a-Si TFT, is provided. be able to.

The method of making the second to fifth embodiments is the same as that of the first embodiment. Also the third
In the example (FIG. 4) and the fifth example (FIG. 6), the width W1 of the semiconductor layer 3 is smaller than the width W3 of the drain electrode 7b, but the width W1 of the semiconductor layer 3 is the width W2 of the source electrode 7a. Similar results can be obtained with a narrower configuration.

[0026]

According to the thin film transistor array element of the first aspect, the width of the semiconductor layer in the path of the current flowing from the source electrode of the thin film transistor to the drain electrode through the semiconductor layer is at least one of the widths of the source electrode and the drain electrode. Since it is narrower than one of them, the potential in the vicinity of the alignment film on the channel of the thin film transistor is less likely to be affected by the potential of the counter electrode and is controlled by the potentials of the source electrode and the drain electrode. As a result, the potential near the alignment film is stabilized, and a-
Induction of electrons in the upper layer portion of the Si semiconductor can be suppressed. Therefore, it is possible to reduce deterioration of the off-characteristics of the thin film transistor caused by driving for a long time, and it is possible to maintain the image quality.

According to the thin film transistor array element of claim 2, the difference between at least one of the widths of the source electrode and the drain electrode and the width of the semiconductor layer of the thin film transistor is set to 4 μm or more. It has the same effect as 1. According to the thin film transistor array element of claim 3, the source electrode and the drain electrode are formed so as to line up in the scanning line direction with respect to the gate electrode protruding from the scanning line, and the tip portion of the gate electrode is formed. Since it is located inside at least one of the source electrode and the drain electrode, the area of the gate electrode can be further reduced without changing the on-current magnitude of the thin film transistor, in addition to the function of claim 1, and thus the gate electrode to the drain electrode. The parasitic capacitance between them becomes small, the DC applied component to the liquid crystal layer is reduced, and the potential drop of the pixel electrode can be suppressed. Therefore, it is possible to prevent the deterioration of reliability and the occurrence of the burning phenomenon, and it is possible to improve the brightness of the screen with the improvement of the aperture ratio, that is, the ratio of the area displayed by the pixel electrodes to the area of the entire screen. Achieves excellent performance with reliability.

[Brief description of drawings]

FIG. 1 shows a structure of a thin film transistor array element according to a first embodiment of the present invention, (a) is a sectional view and (b) is a plan view.

FIG. 2 is a characteristic diagram showing changes with time of Id-Vg characteristics showing switching performance of thin film transistors in the TFT-LCD.

FIG. 3 is a plan view of a thin film transistor array element according to a second embodiment.

FIG. 4 is a plan view of a thin film transistor array element according to a third embodiment.

FIG. 5 is a plan view of a thin film transistor array element according to a fourth embodiment.

FIG. 6 is a plan view of a thin film transistor array element according to a fifth embodiment.

FIG. 7 is a process drawing of a thin film transistor array element of each example of the present invention.

FIG. 8 is a waveform diagram of an applied signal when driving a TFT-LCD.

FIG. 9 shows a structure of a conventional TFT-LCD, (a)
Is a cross-sectional view and (b) is a plan view.

FIG. 10 is a characteristic diagram showing changes with time of Id-Vg characteristics of the thin film transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 gate electrode 2 1st insulating film 3 semiconductor layer 4 2nd insulating film 5 P dope semiconductor layer 6 pixel electrode 7a source electrode 7b drain electrode 8 3rd insulating film 9a, 9b alignment film 10 liquid crystal 11 counter electrode 12a, 12b insulating substrate

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[Procedure amendment]

[Submission date] October 12, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

Currently, such LCD a-Si TFTs are used.
The structure which is widely put into practical use is a so-called inverted stagger type structure in which a gate electrode is arranged in a lower layer. Among these, the self-aligned reverse stagger structure
The a-Si TFT has a protective insulating film pattern on the channel part.
Since the back surface of the substrate is exposed and formed, the TF
It has the advantage that the size of T can be reduced.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

A thin film transistor array element according to a fifth embodiment of the present invention will be described with reference to FIG. That is, in this thin film transistor array element, the pattern end portion of the gate electrode 1 along the source electrode 7a to the drain electrode 7b of the thin film transistor is located inside the drain electrode 7b , and the width W1 of the semiconductor layer 3 is the width of the drain electrode 7b . W3
It is narrower than that of the above, and the difference is 4 μm or more. Also in this thin film transistor array element, an operation test was conducted in the same manner as in the first embodiment, and as a result, the off characteristics of the thin film transistor were almost the same as those in the first to fourth embodiments. , The change in off characteristics with time is suppressed.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

The method of making the second to fourth embodiments is the same as that of the first embodiment. Also the third
In the example (FIG. 4) and the fifth example (FIG. 6), the width W1 of the semiconductor layer 3 is smaller than the width W3 of the drain electrode 7b, but the width W1 of the semiconductor layer 3 is the width W2 of the source electrode 7a. Similar results can be obtained with a narrower configuration.

Claims (3)

[Claims] 1. An insulating substrate having signal lines and scanning lines arranged in a matrix on one main surface, and pixel electrodes formed corresponding to respective intersections of the signal lines and scanning lines of the insulating substrate. A self-aligned inverted stagger structure in which a protective insulating film pattern of a channel portion is formed by performing exposure from another surface different from one main surface of the insulating substrate using a gate electrode as a mask, A thin film transistor provided between the signal line and the scanning line, wherein the width of the semiconductor layer in a path of a current flowing from the source electrode of the thin film transistor to the drain electrode through the semiconductor layer is the source electrode and the drain. A thin film transistor array element characterized by being narrower than at least one of the widths of electrodes. 2. The thin film transistor array element according to claim 1, wherein a difference between at least one of the widths of the source electrode and the drain electrode and the width of the semiconductor layer of the thin film transistor is 4 μm or more. 3. A source electrode and a drain electrode are formed so as to be aligned in the direction of the scanning line with respect to a gate electrode protruding from the scanning line, and the tip of the gate electrode is formed of the source electrode and the drain electrode. The thin film transistor array element according to claim 1, wherein the thin film transistor array element is located inside at least one side.