JPH0832431A - Signal switch - Google Patents

Abstract

PURPOSE:To simplify the configuration and to save power consumption by eliminating the need for separate production of a negative voltage impressed to a gate terminal in the signal changeover device employing a semiconductor element such as a field effect transistor(TR) (FET). CONSTITUTION:A DC voltage impression terminal 10 is provided to a drain side of a FET 3 and a positive voltage (e.g. 3V) below a reverse breakdown voltage of a Schottky junction is impressed to the terminal 10. When a high frequency signal input terminal 1 and a high frequency signal output terminal 2 are conductive, a voltage of 3V is applied to a gate terminal G of a FET 3 from a control signal input terminal 4 to make a width of a depletion layer narrow. On the other hand, when the high frequency signal input terminal 1 and the high frequency signal output terminal 2 are nonconductive, a voltage of OV is impressed to the gate terminal G of the FET 3 from the control signal input terminal 4 to make a width of a depletion layer wider so as to increase a channel resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal switching device used for switching passing or blocking of a signal or changing a signal connection path in the UHF band, the microwave band and the millimeter wave band, and more particularly, FET (field ef) as a switching element
rect transistor).

[0002]

2. Description of the Related Art FIG. 6 is a basic configuration diagram of a conventional single-pole single-throw switching device (SPST switching device) using an FET as a switching element. Reference numeral 1 is a high-frequency signal input end, and 2 is a high-frequency signal output end. 3 is a FET and 4 is a control signal input terminal. FET
The gate terminal G of 3 is high-frequency short-circuited through a capacitor C _G, between the connection point of the capacitor C _G and the control signal input terminal 4, an inductor L for RF blocking
_G is connected. The drain terminal D and the source terminal S have DC blocking capacitors C _D and C _S , respectively.
Is connected.

The switching operation of this SPST switch is performed by FET
It is realized by controlling the channel resistance between the drain terminal D and the source terminal S of No. 3 by the control signal guided to the gate terminal G. This control signal is conventionally the FE
Negative voltage (DC voltage) of a level that T3 can accept and 0
V was used selectively. That is, when the control signal is a negative voltage, the depletion layer immediately below the gate terminal G expands and the channel resistance increases, so that the drain terminal D and the source terminal S are cut off. On the other hand, when the control signal is 0V, the channel resistance becomes small, so that the drain terminal D and the source terminal S are electrically connected and the high-frequency signal is in a passing state.

FIG. 7 shows a conventional single-pole double-throw switch (S
FIG. 3 is a basic configuration diagram of a PDT switch), showing an example in which two sets of the SPST switch are arranged and the high frequency signals guided to the respective input terminals are switched and output at a predetermined timing. This SPDT switch includes a first FET 3A,
The second FET 3B and the second FET 3B are arranged as shown in the drawing, and their source terminals S are connected to each other to form a common high-frequency signal output terminal 2. Further, high-frequency signal input terminals 1A and 1B are arranged at the respective drain terminals D via capacitors C _D , and
The respective gate terminals G are short-circuited in a high frequency manner via the capacitor C _G , and the control signal input terminals 4A, 4A are connected to the connection point of the capacitors C _G via the high frequency blocking inductor L _G.
4B is arranged.

The switching operation of the SPDT switch is realized by alternately applying 0V and the negative voltage to the gate terminals G of the first FET 3A and the second FET. For example, 0 V is applied to the gate terminal G of the first FET 3A and the second F
When a negative voltage is applied to the gate terminal G of ET3B, the channel resistance between the drain terminal D and the source terminal S of the first FET 3A is small, and conversely, the channel resistance of the second FET 3B is large according to the potential difference. As a result, the high frequency signal is guided from the high frequency input end 1A to the high frequency output end 2,
The high frequency signal at the other high frequency input terminal 1B is cut off.

[0006]

As described above, the FET
In the conventional SPST switcher and SPDT switcher using such a semiconductor element, a negative voltage is essential as a control signal. However, in this type of high frequency application, it is usual to use a positive polarity voltage of a predetermined level as the power source for other active circuits, so it is necessary to provide a dedicated power supply circuit separately in order to generate the negative polarity voltage. was there. In particular, when the SPST switcher or SPDT switcher is driven by a battery, the power consumption of the power supply circuit, the switching delay time, and the like become problems, and the circuit configuration becomes complicated, so that the size and cost are reduced. However, there was a certain limit, and improvement was desired. In view of such problems, it is an object of the present invention to provide a signal switcher that does not need to generate a voltage having a polarity different from the existing voltage.

[0007]

[Means for Solving the Problems] First to achieve the above object
A signal switcher of the invention is a signal switcher for selectively applying a binary DC voltage to a gate terminal of a semiconductor element to connect or disconnect between input and output terminals, wherein the input terminal or the output terminal of the semiconductor element is The first DC voltage having a predetermined level is applied, and the second DC voltage having the same polarity and the same level as the first DC voltage and the third DC voltage having the zero level are selectively applied to the gate terminal. It is characterized by being configured.

In the signal switcher of the second invention, the voltage levels of the gate terminals of the first and second semiconductor elements, whose output terminals are connected to each other, are changed so that the respective input / output terminals are alternately conducted, and the semiconductors of the respective semiconductors are electrically connected. In a signal switcher for selectively guiding a high frequency signal guided to an input terminal of an element to the output terminal, a first direct current voltage of a predetermined level is applied to the output terminal and the first direct current is applied to each gate terminal. The second DC voltage having the same polarity and the same level as the voltage is alternately applied.

The signal switch of the third invention is a signal switch for selectively applying a binary DC voltage to the gate terminal of a semiconductor element to connect or disconnect between the input and output terminals. An impedance switching circuit is connected to the terminal and the output terminal so that the impedance at the time of conduction is higher than the characteristic impedance of the input terminal and the output terminal and the impedance at the time of interruption matches the characteristic impedance, and a predetermined level is provided at the connection point. First of
Is applied to the gate terminal, a second DC voltage having the same polarity and the same level as the first DC voltage is applied to the gate terminal, and the same polarity and the same level as the first DC voltage is applied to the gate terminal. Second DC voltage and zero level third
The direct current voltage is selectively applied.

In the signal switch of the fourth aspect of the present invention, the gate terminals of the first and second semiconductor elements whose output terminals are conductively connected to each other are changed so that the respective input / output terminals are alternately conducted, and the semiconductor elements of the respective semiconductor elements are connected. In a signal switcher that selectively guides a high-frequency signal guided to an input terminal to the output terminal, the input terminal of each semiconductor element has a conduction impedance higher than the characteristic impedance of the input terminal, and a disconnection An impedance switching circuit whose impedance matches the characteristic impedance is connected, and a first DC voltage of a predetermined level is applied to the connection point and the output terminal, and each gate terminal has the same polarity as the first DC voltage. Further, it is characterized in that the second DC voltage of the same level is alternately applied.

The impedance switching circuit used in the signal switching device of the third or fourth invention includes a semiconductor element whose input terminal is conductively connected to the connection point and whose output terminal is grounded via a resistor. When the second DC voltage having the same polarity and the same level as the first DC voltage is applied to the gate terminal of the semiconductor element, the impedance at the connection point becomes larger than the characteristic impedance,
The impedance at the connection point is matched with the characteristic impedance when a zero-level third DC voltage is applied to the gate terminal.

[0012]

In the signal switch of the first aspect of the invention, the first direct current voltage of a predetermined level is applied to the input terminal or the output terminal of the semiconductor element, for example, the positive polarity 3V which is often used as the power source voltage of other power-saving active elements. Apply voltage. In this state, if the second DC voltage (3V above) having the same polarity and the same level as the first DC voltage is applied to the gate terminal, the potential difference between the gate terminal and the input / output terminal disappears, and the channel depletion layer is removed. Since it becomes smaller, the input and output terminals become conductive. As a result, the high frequency signal at the input terminal is guided to the output terminal. On the other hand, a zero level third DC voltage (0V) is applied to the gate terminal.
Is applied, the gate terminal becomes relatively lower than the input / output terminal by 3V. Therefore, the depletion layer of the channel expands, and the semiconductor element is cut off.

In the signal switch of the second invention, for example, a positive voltage of 3 V is applied to the output terminals of the first and second semiconductor elements which are conductively connected to each other, and the gate terminals described above are also used. A positive voltage of 3 V is applied alternately. At this time, the semiconductor element on the side to which the voltage is applied to the gate terminal becomes conductive, and the high frequency signal at the input terminal is guided to the output terminal. On the other hand, in the semiconductor element on the side to which the voltage is not applied to the gate terminal, the gate terminal becomes 0V, so that the voltage becomes 3V lower than the input / output terminal, the depletion layer expands, and the input / output terminals are interrupted.

In the signal switch of the third invention, an impedance switching circuit is connected to each of the input terminal and the output terminal of the semiconductor element, and the first DC voltage is applied to the connection point.
For example, a voltage of 3V is applied. Since this impedance switching circuit makes the impedance at the time of conduction larger than the characteristic impedance at the connection point, the circuit side is in an open state, and there is no influence when passing a high frequency signal. On the other hand, since the value has a value that matches the characteristic impedance when cut off, the terminal resistance is branched and connected to the input terminal or output terminal of the semiconductor element, and reflection of high frequency signals is avoided. The principle of switching between the conductive state and the cutoff state of the semiconductor element is the same as in the case of the first invention.

In the signal switcher of the fourth invention, the first and second signal switchers are provided.
The impedance switching circuit that operates as described above is connected to the input terminal of the semiconductor element, and a first DC voltage, for example, a positive voltage of 3 V is applied to each connection and the output terminal. In this state, when the voltage of 3 V is alternately applied to each gate terminal, the input and output terminals of each semiconductor element are alternately turned on and off like the signal switcher of the second invention. The principle that the terminal resistor is branched and connected to the input terminal at the time of interruption and the connection point of the impedance switching circuit is opened at the time of conduction is similar to that of the signal switcher of the third invention.

[0016]

Embodiments of the present invention will now be described in detail with reference to FIGS. (First Embodiment) FIG. 1 shows an SPS according to a first embodiment of the present invention.
FIG. 7 is a basic configuration diagram of a T-switch, which corresponds to FIG. 6. In order to characterize this embodiment, parts having the same functions as those in FIG. 6 are designated by the same reference numerals.

In this embodiment, the drain terminal D of the FET 3 is
And the DC voltage applying terminal 10 is arranged via the high frequency blocking inductor L _D, and the DC voltage applying terminal 1
For example, a positive DC voltage of 3 V is applied to 0. In this case, because of the Schottky junction between the drain terminal D and the gate terminal G and between the source terminal S and the gate terminal G of the FET 3, the applied DC voltage is a reverse voltage and no current flows. However, when a positive voltage that exceeds the reverse withstand voltage of the Schottky junction is applied, the FET 3 is destroyed, so a voltage within the allowable range is set.

The same voltage (3V) as the positive voltage applied to the DC voltage application terminal 10 is applied to the control signal input terminal 4.
And 0 V are selectively applied. When 3V is applied,
Since there is no potential difference between the drain terminal D and the gate terminal G, and the depletion layer of the channel is extremely small, the drain terminal D
And the source terminal S are brought into conduction. On the other hand, when the voltage is 0V, the gate terminal G is 3V relative to the drain terminal D.
Since the potential becomes low, the depletion layer of the channel expands and the resistance becomes high, so that the drain terminal D and the source terminal S are cut off.

As described above, by selectively using the voltages of 3V and 0V, the SPST switching device in which the conductive state and the cutoff state of the FET 3 are formed can be obtained. Therefore, the negative voltage required in the past is not necessary, and the dedicated power supply circuit can be reduced, which has the effect of reducing power consumption. Further, since the circuit configuration is simplified, there is an effect that it is advantageous in terms of cost.

(Second Embodiment) FIG. 2 is a basic configuration diagram of an SPDT switch according to a second embodiment of the present invention, and corresponds to FIG. In order to characterize this embodiment,
Components having the same functions as those in FIG. 7 are designated by the same reference numerals. In this embodiment, a DC voltage applying terminal 10 is arranged at a common high frequency signal output terminal 2 formed by connecting source terminals S to each other via a high frequency blocking inductor L _D, and, for example, a positive DC voltage is applied. For example, the above-mentioned voltage of 3V is applied. In addition, each control signal input terminal 4A, 4B
, The same voltage (3V) as that of the DC voltage application terminal 10 and a voltage of 0V are alternately applied. For example, the first FET 3A
When 3V is applied to the side of the second FET and 0V is applied to the side of the second FET 3B, the channel resistance on the side of the first FET 3A is small and the second FE
The channel resistance on the T3B side becomes very large. As a result, the first FET 3A is turned on and the second FET 3B is turned off, so that only the high frequency signal of the high frequency input terminal 1A is guided to the high frequency output terminal 2. When the voltage level of the control signal is reversed, the first FET 3A is cut off and the second FET 3B is cut off.
Becomes conductive, and only the high frequency signal at the high frequency input end 1B is guided to the high frequency output end 2. Thus, 3V and 0V
It is possible to obtain an SPDT switcher capable of switching signals only with the voltage of. Therefore, the negative voltage required in the past is not necessary, and the dedicated power supply circuit can be reduced, which has the effect of reducing power consumption. Further, since the circuit configuration is simplified, there is an effect that it is advantageous in terms of cost.

(Third Embodiment) FIG. 3 is a basic configuration diagram of the third embodiment of the present invention, in which the high frequency signal input / output terminals 1 and 2 are in a matched state even when the FET 3 is cut off.
An example of a switch is shown. In the present embodiment, in the configuration of FIG. 1, the DC voltage applying terminal 10 is arranged at the drain terminal D and the source terminal S of the FET 3 via the high frequency blocking inductors L _D and L _S , and further, the drain terminal D side and the source. Terminal S
Impedance switching circuits 6 and 7 are connected to the respective sides.

The impedance switching circuits 6 and 7 have, for example, high-frequency signal input / output terminals 1 and 2 whose impedance when conducting is high.
The impedance is larger than the characteristic impedance Zo in Fig. 1 and the impedance at the time of interruption matches the characteristic impedance Zo. That is, the FETs 60 and 70
The drain terminal D of the FET 3 is connected to the drain terminal D and the source terminal S of the FET 3, and the source terminal S thereof is grounded via the resistor R _S. Further, each gate terminal G is short-circuited by a capacitor C _{G in a} high frequency manner, and control signal input terminals 61, 71 are arranged at a connection point of the capacitor C _G via an inductor L _G. In the absorption type SPST switch having the above structure, the relationship between the channel resistance of the FET 3 and the DC voltage applied to the control signal input terminal 4 and the zero level voltage is the same as that of the SPST switch of the first embodiment.

Hereinafter, even if the switching operation is cut off, the high frequency
The reason why the signal input / output terminals 1 and 2 are in the matched state is the drain
The impedance switching circuit 6 on the terminal D side is described as an example.
I do. As shown, the source terminal S of the FET 60 is
Bowl R_SGrounded via the channel resistance of the FET60
Reduced control signal, that is, applied to DC voltage application terminal 10.
The DC voltage (for example, 3V) to be applied to the control signal input terminal 6
When applied to 1, the drain terminal D side of FET3 is FE
Channel resistance of T60 and resistor R_S A series circuit consisting of
It is equivalent to the case of branch connection. FET3 is cut off
When the channel resistance is high, the branch connection circuit
Since impedance can be regarded as a terminating resistance, this impedance
Impedance at the high-frequency signal input / output terminals 1 and 2
If it is set equal to Zo, it will be consistent even when shut off.
Is maintained.

On the other hand, when the FET 3 is conductive, a branch connection circuit is opened by applying a control signal for increasing the channel resistance of the FET 60 of the impedance switching circuit 6, that is, a voltage of 0V, to the control signal input terminal 61. Regarded,
Does not affect the passage of high frequency signals. The above operation is exactly the same in the case of the impedance switching circuit 7 on the source terminal S side.

As described above, the impedance can be switched by selectively using the voltages of 3V and 0V. Therefore, by adjusting the impedance switching timing to the conduction / interruption switching timing of the FET 3, the absorption type SPST can be driven only by the positive DC voltage and the zero level voltage, and the same effect as the first embodiment. Is obtained.

(Fourth Embodiment) FIG. 4 is a basic configuration diagram of a fourth embodiment of the present invention, in which the first FET 3A or the second F is formed.
Each high-frequency signal input terminal 1 even when ET3B is in the cutoff state
An example of an absorption type SPDT switch in which A and 1B are in a matched state is shown. In this embodiment, in the configuration of FIG.
A DC voltage applying terminal 10 is connected to the drain terminal D and the source terminal S of A and 3B via high frequency blocking inductors L _D and L _S.
And a positive polarity DC voltage, for example, a voltage of 3 V is applied thereto, and the impedance switching circuits 6 and 7 described in the third embodiment are connected to the drain terminals D side of the FETs 3A and 3B, respectively. It is a thing. Each FET3A,
The matching state of the high frequency signal input terminals 1A and 1B when 3B is cut off is realized by the effect of the branch connection circuit equivalent to the impedance switching circuits 6 and 7, as described in the third embodiment. After all, this absorption type SPDT switching device can also drive the absorption type SPDT switching device by only the positive DC voltage and the zero level voltage, and the same effect as the second embodiment can be obtained.

(Fifth Embodiment) FIG. 5 is a basic configuration diagram of a fifth embodiment of the present invention, showing an example of a single-pole / multi-throw switch (SPMT switch) which is an application example of the above. In this figure,
Components having the same functions as those in FIGS. 1 to 4 are designated by the same reference numerals.

In this embodiment, each FET 5A-5M
Capacitor C for blocking DC at each drain terminal D of_DThrough
Then, the individual high-frequency signal input terminals 51A to 51M are arranged.
At the same time, for blocking DC from the common connection point of each source terminal S
Capacitor C_SVia the common high-frequency signal output end 2
In addition, an inductor for high frequency blocking is placed at the common connection point.
Kuta L_S The DC voltage application terminal 10 is arranged via
It The DC voltage application terminal 10 has a DC voltage of, for example, 3V.
Apply voltage. Also, the gate end of each FET 5A-5M
Child G is capacitor C_GDue to high frequency short circuit
And these capacitors C_GAt each connection point of
L_GControl signal input terminals 54A to 54M are arranged through
3V, which is the same as the voltage applied to the DC voltage application terminal 10.
And a voltage of 0 V is selectively applied.

In the SPMT switch having the above structure, each F
Channel resistance of ET5A to 5M and control signal input terminal 54A
The relationship with the voltage of 3V and 0V applied to
This is similar to the SPST switch of the first embodiment, for example, the first
When the FET 5A of is in the conductive state, the high frequency signal input terminal 5
Only the high frequency signal of 1A is guided to the high frequency signal output terminal 2,
All the other high-frequency signal input terminals 51B to 51M and the high-frequency signal output terminal 2 are in the cutoff state. As described above, the SPMT switch of this embodiment can also be driven only by the positive DC voltage and the zero level voltage, and the same effect as each embodiment can be obtained.

In each of the above embodiments, inductors L _D , L _S , and L _G are used as high-frequency blocking elements. Instead of this, characteristic impedance at the high-frequency signal input / output terminal (usually 50 ohms) is used. ), A resistor having an impedance sufficiently larger than) may be employed. Further, according to the present invention, since the potential difference between the drain terminal D or the source terminal S and the gate terminal G may be formed only by the DC voltage of the same polarity and the zero level voltage, the voltage applied to the DC voltage applying terminal 10 Is not limited to the positive DC voltage, and the polarity can be changed according to the type of the channel of the FET.

[0031]

As is apparent from the above description, according to the signal switcher of the present invention, the potential difference between the input / output terminal and the gate terminal of the semiconductor element can be determined as the DC voltage of the same polarity and the zero level voltage. Since it can be formed only by itself, there is an effect that a power supply circuit for separately generating a negative DC voltage as in the related art is unnecessary. This simplifies the circuit configuration,
Further, there is an advantage that the power consumption becomes almost zero. In addition, as a control signal for the gate terminal, TTL (transistor transisto)
If a logic signal such as r logic) is directly applied and driven, the circuit configuration can be further simplified and the cost can be significantly reduced. Further, there is an advantage that an MMIC (monolithic microwave integrated circuit) or the like can be easily realized.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of an SPST switch according to a first embodiment of the present invention.

FIG. 2 is a basic configuration diagram of an SPDT switch according to a second embodiment of the present invention.

FIG. 3 is a basic configuration diagram of an absorption type SPST switch according to a third embodiment of the present invention.

FIG. 4 is a basic configuration diagram of an absorption type SPDT switch according to a fourth embodiment of the present invention.

FIG. 5 is a basic configuration diagram of an SPMT switch according to a fifth embodiment of the present invention.

FIG. 6 is a basic configuration diagram of a conventional SPST switch.

FIG. 7 is a basic configuration diagram of a conventional SPDT switch.

[Explanation of symbols]

 1 High frequency signal input terminal 2 High frequency signal output terminal 3,3A, 3B, 5A to 5M FET 4,4A, 4B, 54A to 54M Control signal input terminal 6,7 Impedance switching circuit 10 DC voltage application terminal

Claims (5)

[Claims] 1. A signal switcher for selectively applying a binary voltage DC voltage to a gate terminal of a semiconductor element to connect or disconnect between its input and output terminals, wherein a predetermined voltage is applied to an input terminal or an output terminal of the semiconductor element. A configuration in which a first DC voltage having a level is applied, and a second DC voltage having the same polarity and the same level as the first DC voltage and a third DC voltage having a zero level are selectively applied to the gate terminal. The signal switching device characterized in that 2. The voltage levels of the gate terminals of the first and second semiconductor elements, whose output terminals are connected to each other, are changed so that the respective input / output terminals are electrically connected alternately and led to the input terminals of the respective semiconductor elements. In a signal switcher for selectively guiding a high-frequency signal to the output terminal, a first DC voltage of a predetermined level is applied to the output terminal, and each gate terminal has the same polarity and the same level as the first DC voltage. 2. The signal switcher having a configuration in which the second DC voltage is alternately applied. 3. A signal switcher for selectively applying a binary voltage DC voltage to a gate terminal of a semiconductor element to connect or disconnect between its input and output terminals, wherein an input terminal and an output terminal of the semiconductor element are: An impedance switching circuit is connected so that the impedance when conducting is higher than the characteristic impedance of the input terminal and the output terminal and the impedance when interrupting matches the characteristic impedance, and a first DC voltage of a predetermined level is connected to the connection point. And a second DC voltage having the same polarity and level as the first DC voltage is applied to the gate terminal, and a second DC voltage having the same polarity and level as the first DC voltage is applied to the gate terminal. And a third level DC voltage of zero level are selectively applied. 4. The voltage levels of the gate terminals of the first and second semiconductor elements, whose output terminals are conductively connected to each other, are changed so that the respective input / output terminals are alternately conducted, and the output terminals are electrically connected to the input terminals of the respective semiconductor elements. In a signal switcher that selectively guides a high-frequency signal that has been applied to the output terminal, the input terminal of each semiconductor element has a larger impedance when conducting than the characteristic impedance of the input terminal, and an impedance when shutting off the characteristic. An impedance switching circuit that matches the impedance is connected, and a first DC voltage of a predetermined level is applied to the connection point and the output terminal, and each gate terminal has the same polarity and the same level as the first DC voltage. A signal switcher having a configuration in which a second DC voltage is alternately applied. 5. The impedance switching circuit includes a semiconductor element whose input terminal is conductively connected to the connection point and whose output terminal is grounded via a resistor, and the gate terminal of the semiconductor element includes the first element. When a second DC voltage having the same polarity and the same level as the DC voltage is applied, the impedance at the connection point becomes larger than the characteristic impedance, and a zero level third DC voltage is applied to the gate terminal. The signal switcher according to claim 3, wherein the impedance at the connection point is matched with the characteristic impedance.