JPH0832573A - Frame synchronization protection circuit - Google Patents

Abstract

PURPOSE:To obtain the frame synchronization protection circuit protecting frame synchronization without absence of an external input. CONSTITUTION:A clock counter 3 receives a clock synchronously with a bit stream signal and counts number of clocks. A frame length storage circuit 5 stores number of clocks from the first coincidence between frame synchronizing signals till the 2nd frame length and a reference frame coincidence as a tentative one frame length and a reference frame length. A frame length comparator circuit 6 compares the count value and the reference frame length as to whether or not they match and provides a frame length matching pulse when the both match and provides an output of a frame synchronizing signal comparison result valid flag when the count reaches a value estimated to be a length of a succeeding frame synchronizing signal. A forward/backward protection circuit 7 protects frame synchronization by regarding only the output comparison result of a frame synchronizing signal comparator circuit 1 receiving the frame synchronizing signal comparison result valid flag.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization protection circuit, and more particularly to a frame synchronization protection circuit of a receiver used for digital broadcasting or communication in which transmission contents are framed and multiple types of data are multiplexed and transmitted. .

[0002]

2. Description of the Related Art Conventionally, in digital broadcasting and digital communication, the contents of transmission are formed into a frame that is multiplexed with a frame synchronization signal (frame sync), and the frame is transmitted in units of this frame. In order to accurately receive and demodulate the transmission content from the transmitted frame, it is necessary to detect this frame synchronization signal and determine the frame position. For this reason, a frame synchronization protection circuit is required in the receiving device.

On the other hand, in digital broadcasting or digital communication for transmitting a plurality of types of frames, for example, when a data-compressed video signal and audio signal are formed into one frame and transmitted, the frame length varies depending on the compression mode. Transmit different frames.

For example, in the first transmission mode, as shown in FIG.
As shown in (A), a frame sync 61 is time-division-multiplexed at the head of a multiplexed signal composed of a data signal 64, a video signal 62, an audio signal 63, and data 64.
A 0-byte frame is shown in this frame unit as shown in FIG.
Transmit as shown in.

Further, in the second transmission mode, FIG.
As shown in, a 3000-byte frame having a structure in which a frame sync 65 is time-division-multiplexed at the head of a multiplexed signal composed of a video signal 66 and an audio signal 67 and data 68 compressed in a compression mode different from the above. , The frame unit is transmitted as shown in FIG. The frame syncs 65 and 61 have the same fixed pattern.

As described above, the frame synchronization protection circuit used in the receiver applied to digital broadcasting or digital communication for transmitting a plurality of types of frames has conventionally used a parameter for determining the frame length corresponding to the frame length. It is set from the outside.

[0007]

However, in the conventional frame synchronization protection circuit, a parameter for determining the frame length must be input from the outside every time the frame length of the received signal is different as described above. For example, if a transmission mode different from the transmission mode of the channel being watched until then is received when the channel is switched while receiving digital broadcasting, it is necessary to change and set the parameter for externally determining the frame length. Therefore, there is a problem that the operation is extremely complicated.

The present invention has been made in view of the above points, and an object thereof is to provide a frame synchronization protection circuit capable of performing frame synchronization protection without external input.

[0009]

In order to achieve the above object, the present invention compares a received bit stream signal with a frame sync pattern and outputs a frame sync comparison result, and a frame sync comparison circuit. The input time interval of the first and second frame sync comparison results after resetting among the frame sync comparison results indicating the coincidence output from the frame sync comparison circuit, which receives the comparison result and the clock synchronized with the bit stream signal as an input signal. Is detected as the reference frame length and stored.
It comprises a memory circuit, a frame length comparison circuit, and a front / rear protection circuit.

Here, the frame length comparison circuit compares the counter value of the clock input from the detection / storage circuit with the reference frame length and outputs a frame length matching pulse, and the counter value becomes the reference frame length. Based on this, the frame sync comparison result valid flag is output each time the value expected to be input next time is reached.
In addition, the front / rear protection circuit receives the frame sync comparison result valid flag and the frame sync comparison result as input signals, and determines that only the frame sync comparison result when the frame sync comparison result valid flag is set is valid. The front and rear protection operations are performed and the frame synchronization signal is output.

Further, the detection / storage circuit is provided with an initial match confirmation circuit which outputs an initial match flag when a frame sync comparison result indicating a match is first input after resetting, and a state where the initial match flag is input. The second match confirmation circuit that outputs the second match flag when the frame sync comparison result indicating the first match is input, and the clock synchronized with the bitstream signal is counted, and the frame length match pulse or the first match flag and The counter is reset immediately after the second match flag is output, and the frame length storage circuit that stores the count value of the counter when the second match flag is input as the reference frame length.

[0012]

According to the present invention, the detecting / storing circuit detects the input time intervals of the first and second frame sync comparison results after reset, and stores them as the reference frame length. When the counter value indicating the timing at which the frame sync is expected to be input next in the length comparison circuit is input from the counter, the frame sync comparison result valid flag is output, and the frame sync comparison circuit Since only the frame sync comparison result is valid and the frame protection operation is performed by the front and rear protection circuits, as long as the frame sync is the same, the frame sync is automatically detected even if a transmission signal with a different frame length is received. And can be protected.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to FIGS.
Will be explained together. FIG. 1 shows a block diagram of an embodiment of the present invention. As shown in the figure, in this embodiment, a frame sync comparison circuit 1, a first-time match confirmation circuit 2, a clock counter 3, a second-time match confirmation circuit 4, a frame length storage circuit 5, a frame length comparison circuit 6, and a front / rear direction. It is composed of a protection circuit 7. Of these, the initial match confirmation circuit 2, the clock counter 3, the second match confirmation circuit 4, and the frame length storage circuit 5 constitute the detection / storage circuit.

The frame sync comparison circuit 1 compares the received bit stream signal (received signal) with a known fixed pattern of the frame sync (frame sync pattern), and compares the result (the frame sync comparison result). ) Is output. The initial coincidence confirmation circuit 2 receives this comparison result as an input, and when it confirms that the comparison result coincides after the power-on reset or after the synchronization protection error reset, it sets the initial coincidence flag thereafter.

The second match confirmation circuit 4 receives the frame sync comparison result and the first match flag as inputs, and outputs the second match flag when the frame sync comparison result matches the first time and then the next match. The clock counter 3 receives a clock synchronized with the bit stream signal, counts the number of clocks, and outputs a count value. In addition,
The clock counter 3 is reset by the first match pulse, the second match pulse, and the frame length match pulse.

The frame length storage circuit 5 receives the count value of the clock counter 3 and the second match pulse, and receives the number of clocks from the first match to the second match of the frame sync comparison (that is, the first and second frames after reset). The input time interval of the sync comparison result) is set as a temporary length of one frame and stored as a reference frame length.

The frame length comparison circuit 6 receives the count value of the clock counter 3 and the reference frame length stored in the frame length storage circuit 5, and compares the count value with the reference frame length to determine whether they match. When they match, a frame length matching pulse is output. In addition, the frame length comparison circuit 6
Outputs the frame sync comparison result valid flag when the input count value from the clock counter 3 reaches a value at which the frame sync is expected to come next.

The front / rear protection circuit 7 receives the frame sync comparison result from the frame sync comparison circuit 1 and the frame sync comparison result valid flag from the frame length comparison circuit 6 as input signals, and protects the frame sync front / rear. Then, a frame synchronization signal is output, or when a frame synchronization protection error occurs, a protection error reset signal is output to reset the first match confirmation circuit 2 and the second match confirmation circuit 4.

Next, the operation of this embodiment will be described with reference to FIGS. 2 is a flowchart for explaining the operation from resetting to frame sync comparison initial matching in this embodiment, FIG. 3 is a flowchart for explaining the operation from initial matching to second matching in this embodiment, and FIG. 9 is a flowchart for explaining the operation from the second matching to frame synchronization protection and frame sync output.

FIG. 5 is a timing chart from the reset to the third match in this embodiment. FIG. 6 is a diagram showing each example of a frame structure and a transmission signal. In addition,
In this specification, “reset” refers to a power-on reset and a reset upon protection synchronization error.

First, a power-on reset is activated by turning on the power of the receiver at the time shown in FIG. 5 (step 21 in FIG. 2). By this power-on reset, the frame sync comparison circuit 1 compares the received signal with the frame sync pattern every one clock (step 22 in FIG. 2),
When they match, a high level (H level) pulse is output as the frame sync comparison result.

Therefore, if the frame sync in the received signal is input as shown in FIG. 5A after the power-on reset, the frame sync a1 which is first received after the power-on reset is input. At that time, the frame sync comparison circuit 1 outputs an H level pulse (frame sync comparison result) b1 shown in FIG. 5B.

Upon receipt of this pulse b1, the initial match confirmation circuit 2 judges that it is the initial match and outputs the initial match flag at a high level as shown in FIG. 5C (FIGS. 2 and 3).
Step 23, time in FIG. 5). At this time, the clock counter 3 is reset by the first match pulse output from the first match confirmation circuit 2.

Even after the initial match flag goes high, the frame sync comparison circuit 1 continues the operation of comparing the received signal with the frame sync pattern (step 31 in FIG. 3), and after the power-on reset, FIG. When the second frame sync indicated by a2 is input to (A), an H level pulse is output at a time as indicated by b2 in FIG.

The second match confirmation circuit 4 receives the H-level pulse b2 from the frame sync comparison circuit 1 in the state where the H-level first match flag is input from the first match confirmation circuit 2. As shown in FIG. 5D, the second match flag is set to H level and output to the frame length storage circuit 5 (step 3 in FIGS. 3 and 4).
2).

The frame length storage circuit 5 stores the count value of the clock counter 3 at the time when the second H-level match flag is input as the reference frame length (step 41 in FIG. 4). The count value of the clock counter 3 at this time is, as indicated by e in FIG. 5 (E), the count number of the clock until the time after the reset by the first coincidence pulse at the time, and the value corresponding to the time from the time to Shows. This count value e becomes the reference frame length for the front / rear protection circuit 7 to perform the synchronization protection.

The clock counter 3 is reset by the H-level second coincidence pulse output from the second coincidence confirmation circuit 4 immediately after the second coincidence flag becomes high level.

Here, the received signal is one of a plurality of types of frame lengths as in the conventional case, and is, for example, as shown in FIG.
When the signal having the frame structure shown in (A) is normally received as shown in (B), the reference frame length becomes 2000 bytes, and the signal having the frame structure shown in (C) in FIG. When the data is normally received as shown in D), the reference frame length is 3000 bytes.

The frame lengths shown in FIGS. 6A and 6C are different depending on the transmission content, but the two are not mixed and inputted, but either one is continuously inputted. This is the same as the conventional one. The frame syncs 61 and 65 have the same fixed pattern, which is the same as the frame sync pattern input to the frame sync comparison circuit 1.

After the second match, processing is performed according to the flowchart of FIG. That is, the frame length comparison circuit 6
Is a value that is predicted to arrive at the next frame sync based on the reference frame length input from the frame length storage circuit 5, and compares the predicted value with the count value counted by the clock counter 3. (Step 4
2) If they match, the H level pulse is output as a frame sync comparison result valid flag (step 43).

In the example of FIG. 5, the third frame sync a
At the time corresponding to the time when the third sync pulse b3 is output from the frame sync comparison circuit 1 by the input of 3,
As shown in FIG. 5F, the frame sync comparison result valid flag is output. This frame sync comparison result valid flag is supplied to the front / rear protection circuit 7 and
A frame length matching pulse corresponding thereto is supplied from the frame length comparison circuit 6 to the clock counter 3 to reset it.

The front / rear protection circuit 7 receives the frame sync comparison result from the frame sync comparison circuit 1 (indicated by step 22 in FIG. 4) and the frame sync comparison result valid flag from the frame length comparison circuit 6, The frame sync protection operation is performed assuming that only the frame sync comparison result when the frame sync comparison result valid flag is H level is valid (step 44 in FIG. 4).

That is, the front / rear protection circuit 7 enters the synchronization state when the valid frame sync comparison result satisfies the set number of rear protections, and receives the frame synchronization signal which is protected thereafter. Output in synchronization with the frame sync comparison result and the frame sync comparison result valid flag.

Further, the front / back protection circuit 7 regards the input frame sync comparison result and the frame sync comparison result valid flag as being out of synchronization when it detects that they do not match the set front protection number of times, and protects them. Outputs a reset signal when an error occurs. The first match confirmation circuit 2 and the second match confirmation circuit 4 which have received the reset signal at the time of the protection error,
The data is reset and the confirmation operation is started again.

As described above, according to the present embodiment, the reference frame length indicating the frame length of the received signal is generated and compared with the frame sync comparison result in the front / rear protection circuit 7 using this as a reference. Therefore, it is possible to easily detect and protect the frame sync without inputting the parameter related to the frame length of the received signal from the outside.
Therefore, the parameter input operation can be omitted.

[0036]

As described above, according to the present invention,
Even if a transmission signal with a different frame length is received, the frame sync can be automatically detected and protected, so when applied to digital broadcasting or digital communication that transmits a signal with multiple frame lengths, the frame length One receiver can perform frame synchronization protection operation without externally setting parameters for change.
Even if the frame length changes during reception, it is possible to eliminate the need for an external parameter setting operation for changing the frame length, and the operability can be greatly improved compared to the conventional case.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a flowchart from the reset of FIG. 1 to the frame sync comparison first match.

FIG. 3 is a flowchart from the first match to the second match in FIG.

FIG. 4 is a flowchart from the second matching of FIG. 1 to frame synchronization protection and frame sync output.

5 is a timing chart of each part from the reset of FIG. 1 to the third matching.

FIG. 6 is a diagram showing each example of a frame structure and a structure of a transmission signal.

[Explanation of symbols]

 1 Frame Sync Comparison Circuit 2 First Match Confirmation Circuit 3 Clock Counter 4 Second Match Confirmation Circuit 5 Frame Length Storage Circuit 6 Frame Length Comparison Circuit 7 Front / Back Protection Circuit

Claims (2)

[Claims] 1. A frame sync comparison circuit for comparing a received bit stream signal and a frame sync pattern and outputting a frame sync comparison result, and an input signal for the frame sync comparison result and a clock synchronized with the bit stream signal. Of the frame sync comparison results indicating the coincidence output from the frame sync comparison circuit, the detection and storage circuit that detects and stores the input time intervals of the first and second frame sync comparison results after reset as the reference frame length. And comparing the counter value of the clock input from the detection / storage circuit with the reference frame length to output a frame length coincidence pulse, and the counter value is based on the reference frame length. Frame sync comparison each time the frame sync reaches the expected value A frame length comparison circuit that outputs a result valid flag, and the frame sync comparison result valid flag and the frame sync comparison result as input signals, and only the frame sync comparison result is valid when the frame sync comparison result valid flag is set. And a front / rear protection circuit for performing a frame synchronization front / rear protection operation and outputting a frame synchronization signal. 2. A first match confirmation circuit that outputs a first match flag when a frame sync comparison result indicating the first match is input to the detection / storage circuit, and the first match flag is input. In the state, a second match confirmation circuit that outputs a second match flag when a frame sync comparison result indicating the first match is input, and a clock synchronized with the bitstream signal is counted, and the frame length match pulse is used. Alternatively, a counter that is reset immediately after the first match flag and the second match flag are respectively output, and a frame length that stores the count value of the counter when the second match flag is input as the reference frame length. The frame synchronization protection circuit according to claim 1, further comprising a storage circuit.