JPH0832832A - Sync signal compensation circuit - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a synchronization signal compensation circuit, and an object of the present invention is to compensate a jitter of a synchronization signal supplied from the outside to generate a synchronization signal which does not include the jitter. A match detection circuit 20 performs match detection between an external sync signal, which is a sync signal of a video signal supplied from the outside, and an internal sync signal, which is a sync signal generated internally. The selection circuit 21 selects one of the external synchronization signal and the internal synchronization signal according to the instruction signal. Counter 22
Is reset by the synchronization signal selected by the selection circuit 21, counts clocks, and generates an internal synchronization signal in which jitter is compensated. Selection instruction signal generation circuit 23,
Reference numeral 24 is reset by the match detection signal from the match detection circuit 20 and instructs the selection of the external sync signal when the internal sync signal reaches a predetermined value and otherwise selects the internal sync signal. An instruction signal for instructing is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync signal compensating circuit, and more particularly to a sync signal compensating circuit for compensating a sync signal of a video signal.

In recent years, due to the demand for higher image quality in television, the second generation EDTV aiming at wide aspect ratio (aspect ratio 16: 9) and high image quality while maintaining compatibility with the current NTSC system. (Enhanced television “EDTVII”) is expected as a next-generation television system.

[0003]

2. Description of the Related Art In EDTVII, interlaced scanning is converted into non-interlaced scanning and scanning of 525 scanning lines is performed every 1/60 sec. Therefore, the current NT
When an SC video signal is supplied, the horizontal sync signal separated from this video signal is doubled to generate a double speed horizontal sync signal, and horizontal scanning is performed in synchronization with this double speed horizontal sync signal.

[0004]

When a video signal of interlaced scanning including a large jitter, such as a reproduction signal of a current home video tape recorder, is supplied, the horizontal synchronizing signal of this video signal is doubled. Non-interlaced horizontal scanning is performed using the double speed horizontal synchronizing signal including jitter. In this case, although the horizontal scanning line of one screen is 525 lines, which is twice as large as that of the interlaced scanning, the start position of the horizontal scanning is deviated for each horizontal scanning line due to the large jitter, and the vertical resolution is conventionally reduced. There was a problem that it was worse than the case of non-interlaced scanning.

The present invention has been made in view of the above points,
An object of the present invention is to provide a sync signal compensating circuit which compensates jitter of a sync signal supplied from the outside and generates a sync signal which does not include jitter.

[0006]

According to a first aspect of the present invention, coincidence detection between an external synchronizing signal which is a synchronizing signal of a video signal supplied from the outside and an internal synchronizing signal which is a synchronizing signal generated internally is detected. The coincidence detection circuit that performs the operation, the selection circuit that selects one of the external synchronization signal and the internal synchronization signal according to the instruction signal, and the synchronization signal that is selected by the selection circuit are reset. A counter that generates a compensated internal synchronization signal and a coincidence detection signal from the coincidence detection circuit reset, and when the internal synchronization signal is counted and reaches a predetermined value, an instruction to select the external synchronization signal is issued. And a selection instruction signal generation circuit for generating an instruction signal for instructing selection of the internal synchronization signal.

According to the second aspect of the invention, the predetermined value in the selection instruction signal generating circuit is variable.

According to a third aspect of the invention, the synchronizing signal is a horizontal synchronizing signal.

According to another aspect of the invention, the sync signal is a vertical sync signal.

[0010]

According to the first aspect of the invention, the clock is counted to generate the internal synchronization signal that does not include jitter,
Since the internal synchronization signal is synchronized with the external synchronization signal when the internal synchronization signal and the external synchronization signal do not match a predetermined number of times in succession, it is possible to obtain a synchronization signal that is synchronized with the external synchronization signal and compensates for jitter.

According to the second aspect of the present invention, by making the predetermined value in the selection instruction signal generating circuit variable, the number of times of disagreement for synchronizing the internal synchronizing signal with the external synchronizing signal can be freely changed.

According to the third aspect of the present invention, the horizontal synchronizing signal in which the jitter is compensated can be obtained by using the synchronizing signal as the horizontal synchronizing signal.

According to the fourth aspect of the present invention, the vertical synchronizing signal in which the jitter is compensated can be obtained by using the synchronizing signal as the vertical synchronizing signal.

[0014]

1 shows a block diagram of an embodiment of a synchronizing signal compensating circuit of the present invention. In the figure, a terminal 10 receives a standard video signal of the NTSC system and a horizontal synchronizing signal separated from a reproduction signal of a current home video tape recorder and is supplied to a differentiating circuit 11.

The differentiating circuit 11 has the structure shown in FIG. The horizontal synchronizing signal coming in from the terminal 12 is supplied to the register 13, the horizontal synchronizing signal output from the register 13 as shown in FIG. 3A is branched into two, one is supplied to the register 14, and the other is supplied to the NOR circuit 16. Is supplied to. Register 13,
Reference numeral 14 is driven by a clock having a frequency of 4 fsc (fsc is a color subcarrier frequency).

The output signal of the register 14 is the inverter 15
Is inverted by the NOR circuit 16 to obtain the waveform shown in FIG.
Is supplied to. The NOR circuit 16 generates a differential signal as shown in FIG. 3C in which the falling edge of the horizontal synchronizing signal is detected, and outputs it as an external synchronizing pulse signal from the terminal 17.

Returning to FIG. 1, the external synchronizing pulse signal output from the differentiating circuit 11 is supplied to the coincidence detecting circuit 20 and the selecting circuit 21. The coincidence detection circuit 20 has an H
The internal synchronizing pulse signal output from the counter 22 is supplied, and the coincidence between the external synchronizing pulse signal and the external synchronizing pulse signal is detected. Since both pulse signals are positive polarity pulses, the AND operation is actually performed. The coincidence detection signal obtained here is supplied to the reset terminal of the counting circuit 23, and the counting circuit 23 is reset to zero.

The selecting circuit 21 selects either the external synchronizing pulse signal from the differentiating circuit 11 or the internal synchronizing pulse signal from the H counter 22 according to an instruction signal output from a decoder 24, which will be described later. When the signal is at L level, the internal sync pulse signal is selected, and when it is at H level, the external sync pulse signal is selected. The sync pulse signal selected here is H
It is supplied to the reset terminal of the counter 22.

The H counter 22 is a 910-ary ring counter which is reset to zero by the output of the selection circuit 22 and counts a clock having a frequency of 4 fsc. The H counter 22 generates an internal synchronizing pulse signal and outputs it from the terminal 25.
The coincidence detection circuit 20, the selection circuit 21, and the counting circuit 23 are supplied respectively. The counting circuit 23 is reset to zero by the output of the coincidence detection circuit 20, counts the internal synchronizing pulse signal from the H counter 22, and outputs the count value to the decoder 24.
Supply to. The decoder 24 generates an instruction signal that becomes H level when the count value of the counting circuit 23 becomes equal to the set value set from the terminal 24a, and otherwise becomes L level, and supplies it to the selection circuit 21. H counter 22
When the internal synchronization pulse signal output by the output signal of 1 is synchronized with the external synchronization pulse signal output by the differentiating circuit 20,
When the external synchronizing pulse signal comes in, the count value of the counting circuit 23 is reset by the coincidence detection signal.

Here, when the external sync pulse signal deviates from the internal sync pulse signal shown in FIG. 4 (A) by jitter as shown in FIG. 4 (B) (even when the pulse is lost, it is equivalent to jitter). 4C, since the coincidence detection signal is missing as shown in FIG. 4C, the count value of the counting circuit 23 is counted up by the internal synchronization pulse signal, but when the coincidence detection signal is output again, The count value is reset.

Thus, even if the horizontal synchronizing signal coming from the terminal 10 has a jitter, the frequency from the terminal 25 is 4f.
A double speed horizontal sync signal (internal sync pulse signal), which is obtained by counting the sc clock and compensated for jitter, is output. Therefore, when non-interlaced scanning is performed using the double speed horizontal synchronization signal generated from the horizontal synchronization signal that compensates for jitter, the horizontal scanning start position becomes the same in each horizontal scanning line,
It is possible to prevent deterioration of vertical resolution.

Further, since the decoder 24 can freely change the set value, the number of times that the internal sync pulse signal and the external sync pulse signal do not match continuously is changed to change the internal sync pulse signal to the external sync pulse signal. The timing to synchronize can be changed.

Here, if the external sync pulse signal continuously deviates from the internal sync pulse signal shown in FIG. 5A due to the jitter as shown in FIG. 5B, the coincidence detection signal continues. Therefore, the count value of the counting circuit 23 is counted up by the internal synchronizing pulse signal. As a result, when the count value of the counting circuit 23 becomes 128 as shown in FIG.
As shown in (C), the instruction signal is set to the H level, the H counter 22 is reset by the next external synchronizing pulse signal,
Synchronized. Therefore, when the next external synchronization pulse signal is supplied, the coincidence detection circuit 20 generates a coincidence detection signal and the counting circuit 23 is reset. When the internal sync pulse signal and the external sync pulse signal are continuously out of sync for a long period of time in this way, synchronization is re-established, and thereafter, the internal sync pulse signal that does not include jitter synchronized with the external sync pulse signal. That is, the double speed horizontal synchronizing signal is obtained and supplied from the terminal 25 to the subsequent circuit.

A preset counter is used in place of the counting circuit 23 and the decoder 24, a set value is loaded by a coincidence detection signal, down-counting is performed by an internal synchronizing pulse signal, and when the count value is 0, an instruction signal is issued. May be set to the H level, and is not limited to the above embodiment.

Further, by supplying an external vertical synchronizing signal to the terminal 10 and providing a ring counter for counting 238875 of a clock having a frequency of 4 fsc instead of the H counter 22, a vertical synchronizing signal containing no jitter is output from the terminal 25. It is also possible to do so. Also in this case, the decoder 2
The set value of 4 is selected as an appropriate value.

[0026]

As described above, according to the first aspect of the present invention, the clock is counted to generate the internal synchronization signal that does not include jitter, and the internal synchronization signal and the external synchronization signal are successively output a predetermined number of times. When they do not match, the internal synchronization signal is synchronized with the external synchronization signal, so that it is possible to obtain a synchronization signal that is synchronized with the external synchronization signal and compensates for jitter.

According to the second aspect of the present invention, by making the predetermined value in the selection instruction signal generating circuit variable, the number of times of disagreement for synchronizing the internal synchronizing signal with the external synchronizing signal can be freely changed. According to the third aspect of the invention, the horizontal synchronizing signal in which the jitter is compensated can be obtained by using the synchronizing signal as the horizontal synchronizing signal. Further, according to the invention described in claim 4, it is possible to obtain the vertical synchronizing signal in which the jitter is compensated by using the synchronizing signal as the vertical synchronizing signal, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block diagram of a circuit of the present invention.

FIG. 2 is a block diagram of a differentiating circuit.

FIG. 3 is a signal timing chart of the circuit of FIG.

FIG. 4 is a signal timing chart of the circuit of FIG.

5 is a signal timing chart of the circuit of FIG.

[Explanation of symbols]

 11 Differentiation Circuit 13, 14 Register 15 Inverter 16 NOR Circuit 20 Match Detection Circuit 21 Selection Circuit 22 H Counter 23 Counting Circuit 24 Decoder

Claims (4)

[Claims] 1. A coincidence detection circuit (20) for performing coincidence detection between an external synchronization signal which is a synchronization signal of a video signal supplied from the outside and an internal synchronization signal which is an internally generated synchronization signal.
A selection circuit (21) for selecting one of the external synchronization signal and the internal synchronization signal in accordance with an instruction signal; and resetting by the synchronization signal selected by the selection circuit (21), counting clocks and jittering. A counter (22) that generates an internal synchronization signal that does not include an internal synchronization signal, and is reset by a match detection signal from the match detection circuit (20). When the internal synchronization signal is counted and reaches a predetermined value, an external synchronization signal is selected. And a selection instruction signal generation circuit (23, 24) for generating an instruction signal for instructing the selection of the internal synchronization signal at other times. 2. The selection instruction signal generation circuit (23, 2)
The synchronization signal compensating circuit according to claim 1, wherein the predetermined value in 4) is variable. 3. The sync signal compensating circuit according to claim 1, wherein the sync signal is a horizontal sync signal. 4. The sync signal compensating circuit according to claim 1, wherein the sync signal is a vertical sync signal.