JPH08328902A - Software development supporting device - Google Patents

Abstract

PURPOSE: To designate a label as a break point only by designating the label set to a memory space where a program space and a data space are independent. CONSTITUTION: This device is provided with a keyboard 3 for inputting the address of an instruction to be executed by a target processor 5 having the memory space, in which the program space and the data space are allocated to independent logical spaces and the label for specifying the those spaces while dividing those spaces into the ranges of plural continuous logical addresses, or for inputting the address of data to be accessed while being connected to the target processor 5, break address registers 220 and 221 for holding the inputted address, comparators 230 and 231 for comparing the address held by these registers with the address of the instruction to be executed by the target processor 5 or with the address of the data to be accessed in the case of executing the instruction, and debugging controller 21 for stopping the operation of the target processor 5 when any compared result shows coincidence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a software development support apparatus, and particularly software development suitable when the program space and the data space of the system to be targeted are independent and both labels are set. Regarding the support device.

[0002]

2. Description of the Related Art A computer program is developed on a so-called host computer, but a processor (target processor) that actually runs the program.
Is a separate computer that is essentially independent of the host computer. However, in order to develop a computer program efficiently, put the target processor under the control of the host computer, break the program on the target processor at a predetermined address, and observe the contents of registers and memory at that time. It is necessary to find a program mistake (bug), that is, to debug. In other words, dedicated hardware that observes the state of the target processor, determines the result, and controls it.
(Debugger) is required. Such hardware is an in-circuit emulator (ICE).
It is a software development support device called r).

FIG. 4 is a block diagram showing a configuration example of an in-circuit emulator as a conventional software development supporting device, and FIG. 5 is a general connection state between a host computer incorporating such an in-circuit emulator and a target processor. It is a schematic diagram which shows.

In FIG. 5, reference numeral 1 indicates a host computer, in which a conventional in-circuit emulator (hereinafter referred to as ICE) 2 is installed. Reference number 3
Is a keyboard of the host computer 1 and is used to give various instructions to the host computer 1 itself and to the ICE 2 via the host computer 1.

Reference numeral 4 indicates a target system, and its CPU 5 is a target processor. In the description below, the processor 5 of the target system 4 is referred to as a target processor.

In FIG. 4 showing the internal structure of the conventional ICE 2, reference numeral PAB indicates a program address bus and DAB indicates a data address bus. These are the program bus of the target processor 5 via an interface (not shown). , Are connected to the data bus respectively.

Reference numeral 21 indicates a debug controller, which controls the entire ICE 2 and the target processor 5. Reference numeral 22 indicates a break address register, which is provided with an address for specifying a break point, that is, a break address, from the debug controller 21 and holds the break address.

Reference numeral 23 indicates a comparator, which is provided with the break address held by the break address register 22, the program address on the program address bus PAB, and the data address on the data address bus DAB. To be The comparator 23 is provided when the break address given from the break address register 22 and the program address given from the program address bus PAB match, or the break address given from the break address register 22 and the data address bus DA.
A predetermined match signal S is output when the data address given from B matches.

Reference numeral 24 indicates a break counter, which counts the number of times the above-mentioned coincidence signal S is output from the comparator 23. The count number of the break counter 24 can be set by the debug controller 21, and when the count value of the break counter 24 reaches the value set by the debug controller 21, a predetermined signal (break signal B)
Is output to the debug controller 21.

Reference numeral 25 indicates a PC controller, which receives a P signal from the target processor 5 when a predetermined signal (control signal C) is given from the debug controller 21.
C, that is, the program counter is controlled to perform various controls including starting and stopping of the target processor 5.

Therefore, the debug controller 21 is operated by the operator, for example, on the keyboard 3 of the host computer 1.
When a program address or data address that is operated is input, it is held in the break address register 22, and then the PC controller 25 is controlled to start the target processor 5. Target processor 5
Outputs the program address value set in its own PC after startup, that is, the PC value, to the program address bus inside the target system 4, and according to it (usually "1" is incremented each time one instruction is executed) , Executes each instruction of the program, and outputs the data address of the data necessary for the execution or the data address storing the execution result to the data address bus inside the target system 4.

The program address and data address output to the program address bus and the data address bus inside the target system 4 are also given to the program address bus PAB and the data address bus DAB of the ICE 2 through an interface (not shown). Therefore, they are input to the comparator 23.

In the comparator 23, the program address bus PA
B, The address on the data address bus DAB is constantly compared with the break address given to the break address register 22 from the debug controller 21 first, and if they match, the match signal S is sent to the break counter 24. Output to.

On the other hand, since the break controller 24 is preset with a set value by the debug controller 21,
When the number of times the coincidence signal S is output from the comparator 23 reaches the set value, the break signal B is output to the debug controller 21. In response to this, the debug controller 21 outputs the control signal C to the PC controller 25, and the PC controller 25 stops the PC of the target processor 5 of the target system 4. When the PC stops, the target processor 5 stops executing the program.

In this way, when the target processor 5 stops the execution of the program, the contents of the register and memory in the target system 4 are read by the host computer 1 and displayed on its display screen, so that the operator The state is checked visually or after being stored in an appropriate storage means to check whether the program of the target processor 5 functions as designed.

By the way, in a memory space of a computer (processor), a space for programs (individual addresses constituting individual programs are designated by individual addresses),
In some cases, the space for data (individual data is specified by each address) is allocated as a separate and independent space. In this case, since the physical address unique to the memory is uniquely assigned, it is necessary to distinguish the address of the program space and the address of the data space and convert them into physical addresses.

Further, the program space and the data space are each divided into a certain range of addresses (in the case of the program space, for example, one-divided processing, a subroutine, etc., and in the case of the data space, for example, a table unit to be incorporated as data), and each data is divided. There is a method of giving a label to a range. In an in-circuit emulator for a processor having such a memory space, each time the operator specifies a breakpoint with a label, the address of the specified label and whether it is the program space or the data space is specified. Will need to be specified,
The operation becomes very complicated.

[0018]

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and when a label is set in a memory space in which a program space and a data space are independent, the label The purpose is to provide a software development support device that can specify a label as a breakpoint only by specifying it.

It is another object of the present invention to provide a software development support device capable of designating whether to read data from the address or write to the address when the data address is designated as the breakpoint.

[0020]

A software development support apparatus according to the present invention comprises a program space composed of logical addresses in which respective instructions of a program to be executed are arranged, data used in executing the program, The data space configured by the logical address where the execution result data is allocated is allocated to an independent logical space, and the program space and the data space are divided into multiple continuous logical address ranges to identify each Input means connected to a processor having a memory space in which a label is set, for inputting an address of an instruction to be executed by the processor or an address of data to be accessed, and address holding means for holding the address input by the input means. And the address of the instruction executed by the processor or The comparison means compares the address of the data to be stored with the address held by the address holding means, the control means for stopping the operation of the processor when the comparison result by the comparison means matches, and further represents each label. It has a table that associates information, information indicating whether each label is set in the program space or the data space, and the physical address range to which the logical address range specified by each label is assigned. ing.

Further, the software development support apparatus according to the present invention comprises write / read input means for inputting whether to write or read the data input by the input means,
Write / read signal holding means for holding a signal indicating whether writing or reading of data input by the write / read input means, a signal held in the write / read signal holding means, and writing accompanying data access The signal and the read signal are compared with each other, and a means for giving a data address to the comparing means is provided only when they match.

[0022]

In the software development support device according to the present invention,
If any label is entered by the input means,
The control signal causes the address holding means to hold the physical address corresponding to the designated label by referring to the table.

Further, in the software development support apparatus according to the present invention, writing of data input by the input means,
Whether to read or not is input, a signal indicating whether to write or read the input data is held by the write / read signal holding unit, and the signal held in the write / read signal holding unit and the data are accessed. The write signal and the read signal are compared, and only when they match, the address of the data is given to the comparison means and the comparison is performed.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof. FIG. 1 is a block diagram showing the internal configuration of an in-circuit emulator as an embodiment of the software development support device according to the present invention.

The in-circuit emulator as the software development support apparatus of the present invention, the internal structure of which is shown in FIG. 1, is exactly the same as the conventional in-circuit emulator as shown in FIG. Installed in the host computer 1 and the target system 4
Connected with. A target processor 5 is built in the target system 4, and a keyboard 3 is connected to the host computer 1.

The keyboard 3 functions as an input means for inputting an address of an instruction to be executed by the target processor 5 or an address of data to be accessed as a break address. Also, keyboard 3
Also functions as an input means for inputting another designation of writing to or reading from the memory when the data address is designated as the break address.

In FIG. 1, reference numeral PAB indicates a program address bus and DAB indicates a data address bus, which are connected to the program bus and the data bus of the target processor 5 through an interface (not shown). There is.

Reference numeral DWE indicates a data memory write enable signal line, and DRE indicates a data memory read enable signal line. These are connected to a data memory write enable signal line and a data memory read enable signal line of the target processor 5 through an interface (not shown).

Reference numeral 21 indicates a debug controller which functions as a control means, and controls the entire ICE of the present invention. Reference numerals 220 and 221 each indicate a break address register, and an address for specifying a break point, that is, a break address is given from the debug controller 21 and is held. That is, the break address registers 220 and 221 function as a holding unit that holds the break address.

Reference numerals 30 and 31 are both W / R (write / write
(Read) This shows the detection circuit. W / R detection circuit 30, 31
In both, the address (hereinafter referred to as W / R signal) indicating the write / read from the debug controller 21, the data memory read enable signal line DRE, the data memory write enable signal line DWE, and the address from the data address bus DAB. The signal is given.

FIG. 2 is a logic circuit diagram showing a configuration example of the W / R detection circuit 30 (31). It is assumed here that both the data memory write enable signal and the data memory read enable signal are high active.

In FIG. 2, reference numeral 300 is a W / R register, which is "1" when a break at the time of reading data is designated and "0" when a break at the time of writing is designated. Respectively debug controller 21
Written from. That is, the W / R register 300 functions as a holding unit for the W / R signal.

Reference numeral 310 indicates AND of which one input is negative logic.
Gates 321 are AND gates of which both inputs are positive logic. W / R for negative logic input to AND gate 310
The output signal of the register 300 is input to the positive logic input of the data memory write enable signal line DWE. Therefore, when the signal "0" designating the break at the time of writing data is held in the W / R register 300, the data memory write enable signal line DWE becomes "1".
When it becomes (active), the output signal of AND gate 310 becomes "1". On the other hand, a W is applied to both inputs of the AND gate 311.
The output signal of the / R register 300 and the data memory read enable signal line DRE are input. Therefore,
If the data memory read enable signal line DRE becomes "1" (active) when the signal "1" that specifies the break when reading data is held in the W / R register 300, the output signal of the AND gate 311 Becomes "1".

The output signals of both AND gates 310 and 311 are input to the OR gate 320, and the output signal of the OR gate 320 is 2
Input to input AND gate 330. AND gate 33
The other input of 0 is an address signal from the data address bus DAB. Therefore, when the signal "0" designating the break at the time of writing the data is held in the W / R register 300, the data address from the AND gate 330 functions as the comparator 23 only when the data is written.
When it is output to 0 (231) and the signal "1" that specifies the break at the time of reading data is held in the W / R register 300, the data address is A only when reading the data.
Output from the ND gate 330 to the comparator 230 (231).

As is clear from the above, the AND gate 310,
311 is the W / R signal stored in the W / R register 300,
As a means for comparing the write signal and read signal associated with data access, that is, the data memory write enable signal line DWE and the data memory read enable signal line DRE, and giving a data address to the comparator 230 (231) only when they match. Function.

Returning to FIG. 1 and continuing the explanation, the comparator 230
A break address held by the break address register 220 described above, an address signal output from the W / R detection circuit 30 described above, and a program address on the program address bus PB are given to the. The break address held by the break address register 221, the address signal output from the W / R detection circuit 31, and the program address on the program address bus PB are given to the comparator 231.

The comparator 230 is a break address register.
If the break address given by 220 and the program address given by program address bus PAB match, or the break address given by break address register 220 and given by data address bus DAB via W / R detection circuit 30. A predetermined match signal S0 is output when either of the data addresses matches. The comparator 231 is the break address register 221.
If the break address given by the break address matches the program address given by the program address bus PAB, or the break address given by the break address register 221 and the data given by the data address bus DAB via the W / R detection circuit 31. A predetermined match signal S1 is output in any of the cases where the addresses match.

Reference numerals 240 and 241 both denote break counters. The break counter 240 counts the number of times the above-mentioned coincidence signal S0 is output from the comparator 23. The break counter 241 outputs the above-mentioned match signal S1 to the comparator 231.
Count the number of times output from. The number of counts of these break counters 240, 241 can be set by the debug controller 21, and when the count value of the break counters 240, 241 reaches the value set by the debug controller 21, a predetermined signal (break signal B0 , B1) is output to the debug controller 21.

Reference numeral 25 indicates a PC controller, which receives a P signal from the target processor 5 when a predetermined signal (control signal C) is given from the debug controller 21.
C, that is, the program counter is controlled to perform various controls including starting and stopping of the target processor 5.

Reference numeral 26 indicates a label table which characterizes the present invention. The label table 26 will be described below.

FIG. 3 is a schematic diagram showing the program space PS and data space DS of the target processor 5 to be emulated by the in-circuit emulator as the software development support apparatus of the present invention, and the contents of the label table 26 created from them. Is.

For example, the program space PS of the target processor 5 is divided into a range of a plurality of consecutive addresses, and the program routines A, B, C in each range are divided.
... is configured. And each of the program routines A, B, C ... has labels PA, PB, PC, respectively.
... is set.

Further, for example, it is assumed that the data space DS of the target processor 5 is divided into a plurality of consecutive address ranges, and the data tables A, B, C ... Are constructed in the respective ranges. It is assumed that labels DA, DB, DC ... Are set in the respective data tables A, B, C.

In this way, the program routines A, B, C ... With the labels PA, PB, PC ... Set respectively are allocated in the program space PS, and the labels DA, DB, DC ...
The data table A, B, C, ... in which is set is the data space DS
Information (code) representing each label as indicated by reference numeral 26 by compiling or assembling the program created in the above allocated state
And information (flag) indicating whether each label is set in the program space or the data space, and the range of logical addresses specified by each label (in this example, the address range of each label is fixed as an example. Therefore, the correspondence relationship with the range of the physical address to which (the head address only) is allocated can be obtained, and the label table 26 is stored in the host computer 1 in advance.

The operation of the in-circuit emulator as the software development support device of the present invention as described above will be described below.

For example, it is assumed that the operator operates the keyboard 3 of the host computer 1 to input the label PB of the program routine B, the label DB of the data table B, and writing / reading thereof, for example, reading. In this case, the debug controller 21 refers to the label table 26 and sets the address "100" corresponding to the label PB.
"" Is read and held as a break address in the break address register 220, and the label table
The address “1200” corresponding to the label DB is read out with reference to 26 and held in the break address register 221 as a break address. In addition, the debug controller 21
Is the data address and W / R signal “1” is W / R detection circuit 3
It is held in the W / R registers 300 of 0 and 31, and then the PC controller 25 is controlled to start the target processor 5.

After starting, the target processor 5 outputs the program address value set in its own PC, that is, the PC value, to the program address bus inside the target system 4, and accordingly (usually every time one instruction is executed).
1 "is incremented), each instruction of the program is executed, and the address of the data necessary for the execution or the address for storing the execution result is output to the data address bus inside the target system 4.

The program address and the data address output to the program address bus and the data address bus inside the target system 4 are transmitted through the interface (not shown) of the ICE 2 of the present invention to the program address bus PAB and the data address bus DAB. , The program address is direct and the data address is W / R
It is input to the comparators 230 and 231 via the detection circuits 30 and 31, respectively. Also, when the target processor 5 accesses the data, either the data memory write enable signal line DWE or the data memory read enable signal line DRE is activated (" 1 "), they are input to the W / R detection circuits 30 and 31.

In the comparator 230, the break address “0” and the program address bus PAB which are previously given to the break address register 220 from the debug controller 21 and held are passed through the W / R detection circuit 30. The data address on the given data address bus DAB is constantly compared, and if they match, a match signal S0 is output to the break counter 240. However, from the data address bus DAB, in this case, since "1" is held in the W / R register 300 of the W / R detection circuit 30, only the data address output at the time of writing the data is the comparator 23.
Given to 0.

In the comparator 231, the break address “1200” and the program address bus PAB, which have been given to the break address register 221 from the debug controller 21 and held, are passed through the W / R detection circuit 31. It constantly compares the given address on the data address bus DAB, and outputs a match signal S1 to the break counter 241 when they match. However, the data address bus DA
From B, in this case, the W / R register 300 of the W / R detection circuit 31
Since "1" is held in, the comparator 231 is provided with only the data address output at the time of writing data.

On the other hand, the break counters 240 and 241 are set with preset values by the debug controller 21 in advance. Therefore, the match signals S0, S1 from the comparator 230
When the number of outputs of B reaches the set value, break signals B0 and B1 are output to the debug controller 21, respectively. The debug controller 21 outputs the control signal C to the PC controller 25 when either of the break signals B0 and B1 is output first, and the PC controller 25 stops the PC of the target processor 5 of the target system 4. When the PC stops, the target processor 5 stops executing the program.

Now, for example, both break counters 240, 2
Assuming that both 41 are set to "1" by the debug controller 21, if the processing of the program by the target processor 5 proceeds to the program routine B in which the label PB is set, the program address bus PAB
Since the address "100" is output to, the comparison result of the comparator 230 matches and the operation of the target processor 5 is stopped. Alternatively, if an attempt is made to perform a write process on the data table B in which the label DB is set during the processing of the program by the target processor 5, the address "1200" is output to the data address bus DAB. It is given to the comparator 231 via the R detection circuit 31, the comparison result of the comparator 231 becomes coincident, and the operation of the target processor 5 is stopped.

In this way, when the target processor 5 stops the execution of the program, the contents of the register and memory in the target system 4 are read by the host computer 1 and displayed on the display screen thereof, so that the operator The state is checked visually or after being stored in an appropriate storage means to check whether the program of the target processor 5 functions as designed.

[0054]

As described above in detail, according to the software development support apparatus of the present invention, when a label is set in a memory space in which a program space and a data space are independent, the label can be designated. The address in the program space or data space indicated by the label can be specified as a breakpoint only.

When a data address is designated as a breakpoint, it is possible to specify whether to read data from that address or write to that address.

[Brief description of drawings]

FIG. 1 is a block diagram showing an internal configuration of an in-circuit emulator as an embodiment of a software development support device according to the present invention.

FIG. 2 is a logic circuit diagram showing a configuration example of a W / R detection circuit for detecting whether data is written or read in an in-circuit emulator as a software development support device according to the present invention.

FIG. 3 is a schematic diagram showing the program space and data space of a target processor to be emulated by an in-circuit emulator as a software development support device of the present invention, and the contents of a label table created from them.

FIG. 4 is a block diagram showing a configuration example of a conventional in-circuit emulator.

FIG. 5 is a schematic diagram showing a general connection state between a host computer incorporating an in-circuit emulator and a target processor.

[Explanation of symbols]

 1 Host computer 2 ICE 3 Keyboard 4 Target system 5 Target processor 21 Debug controller 25 PC controller 26 Label table 30 W / R detection circuit 31 W / R detection circuit 220 Break address register 221 Break address register 230 Comparator 231 Comparator PAB program Address bus DAB Data address bus

Claims (2)

[Claims] 1. A program space composed of a logical address in which each instruction of a program to be executed is arranged, a data used in execution of the program, and a logical address in which execution result data is arranged. Is allocated to a logical space independent of the data space
The program space and the data space are connected to a processor having a memory space in which a label is set by dividing the program space and the data space into a plurality of continuous logical address ranges, and the address of an instruction to be executed by the processor or to be accessed Input means for inputting an address of data, address holding means for holding an address input by the input means, address of an instruction executed by the processor or address of data accessed when the instruction is executed, and the address holding In a software development support device including a comparison unit that compares an address held by the unit, and a control unit that stops the operation of the processor when the comparison result by the comparison unit matches, information indicating each label, Each label is program space or data space It has a table in which the information indicating which is set and the range of the physical address to which the range of the logical address specified by each label is assigned are associated with each other. When the label is input, the software development support device is configured to cause the address holding means to hold the physical address corresponding to the designated label by referring to the table. 2. A write / read input means for inputting write / read of data input by the input means, and a signal indicating write / read of data input by the write / read input means. The write / read signal holding means to hold, the signal held in the write / read signal holding means, the write signal and the read signal accompanying the access of the data are compared, and the data is written to the comparing means only when they match. 2. The software development support apparatus according to claim 1, further comprising: means for giving the address of.