JPH08329232A - Picture data storage device - Google Patents

Abstract

PURPOSE: To provide a picture data storage device having the same function as adoption of a dual port memory and capable of being produced with a low cost by arranging two single port RAMs in parallel between a picture data input port and a picture data output port. CONSTITUTION: Output terminals A and B of an input side switching circuit 3 are connected to ports P3 and P4 of two single port RAMs 1 and 2 through busses bus1 and bus3. Input terminals A and B of an output side switching circuit 4 are connected to ports P3 and P4 of two single port RAMs 1 and 2 through busses bus2 and bus4. In this case, single port RAMs 1 and 2 have the same storage capacity corresponding to one frame of the video signal and can be accessed independently of each other by write control signals 1 and 2 and read control signals 1 and 2. Ports P3 and P4 are alternatively connected to a picture data input port P1 or a picture data output port P2 by switching circuits 3 and 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data storage device suitable for displaying various moving images by appropriately performing image processing on image data generated based on video signals.

[0002]

2. Description of the Related Art In recent digital devices such as personal computers and word processors, it is known that a corresponding moving image can be displayed on a screen based on a video signal received by a TV or taken by a video camera. . An external support device generally called a video capture board or the like is used for such an application. When a moving image is displayed using a video capture board, various processing such as enlargement, reduction, and mosaicing can be easily performed on the original moving image by using appropriate image processing software together.

By the way, such a video capture board is provided between a video signal capturing device (which is composed of a high-speed AD converter or the like) and an image processing device (which is composed of a personal computer or a word processor). A built-in image data storage device is provided for temporarily storing digital image data corresponding to a video signal captured by the video signal capturing device and reading it out to the image processing device side as necessary. . Conventionally, a so-called dual port memory is generally used as the image storage device because of the advantage that the writing operation from the video signal capturing device and the reading operation from the image processing device can be performed asynchronously.

[0004]

However, the conventional image data storage device employing such a dual port memory has an advantage that the read operation and the write operation can be performed asynchronously, but on the other hand, a single port is used. DR
There is a problem that it is expensive because it requires a high-speed element as compared with AM and the like.

The present invention has been made in view of the above-mentioned problems, and an object thereof is to have a function substantially equivalent to that of a dual port memory and to be manufactured at low cost. Another object is to provide a simple image data storage device.

[0006]

SUMMARY OF THE INVENTION The present invention is located between a video signal capturing device and an image processing device and temporarily stores digital image data corresponding to a video signal captured by the video signal capturing device. And an image data storage device for reading the image data to the image processing device side as needed, and an image data input port to be connected to the video signal capturing device, and an image data input device to the image processing device. An image data output port to be connected, two single-port RAMs arranged in parallel between the image data input port and the image data output port, each having a storage capacity of at least one field of a video signal, An input side switching circuit capable of selectively connecting the image data input port to each of the ports of the two single-port RAMs; An output side switching circuit capable of selectively connecting a power port to each of the ports of the two single-port RAMs, and writing data from the image data input port in each of the two single-port RAMs. And a cooperation circuit for controlling the input side switching circuit and the output side switching circuit so that the operation and the data reading operation to the image data output port are alternately performed without conflict. is there.

According to the present invention, internally, the data write operation from the image data input port and the data read operation to the image data output port alternate in each of the two single-port RAMs without conflict. However, apparently from the outside, the write operation to the image data input port and the read operation from the image data output port can be performed without being aware of the internal circuit. Since an inexpensive element such as a DRAM can be used as the one-port RAM, it is possible to realize an image data storage device that can be manufactured at low cost, although it has substantially the same function as that of the dual-port memory.

The alternate switching control of the two single-port RAMs can be made to respond to a timing signal from a built-in self-excited oscillator or to respond to a timing signal from the outside. As the external timing signal, it is preferable to use a frame synchronization signal or a field synchronization signal supplied from the video signal capturing device. Further, at this time, if the status signals (write status / read status) of the two single-port RAMs are sent to the image data processing device side, the read control from the outside becomes easy.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. A hardware configuration diagram of an embodiment of an image storage device according to the present invention is shown in FIG. The image data storage device is provided between a video signal capturing device (not shown) (comprising a high-speed AD converter or the like) and an image processing device (not shown) (comprising a personal computer, word processor or the like), and the video signal The digital image data corresponding to the video signal captured by the capture device is temporarily stored and read out to the image processing device side as necessary.

As shown in the figure, the image data storage device includes an image data input port P1 to be connected to a video signal capturing device (not shown) and an image to be connected to an image processing device (not shown). Data output port P2
And two single port RAMs 1 and 2 arranged in parallel between the image data input port P1 and the image data output port P2 and each having a storage capacity of at least one field of the video signal, and the image data input port P1. The input side switching circuit 3 which can be selectively connected to each of the ports P3 and P4 of the two single port RAMs 1 and 2, and the image data output port P2 are connected to the two single port RAMs.
The output side switching circuit 4 which can be selectively connected to each of the ports P3 and P4 of 1 and 2, and the two single ports RA.
The input side switching circuit 3 and the output side switching circuit are arranged so that the data writing operation from the image data input port P1 and the data reading operation to the image data output port P2 are alternately performed in each of M1 and M2 without conflict. Four
And a cooperation circuit 5 for controlling

The image data input port P1 is shown in FIG.
As shown in (d), image data F1, F2, F for each frame forming the video signal to be captured.
3, F4 ... Are continuously supplied. Further, as shown in FIG. 2 (i), the above-mentioned image data F1, F2, F3, F4, ... Can be sequentially read from the image data output port P2 with a delay of one frame.

The input side switching circuit 3 has two output terminals A and B.
And these output terminals A and B are bus buses.
1, via the bus bus3, respectively, to the ports P3 and P4 of the two single-port RAMs 1 and 2, respectively. Similarly, the output side switching circuit 4 has two input terminals A and B, and these input terminals A and B pass through the bus bus2 and the bus bus4 respectively, and two single port RAM1. , 2 of each of the ports P3 and P4.

The two single-port RAMs 1 and 2 are:
In principle, either DRAM or SRAM can be adopted, but D is required in order to reduce the cost which is the object of the present invention.
It is preferable to use RAM. These single-port RAMs 1 and 2 have the same storage capacity for one frame of the video signal, and the write control signals 1 and
2 and read control signals 1 and 2 are used so that they can be accessed independently of each other. Further, the respective ports P3, P4 of these single-port RAMs 1, 2 are selected as either the image data input port P1 or the image data output port P2 by the action of the input side and output side switching circuits 3, 4. Are connected to each other.

The input side switching circuit 3 and the output side switching circuit 4 are designed to alternately perform switching operations under the control of the cooperation circuit 5, and in this example, in particular, FIGS.
As shown in (c), the switching timing is controlled in response to the frame synchronization signal s1 sent from the video signal capturing device side.

Next, the operation of the image data storage device having the above configuration will be systematically described with reference to the timing chart of FIG. Now, suppose that the image data input port P1 has image data F1 and F1 corresponding to consecutive video frames in synchronization with a frame synchronization signal (see FIG. 2a).
2, F3, F4 ... (See FIG. 2d) have arrived, and it is assumed that the input side switching circuit 3 and the output side switching circuit 4 alternately repeat the switching operation in synchronization with the frame synchronization signal. (See Figures 2b and c).

At this time, when the input side switching circuit 3 is switched to the terminal A side and the output side switching circuit 4 is switched to the B side (see FIGS. 2B and 2C), the image data from the image data input port P1 is input. (F1) is written in the single-port RAM1 via the bus bus1 (see FIG. 2e), and the image data (blank in the figure) of the single-port RAM2 is stored in the bus bus.
It is read out from the image data output port P2 via 4 (see FIG. 2h).

Next, the input side switching circuit 3 is connected to the terminal B side,
When the output side switching circuit 4 is switched to the A side (see FIGS. 2b and 2c), the image data (F2) from the image data input port P1 is written to the single port RAM 2 via the bus bus3. The image data (F1) of the single-port RAM1 is read from the image data output port P2 via the bus bus2 (see FIG. 2f) (FIG. 2).
g)).

Next, the input side switching circuit 3 is connected to the terminal A side,
When the output side switching circuit 4 is set to be switched to the B side (see FIGS. 2b and 2c), the image data (F3) from the image data input port P1 is written in the single port RAM1 via the bus bus1. (See FIG. 2e), and the image data (F2) of the single-port RAM 2 is read from the image data output port P2 via the bus bus4 (FIG. 2).
h)).

Next, the input side switching circuit 3 is connected to the terminal B side,
Further, when the output side switching circuit 4 is set to be switched to the A side (see FIGS. 2b and 2c), the image data (F4) from the image data input port P1 is written to the single port RAM 2 via the bus bus3. The image data (F3) of the single-port RAM1 is read from the image data output port P2 via the bus bus2 (see FIG. 2f) (FIG. 2).
g)).

Next, the input side switching circuit 3 is connected to the terminal A side,
Further, when the output side switching circuit 4 is set to be switched to the B side (see FIGS. 2b and 2c), the image data (F5) from the image data input port P1 is written in the single port RAM1 via the bus bus1. (See FIG. 2e), and the image data (F4) of the single-port RAM 2 is read from the image data output port P2 via the bus bus4 (FIG. 2).
h)).

As a result of the above operations being repeated, the image data input from the image data input port P1 (see FIG. 2d) are sequentially read out from the image data output port P2 with a delay of one frame (see FIG. 2i). At that time, it is well known that appropriate processing such as enlargement, reduction, and mosaicing of a moving image can be performed by appropriately controlling the read timing and read address on the image processing apparatus side.

As described above, according to the device of this embodiment, the two single-port RAMs 1 such as the relatively inexpensive DRAM 1 are used.
Although the RAM 2 is adopted, the RAMs 1 and 2 are automatically and alternately connected to the image data input port P1 and the image data output port P2 via the input side switching circuit 3 and the output side switching circuit 4, so that the image On the processor side, these RAMs
It is possible to sequentially read the image data, considering that 1 and 2 are arranged in the same address space,
The function equivalent to the dual port RAM can be realized without paying attention to any switching process.

In the above embodiments, the single port RAM is used.
Although the storage capacities of 1 and 2 correspond to the image data of one frame of the video signal, this is merely an example, and an appropriate modification such as one field or two or more frames is made. Of course, it is possible.

[0024]

As is apparent from the above embodiments, according to the present invention, there is provided an image data storage device which has substantially the same functions as those employing the dual port memory and can be manufactured at low cost. Can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing hardware of an embodiment of the present invention.

FIG. 2 is a timing chart of an embodiment of the present invention.

[Explanation of symbols]

 1 Single Port RAM 2 Single Port RAM 3 Input Side Switching Circuit 4 Output Side Switching Circuit 5 Coordination Circuit P1 Image Data Input Port P2 Image Data Output Port P3 Single Port RAM Port P4 Single Port RAM Port S1 Frame Synchronization Signal S2 Memory status signal

Claims (5)

[Claims] 1. Digital image data corresponding to a video signal captured by the video signal capturing device is temporarily stored between the video signal capturing device and the image processing device, and the digital image data is stored as necessary. An image data storage device for reading to the image processing device side, wherein an image data input port to be connected to the video signal capturing device and an image data output port to be connected to the image processing device Two single-port RAMs arranged in parallel between the image data input port and the image data output port and each having a storage capacity of at least one field of a video signal; Single port RA
An input side switching circuit that can be selectively connected to each of the M ports, and the image data output port is connected to the two single ports RA.
An output side switching circuit that can be selectively connected to each of the M ports, and a data write operation from the image data input port and a data read from the image data output port in each of the two single-port RAMs. An image data storage device, comprising: a cooperation circuit that controls the input-side switching circuit and the output-side switching circuit so that the operation and the output-side switching circuit are alternately performed without conflict. 2. The coordinating circuit controls the input side switching circuit and the output side switching circuit in response to a video synchronization signal sent from the video signal capturing device. 1. The image data storage device according to 1. 3. The image data storage device according to claim 1, wherein the cooperation circuit generates a status signal of the two single-port RAMs and outputs the status signal to the image processing device side. 4. The image data storage device according to claim 2, wherein the video synchronization signal is a frame synchronization signal. 5. The video synchronization signal is a field synchronization signal, and the video synchronization signal is a field synchronization signal.
The image data storage device according to.