JPH0832961A - Video signal compression device and video signal expansion device - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the quality of a reproduced image even when a video signal of the second generation EDTV system is compressed. [Structure] The input video signal is given to a discrimination circuit 22 to discriminate the system. The switch 23, depending on the determination signal from the determination circuit 22,
28 is switched and the current NTSC system video signal is supplied to the current system video signal compression circuit 24 or the current system video signal decompression circuit 25. Further, the video signal of the second generation EDTV system is given to the wide system video signal compression circuit 26 or the wide system video signal expansion circuit 27. A compression circuit and a decompression circuit that differ for each system are used, and optimal compression according to the system is possible. The horizontal and vertical reinforcement signals of the video signal of the second generation EDTV system are weighted in the high frequency range and quantized to enable transmission of sufficient power. This improves the quality of the reproduced image.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal compression apparatus and a video signal decompression apparatus suitable for recording and reproducing a second generation EDTV broadcast.

[0002]

2. Description of the Related Art In recent years, second-generation EDTV (Extended Definition TV) broadcasting aimed at high image quality and high sound quality has been studied. Second-generation EDTV broadcasting is compatible with current broadcasting and has a screen aspect ratio of 1
The horizontal aspect ratio of 6: 9 makes it possible to watch programs with a realistic feel. The effective scanning line of the second generation EDTV signal (wide aspect television signal) is 1 in the vertical center of the current NTSC signal having an aspect ratio of 4: 3.
It corresponds to the part of 6: 9. Therefore, for example, when a second-generation EDTV broadcast is displayed by a television receiver for current broadcasting having an aspect ratio of 4: 3, a letterbox display having a non-image portion at the top and bottom of the screen and a main image portion at the center is displayed. Will be done.

FIG. 14 shows a screen display when such a letter box type video signal is received by a current television receiver of the NTSC system.

The aspect ratio of the display screen 1 of an NTSC television receiver is 4: 3. In the vertical center of the display screen 1 where the aspect ratio is 16: 9, the main image portion 2 having 180 scanning lines per field is displayed, and the upper and lower scanning lines of the display screen 1 are 30 lines each. The non-image part 3 (mesh line part) of a predetermined black level is displayed in the area of. Since the aspect ratio of the main image portion 2 is 16: 9, the roundness of the projected effective image is 1.

This image has an aspect ratio of 16: 9.
When the image is displayed on the display screen of No. 1, as shown in FIG.

The second generation EDTV has an aspect ratio of 4:
Since only the central 16: 9 portion of the current NTSC signal of No. 3 is the effective scanning line, the number of effective scanning lines of the current NTSC signal is 480, whereas the second generation ED for transmission
The number of effective scanning lines for TV signals is 360. Second generation E
In a television receiver compatible with the DTV system,
At the time of decoding, these effective scanning lines of 360 lines are converted into 3 to 4 scanning lines and returned to 480 lines. By simply converting the scan lines,
Since the second-generation EDTV signal has a lower vertical resolution than the current NTSC signal, it has been decided to multiplex and transmit a vertical reinforcement signal for improving the vertical resolution during transmission.

In the second generation EDTV system, a progressive scanning signal of 480 lines / screen height is converted into an interlaced scanning signal and transmitted on the transmitting side. In this case, in order to make the letterbox format, that is, to make the number of effective scanning lines 360, the luminance signal of 480 lines / screen height is band-limited to 360 lines / screen height signal by the vertical low-pass filter. To do. Further, in order to convert to the interlaced scanning signal, the luminance signal is band-limited to the signal of 180 lines / screen height by the vertical low pass filter. The band limitation prevents the generation of aliasing distortion at the time of scanning line conversion. The component YL of 4.2 MHz or less in the horizontal low range of the luminance signal of 180 lines / screen height is transmitted as the main image portion signal. Also, 180 to 3 lost due to band limitation during conversion from progressive scanning to interlaced scanning
60 lines / temporal vertical high frequency component (VT signal)
Is transmitted as a vertical reinforcement signal.

The main picture portion signal and the VT signal are SSK
Separated by F (Symmetric Short Kernel Filter). As SSKF, a 3-tap or 5-tap filter is used. In addition, a vertical high-frequency component (VH signal) of a luminance signal of 360 to 480 lines / screen height, which is lost due to band limitation during conversion to the letterbox format, is also transmitted as a vertical reinforcement signal. These components VH and VT are added according to the movement of the image and compressed to 1/3 in the horizontal direction (time direction). In this case, in order to separate the VT signal and the VH signal on the receiving side, the VH signal is line-inverted to shift by 15 Hz in the time axis direction and then V
Add with T signal. Next, the added signal is modulated using the color subcarrier, band limited using the Nyquist filter, and multiplexed in the non-image areas at the top and bottom of the screen. In order to prevent the vertical reinforcement signal of the non-image portion from standing out on the screen, a component having a correlation with the VT signal is generated from the main image portion signal, and after subtracting this component from the VT signal, it is converted into the VH signal. It is designed to add.

Further, the component YH of the band of 4.2 to 6 MHz in the horizontal high range of the luminance signal of 180 lines / screen height is multiplexed with the main picture portion signal as the horizontal reinforcement signal HH '. In this case, the horizontal high frequency component YH has a frequency of 1
The carrier suppression amplitude modulation is performed using a carrier of 6/7 fsc (fsc is a color subcarrier frequency), and the frequency is further shifted and frequency-multiplexed with the main picture portion signal.

FIG. 15 is an explanatory diagram for explaining the multiplexed state of these horizontal and vertical reinforcement signals. In FIG. 15, the vertical direction shows the scanning lines in the odd field and the even field, and the horizontal direction shows the pixels in the screen horizontal direction.

One screen is composed of horizontal 910 pixels × vertical 525 lines. Of the 525 vertical lines, the number of effective scanning lines is 480, which is 240 per field. The HH 'signal of the horizontal reinforcement signal is multiplexed in the main image portion of the center 180 of the 240 effective scanning lines in each field. In addition, the vertical reinforcement signal VT and VH signals are multiplexed in the upper non-picture area of 30 scanning lines and the lower non-picture area of 30 scanning lines in each field. The VT and VH signals are time-compressed to 1/3 and the VT multiplexed on one line
The VH signal improves the resolution of the main image portion for three lines. That is, for example, the VT and VH signals multiplexed in the period ⅓ on the left side of the screen of the first line of the upper non-picture part of each field correspond to the first line of the main picture part and 1 / m of the center.
The VT and VH signals multiplexed in the period of 3 are the second of the main picture part.
VT corresponding to the line and multiplexed in the right third period
And VH signals correspond to the third line of the main picture portion.

In the second generation EDTV broadcasting,
In order to improve the YC separation performance, three-dimensional precoding is performed on the transmitting side. Incidentally, these techniques are disclosed in Japanese Patent Publication No. 208783/1992.

By the way, it is conceivable to record or reproduce this second generation EDTV broadcast signal in a consumer VTR (video tape recorder). If a digital VTR is adopted in this case, it is necessary to compress and record the second generation EDTV broadcast signal.

FIG. 16 is a block diagram showing a digital VTR incorporating a conventional video signal compression device and video signal expansion device.

The consumer VTR enables high-quality recording for a long time by high-density recording and high-efficiency coding. The analog input video signal is supplied to the video processing circuit 4. The video processing circuit 4 converts the input video signal into a digital signal and frames it. As a result, one frame is, for example, 72
It is composed of 0 pixels × 480 lines of effective pixels. The video signal from the video processing circuit 4 is separated into a luminance signal component and a color difference signal component for processing. Note that, in FIG. 16, only the luminance signal component is shown for simplification of description.

The video processing circuit 4 blocks the framed video signal into, for example, a block of 8 pixels × 8 lines (DCT block) and supplies the block to the shuffling circuit 5. The shuffling circuit 5 shuffles the input data and gives it to the DCT circuit 6. FIG. 17 is an explanatory diagram showing blocking, and FIG. 17A shows a luminance block.
7 (b) shows a color difference block. Since the number of effective pixels of the luminance signal is 720 pixels × 480 lines, one frame is divided into 90 × 60 luminance blocks as shown in FIG. On the other hand, due to the difference in sampling clocks between the color difference signal and the luminance signal, the sizes of the luminance block and the color difference block are different. For example, assuming that the sampling clock of the color difference signal has a frequency of 1/4 of the sampling clock of the luminance signal, one frame of the color difference signal is composed of 180 pixels × 480 lines. Therefore, the color difference blocks Cb and Cr of 8 pixels × 8 lines are 22.5 × in each frame as shown in FIG. 17B.
It consists of only 60 blocks.

The DCT circuit 6 converts the spatial coordinate axis component into a frequency axis component by subjecting the block data from the video processing circuit 4 to two-dimensional DCT (discrete cosine transform) processing. The transform coefficient from the DCT circuit 6 is given to the quantizing circuit 7 and quantized by using a predetermined quantizing coefficient. In this case, considering the human visual characteristics, the quantization coefficient is set larger for the higher frequency component of the transform coefficient. This reduces signal redundancy.

The output of the quantizing circuit 7 is a variable length coding circuit 8
The variable-length coding circuit 8 gives a predetermined variable-length code table,
For example, the quantized output is variable-length coded based on the Huffman code table or the like and output to the error correction coding circuit 9. As a result, short bits are assigned to data with a high appearance probability, long bits are assigned to data with a low appearance probability,
Further reduce the amount of transmission.

In consideration of special reproduction and the like, the encoded output from the variable length encoding circuit 8 is designed to have a fixed length. This fixed length is performed, for example, in macroblock units. FIG. 18 shows the structure of a macro block. Considering that the size of the luminance block and the chrominance block is 1: 4, a macro block is configured by 6 DCT blocks of 4 luminance blocks and 1 chrominance block. Then, for example, by fixing the length to 5 macroblocks at discrete positions on the screen, the code amount is appropriately assigned regardless of the pattern.

On the other hand, the input voice signal is given to the voice processing circuit 11. The audio processing circuit 11 A / D-converts the input audio signal, synchronizes it with the video signal, performs mixing processing, and outputs it to the error correction encoding circuit 9. The error correction encoding circuit 9 encodes the compressed video data and audio data into a product code such as a Reed-Solomon code, and outputs the product code to the modulation circuit 10. The modulation circuit 10 modulates the input data by a modulation method suitable for high density recording and records it on the magnetic tape 12 via a magnetic head (not shown).

During reproduction, reproduction data from the magnetic tape 12 is given from the magnetic head to the demodulation circuit 13. Demodulation circuit
Reference numeral 13 demodulates the reproduced data, and the demodulated data is subjected to error correction processing by the error correction decoding circuit 14. The video data from the error correction decoding circuit 14 is given to the variable length decoding circuit 15,
The audio data is given to the audio processing circuit 16. The variable length decoding circuit 15 variable length decodes the video data and supplies it to the inverse quantization circuit 17, and the inverse quantization circuit 17 inversely quantizes the variable length decoding output and supplies it to the inverse DCT circuit 18. The inverse DCT circuit 18 performs inverse DCT processing on the input data, expands the original coordinate axis data before DCT processing, and outputs it to the deshuffling circuit 19.

The deshuffling circuit 19 performs deshuffling within the frame on the decompressed data to restore the original data array, and the video processing circuit 20 performs D / A conversion to obtain an analog output video signal. On the other hand, the audio data from the error correction decoding circuit 14 is given to the audio processing circuit 16, and after time adjustment with the video signal and correction processing, D / A conversion is performed to obtain an analog output audio signal.

By the way, as described above, the second generation ED
The TV signal includes a horizontal high frequency component (HH 'signal), a vertical high frequency component (VH signal), and a temporal vertical high frequency component (VT signal). When DCT processing is performed on these components, the transform coefficient has a large power on the high frequency side in the horizontal or vertical direction.
However, since the quantizing circuit 7 sets a larger quantizing coefficient for the higher frequency component of the transform coefficient, these components are missing and sufficient power cannot be transmitted. For this reason, there is a problem that it is not possible to obtain a high-quality reproduced image by using these reinforcement signals.

[0024]

As described above, in the above-described conventional video signal compression apparatus and video signal decompression apparatus, the horizontal high frequency component, the vertical high frequency component, and the time vertical high frequency component of the second generation EDTV signal are provided. Since the components are not transmitted with sufficient power, there is a problem that the quality of the reproduced image is not sufficient.

It is an object of the present invention to provide a video signal compression device and a video signal expansion device that can obtain a reproduced image with sufficient image quality even when the second generation EDTV signal is compressed.

[Constitution of the Invention]

According to a first aspect of the present invention, there is provided a video signal compression apparatus, wherein an input video signal based on a wide aspect television signal or a non-wide aspect television signal is input, and the system of the input video signal is adopted. Discriminating means for discriminating and outputting a discrimination result, non-wide format video signal compressing means for compressing the non-wide aspect television signal, and wide format video signal compressing means for compressing the wide aspect television signal, Selection means for selectively outputting the output of the non-wide format video signal compression means or the output of the wide format video signal compression means, and the output of this selection means and the discrimination result are multiplexed to output a multiplexed signal. The video signal decompressing device according to claim 6 of the present invention is a wide aspect television projector. A signal or a compression signal for a non-wide aspect television signal and a determination signal for determining whether the compression signal is based on a wide aspect television signal or a non-wide aspect television signal Non-wide format video signal expanding means for receiving the multiplex signal and expanding the compressed signal for the non-wide aspect television signal to obtain the non-wide aspect television signal; and the multiplex signal for inputting the wide television. Wide system video signal decompression means for decompressing a compressed signal for the signal to obtain the wide aspect television signal, and output of the non-wide system video signal decompression means based on the discrimination signal included in the multiplex signal or the Switching the output of the wide system video signal expansion means It is obtained; and a switching means for force.

[0027]

In the first aspect of the present invention, the discrimination means discriminates the system of the input video signal and outputs the discrimination result. When the input video signal is a non-wide aspect television signal, it is compressed by the non-wide format video signal compression means, and when it is a wide aspect television signal, it is compressed by the wide format video signal compression means.
As a result, it is possible to perform optimum compression according to the input video signal system. The selecting means selects the output of the non-wide format video signal compressing means or the output of the wide format video signal compressing means based on the determination result, and the multiplexing means multiplexes the method determination result with the output of the selecting means and outputs the result. .

In the sixth aspect of the present invention, the input multiplex signal is a multiplex of the compression signal and the discrimination signal for the non-wide aspect television signal or the wide aspect television signal. The switching means switches and outputs the output of the non-wide format video signal expansion means or the output of the wide format video signal expansion means based on the determination signal.
As a result, the optimum expansion processing is performed according to the video signal system.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a video signal compression device and a video signal expansion device according to the present invention.

This embodiment is an example applied to a recording / reproducing apparatus in which an input video signal is compressed and supplied to a recording system, and a reproduction signal from the reproduction system is expanded to restore the original video signal. At the time of recording, an NTS from a tuner (not shown) is connected to the terminal 21.
A baseband video signal of the C system or the second generation EDTV system is input. This video signal is given to the switch 23 and the discrimination circuit 22. On the other hand, during reproduction, the video signal from the switch 23 is output via the terminal 21.

At the beginning of the second-generation EDTV broadcasting, a signal of the current NTSC system having an aspect ratio of 4: 3 and a signal of the second-generation EDTV system having an aspect ratio of 16: 9 are mixed and broadcast for each program. It is expected that. Therefore, it is necessary for the receiving side to perform control corresponding to the current NTSC system and the second-generation EDTV system, respectively. Therefore, it has been decided on the transmitting side to multiplex and transmit an identification signal indicating that a second generation EDTV system broadcast signal is being transmitted. The identification signal indicates the aspect ratio of the broadcast signal and the presence / absence of various reinforcing signals, and the phase reference for demodulating the reinforcing signal is obtained.

The identification signal is at the top of the image area (22H,
285H) in the horizontal scanning period. The identification signal is
It has bit areas B1 to B27 for 27 bits.
The bit width of each bit is 7 times the color subcarrier period. The bit areas B1 to B5 and B24 are identification codes transmitted in the NRZ (non-return zero) format, and the bit area B6.
To B23 are identification codes of the color subcarrier format (frequency is fsc)
Is. Further, in the bit areas B25 to B27, a confirmation signal for determining the existing video signal is transmitted. The confirmation signal is a sine wave having a frequency of 2.04 MHz (= (4/7) fsc).

The discrimination circuit 22 is the input video signal 22H or 2
By detecting whether or not the identification signal is superimposed on 85H, it is determined whether the input video signal is the signal of the second generation EDTV system or the signal of the current NTSC system, and the determination signal is switched to the switch 23. , 28 is output. Further, the discriminating circuit 22 determines whether the reproduced signal is the signal of the second generation EDTV system or the current NTSC system based on the discriminant signal included in the reproduced signal from the error correction coding / decoding circuit 29 described later. It is configured to determine whether there is any and output a determination signal to the switches 23 and 28. The switches 23 and 28 select the terminal a when the discrimination signal indicates that the current NTSC video signal has been input, and indicate that the second generation EDTV video signal has been input. In this case, the terminal b is selected.

A current system video signal compression circuit 24 and a current system video signal expansion circuit 25 are connected between the terminals a of the switches 23 and 28, and a wide system video signal compression circuit 26 and a current system video signal expansion circuit 25 are connected between the terminals b. The decompression circuit 27 for wide type video signals is connected. The switch 28 outputs the signals input to the terminals a and b to the error correction encoding / decoding circuit 29 and outputs the reproduced signal from the error correction encoding / decoding circuit 29 to the terminals a and b. It has become. The error correction coding / decoding circuit 29 receives the output of the switch 28 and the discrimination signal, multiplexes both, performs error correction coding, and outputs the multiplexed signal to a recording system (not shown). Further, the error correction coding / decoding circuit 29 is adapted to perform error correction decoding of a reproduction signal from a reproduction system (not shown) and output it to the switch 28 and the discrimination circuit 22.

2 to 5 respectively show the current system video signal compression circuit 24, the current system video signal decompression circuit 25, the wide system video signal compression circuit 26 and the wide system video signal decompression circuit 27 shown in FIG. It is a block diagram shown. 2 to 5, the same components as those in FIG. 16 are designated by the same reference numerals.

In FIG. 2, an input video signal from the terminal a of the switch 23 is given to the video processing circuit 4. Video processing circuit 4
Outputs the input video signal to the shuffling circuit 5 after framing it. The shuffling circuit 5 shuffles the framed video data and outputs it to the DCT circuit 6 in block units of, for example, 8 pixels × 8 lines.

The DCT circuit 6 transforms the spatial coordinate axis component into a frequency axis component by subjecting the input block data to two-dimensional DCT processing. In this case, the transform coefficient of the DCT circuit 6 consists of one DC component and 63 AC components, and the DCT circuit 6 sequentially arranges the transform coefficients from the horizontal and vertical low frequencies to the high frequencies, It outputs to the quantization circuit 7 in the zigzag scan order.

FIG. 6 is an explanatory diagram for explaining zigzag scanning. The numbers in FIG. 6 indicate the output order of the 64 transform coefficients of the 1DCT block. As shown in FIG.
The conversion coefficient is sequentially output while performing zigzag scanning in the order from the DC component to the horizontal and vertical high frequencies.

The quantizing circuit 7 quantizes the transform coefficient based on the quantized coefficient. FIG. 7 is an explanatory diagram for explaining the quantization coefficient used by the quantization circuit 7 under a predetermined condition. The 64 coefficients in FIG. 7 correspond to the 64 DCT transform coefficients in FIG. 6, respectively. The quantization circuit 7 performs quantization by multiplying each transform coefficient by each corresponding quantization coefficient. As shown in FIG. 7, the quantization coefficient for the horizontal and vertical low-frequency transform coefficients has a larger value.

In general, the quantization coefficient is designed to divide the low to high band of the transform coefficient into a plurality of areas and set a value for each area. FIG. 8 is an explanatory diagram showing division of this area. FIG. 8 shows to which area the 64 DCT transform coefficients belong by the area numbers from 0 to 4.

Quantization coefficients are set according to these areas. For example, if the quantization circuit outputs the quotient obtained by dividing the DCT transform coefficient by the quantization coefficient as the quantization output, the data amount can be reduced by setting a large quantization coefficient. So in this case,
By setting the quantization coefficient for the conversion coefficient of area number 0 small, weighting can be performed so that low-frequency components are sufficiently transmitted.

As described above, the generated code amount can be controlled by adjusting the quantization coefficient used by the quantization circuit. By the way, the maximum value of the transform coefficient may be extremely large depending on the block, and conversely, there is a DCT block in which the maximum value of the transform coefficient is extremely small. These DC
If a constant quantized coefficient is used for each area for the T block, excess or deficiency of the code amount occurs. Therefore, each DCT block is divided into, for example, four classes according to the maximum value of the transform coefficient, and the quantization coefficient is set for each class.

Further, as will be described later, in the present embodiment as well, as in the conventional example, the encoded output is fixed length in units of, for example, 5 macroblocks. It is necessary to set the quantization coefficient such that the code amount of the macro block, which is the unit of encoding, is within a predetermined set code amount. Therefore,
A number (Q
No.) is set in macroblock units. The smaller Q number is assigned to the macro block in which the generated code amount tends to be larger.

FIG. 9 is an explanatory diagram showing the quantization coefficient of the quantization circuit 7 set in consideration of the area number, class number and Q number. In FIG. 9, the transform coefficient is divided into four area numbers 0 to 3, each block is divided into four class numbers 0 to 3, and each macroblock is divided into 0 to 15.
It is divided into 16 Q-numbers. The quantized coefficient for each transform coefficient is obtained from these area number, class number and Q number. In FIG. 9, the quantized coefficients are classified into five levels of 1, 2, 4, 8, and 16.

For example, in the case of a DCT block of class number 0 having a relatively small maximum value of transform coefficients, if the Q number of the macroblock to which it belongs is 4, the quantized coefficient for the transform coefficient belonging to area number 0 Is 1,
The quantization coefficient for the transform coefficient belonging to area number 1 is 2
The quantized coefficient for the transform coefficient belonging to the area number 2 is 2, and the quantized coefficient for the transform coefficient belonging to the area number 3 is 4.

The quantized output from the quantizing circuit 7 is given to the variable length coding circuit 8. The variable length coding circuit 8 performs variable length coding on the quantized output using a predetermined variable length code table, for example, a Huffman code table, and outputs it as a coded output. In this case, the variable length coding circuit 8 performs fixed length coding so that the code amount of the coded output is within a predetermined set code amount. For example, the variable-length coding circuit 8 collects five macroblocks each composed of four luminance blocks and one color difference block, and performs fixed length conversion in units of these five macroblocks.

According to the current system video signal compression circuit 24 thus constructed, the same compression as the conventional one is performed. That is, the video signal of the current NTSC system is framed in the video processing circuit 4, shuffled by the shuffling circuit 5, and then the DCT circuit 6 is divided into blocks of 8 × 8 pixels.
Give to. The DCT circuit 6 converts the block data into frequency axis components and outputs the conversion coefficient to the quantization circuit 7.

The quantizing circuit 7 quantizes the transform coefficient using the quantizing coefficient set based on FIG. As shown in FIG. 9, the higher the high frequency component of the transform coefficient is set, the larger the quantization coefficient is set, and the quantization circuit 7 performs the quantization by weighting the low frequency component. The quantized output from the quantization circuit 7 is variable length coded by the variable length coding circuit 8 and output as a coded output.

In FIG. 3, terminal a of the switch 28 shown in FIG.
The reproduced signal from is supplied to the variable length decoding circuit 15. The variable length decoding circuit 15 variable length decodes the reproduction signal and outputs it to the inverse quantization circuit 17. The inverse quantization circuit 17 is a variable length decoding circuit 15
Is inversely quantized by using the quantized coefficient based on FIG. 9 to restore the data before quantization and output to the inverse DCT circuit 18.
The inverse DCT circuit 18 performs inverse DCT processing on the inverse quantized output to return the frequency axis component to the spatial coordinate axis component and outputs the block data to the deshuffling circuit 19. The deshuffling circuit 19 deshuffles the block data, restores the pre-shuffled array, and outputs it to the video processing circuit 20. The video processing circuit 20 frames the input block data and outputs it as an output video signal in the field order.

According to the current system video signal expansion circuit 25 thus configured, the video signal compressed by the current system video signal compression circuit 24 can be expanded and output.

In FIG. 4, the video signal from the terminal b of the switch 23 is given to the wide system video signal compression circuit 26. This input video signal is applied to the video processing circuit 4 in the field order shown in FIG. Video processing circuit 4 Shuffling circuit 31 after framed fielded data
Give to.

FIG. 10 is an explanatory view for explaining framing of the video processing circuit 4 in FIG. 10A shows input field data, and FIG. 10B shows output frame data. As shown in FIG. 10A, the odd field (ODD) has no upper and lower non-image areas O1,
O2 and main image area O, and even field (E
VEN) is composed of upper and lower non-picture areas E1 and E2 and a main picture area E. Vertical reinforcement signals (VT, VH signals) are multiplexed in the non-image areas O1, O2, E1, E2, and the horizontal reinforcement signal HH 'is added to the main image areas O and E and the luminance signal Y and color difference signals CR and CB. Is multiplexed.

The video processing circuit 4 separates the non-picture part data and the main picture part data when the inputted field data is framed. For example, the video processing circuit 4, as shown in FIG.
1, the VT and VH signals of E1 and the VT and VH signals of the lower non-image area O2 and E2 for 60 lines are continuously arranged, and the Y, CR and CB of the main image areas E and O for 360 lines are continuously arranged. , H
The H'signal is arranged continuously.

FIG. 11 is an explanatory diagram for explaining how the shuffling circuit 31 in FIG. 4 is divided into blocks. FIG. 11 (a)
Indicates a luminance block and a color difference block, and FIG.
Shows blocks for horizontal and vertical reinforcement signals.

The shuffling circuit 31 shuffles the input data, divides it into blocks of 8 × 8 pixels, and outputs the blocks to the DCT circuits 32 and 34. That is, the shuffling circuit
The main image signal 31 has four luminance blocks Y0 to Y3 and one chrominance block CR and CB arranged one at a time and outputs them to the DCT circuit 32. Also, shuffling circuit
31 shows the horizontal and vertical reinforcement signals in FIG. 11 (b).
As shown in (4), four blocks based on the vertical reinforcement signal are made continuous, and then five blocks based on the horizontal reinforcement signal are made continuous and output to the DCT circuit 34.

The DCT circuit 32 has the same configuration as the DCT circuit 6, and converts the block data of the input main picture portion signal into a frequency axis component and outputs it to the quantization circuit 33. The quantizing circuit 33 has the same configuration as that of the quantizing circuit 7, and quantizes the DCT transform coefficient using the quantizing coefficient based on FIG. 9 and outputs it to the terminal a of the switch 36.

On the other hand, the DCT circuit 34 has the same configuration as the DCT circuit 6, and converts the block data for the horizontal and vertical reinforcement signals into frequency axis components and outputs them to the quantization circuit 35. The quantization circuit 35 quantizes the DCT transform coefficient from the DCT circuit 34 and outputs it. In the present embodiment, the quantization coefficient used by the quantization circuit 35 is for weighting high frequencies.

FIG. 12 is an explanatory diagram for explaining the quantization coefficient used by the quantization circuit 35 in FIG.

Also in FIG. 12, the quantization coefficient is determined based on the area number, class number and Q number. For example, in FIG. 12, for the DCT block of class number 0, when the Q number of the macro block to which it belongs is 4, the quantized coefficients for the transform coefficients belonging to area numbers 0, 1, 2, 3 are respectively It is set to 4, 2, 2, 1. That is, the quantization coefficient based on FIG. 12 weights high frequencies. The quantized output from the quantization circuit 35 is given to the terminal b of the switch 36. The switch 36 switches and selects the terminals a and b, and outputs the block for the main picture portion signal from the quantizing circuit 33 and the block for the non-picture portion from the quantizing circuit 35 to the variable length coding circuit 8. It has become.

In the wide-system video signal compression circuit 26 thus configured, when the second-generation EDTV system video signal is input, the video processing circuit 4 and the shuffling circuit 31 respond to the main picture portion signal. It is divided into block data and block data for horizontal and vertical reinforcement signals. The block data of the main picture portion signal is converted to DC by the DCT circuit 32.
T processing is performed, and quantization is performed by the quantization circuit 33. As a result, the data of the main picture portion signal is weighted in the low frequency band, and the code amount is reduced. The quantized output is given to the variable length coding circuit 8 via the terminal a of the switch 36.

On the other hand, the block data for the horizontal and vertical reinforcement signals is given to the DCT circuit 34. The DCT circuit 34 DCT-processes the block data and supplies it to the quantization circuit 35.
The quantizing circuit 35 quantizes the transform coefficient using the quantized coefficient based on FIG. 12, that is, the quantized coefficient weighted on the high frequency side. The power of the horizontal and vertical reinforcement signals is concentrated on the conversion coefficient of a relatively high frequency, so that the quantization circuit 35 can reduce the code amount and can sufficiently transmit the horizontal and vertical reinforcement signals. The quantized output from the quantization circuit 35 is given to the variable length coding circuit 8 via the terminal b of the switch 36. The variable length coding circuit 8 performs variable length coding on the input quantized output and outputs it as a coded output.

In FIG. 5, the reproduction signal from the terminal b of the switch 28 is given to the wide system video signal expansion circuit 27. This reproduced signal is given to the variable length decoding circuit 15. The variable length decoding circuit 15 outputs the reproduction signal to the switch 37. The switch 37 gives a reproduced signal for the block data of the main picture portion signal to the inverse quantization circuit 38 via the terminal a, and a reproduced signal for the block data of the horizontal and vertical reinforcement signals at the terminal b.
To the inverse quantization circuit 40 via. The inverse quantization circuit 38 inversely quantizes the output of the variable length decoding circuit 15 using the quantization coefficient based on FIG. 9, restores the data before quantization, and outputs it to the inverse DCT circuit 39. The inverse quantization circuit 40 is a variable length decoding circuit 15
12 is inversely quantized by using the quantized coefficient based on FIG. 12 to restore the data before quantization and output to the inverse DCT circuit 41.

The inverse DCT circuits 39 and 41 are inverse quantization circuits, respectively.
By inverse DCT processing the inverse quantized outputs from 38 and 40, the frequency axis component is returned to the spatial coordinate axis component and the block data is output to the deshuffling circuit 42. The deshuffling circuit 42 deshuffles the block data, restores the pre-shuffled array, and outputs it to the video processing circuit 20. The video processing circuit 20 converts the array of frame data shown in FIG. 10B to obtain the field data shown in FIG. 10A and outputs it as an output video signal.

According to the wide-system video signal decompression circuit 27 thus configured, the wide-system video signal compression circuit
The video signal compressed by 26 can be expanded and output.

The operation of the video signal compressing device and the video signal expanding device thus constructed will be described with reference to the explanatory view of FIG. FIG. 13A shows the data format after compression of the block data for the main picture part signal, and FIG. 13B shows the data format after compression of the block data for the horizontal and vertical reinforcement signals.

At the time of compression, the video signal input through the terminal 21 is supplied to the switch 23 and also to the discrimination circuit 22. The discrimination circuit 22 discriminates the system of the input video signal and outputs a discrimination signal. When the input video signal is an NTSC system signal, the switch 23 selects the terminal a based on the discrimination signal from the discrimination circuit 22. The input video signal of the NTSC system is given to the current system video signal compression circuit 24 through the terminal a of the switch 23 to be compressed. This compression is performed by weighting the low range of the transform coefficient, and the input video signal is compressed at a sufficient compression ratio and supplied to the switch 28.

The switch 28 selects the terminal a by the discrimination signal from the discrimination circuit 22, and gives the encoded output from the current system video signal compression circuit 24 to the error correction encoding / decoding circuit 29. The error correction coding / decoding circuit 29 multiplexes the coded output and the discrimination signal that have been input, performs error correction coding, and outputs them to a recording system (not shown).

On the other hand, at the time of reproduction, the signal from the reproduction system (not shown) is error-corrected by the error correction coding / decoding circuit 29. The output of the error correction coding / decoding circuit 29 is also given to the discriminating circuit 22, and the discriminating circuit 22 outputs an identification signal indicating that it is an NTSC system signal to the switches 28 and 23. As a result, the switch 28 selects the terminal a and the reproduction signal is supplied to the current system video signal expansion circuit 25. The current system video signal decompression circuit 25 decompresses the reproduction signal by the reverse processing of the current system video signal compression circuit 24 and outputs it from the terminal 21 via the switch 23.

On the other hand, when the input video signal input to the terminal 21 is the signal of the second generation EDTV system, the switches 23 and 28 select the terminal b according to the determination signal. The video signal of the second generation EDTV system is supplied to the wide system video signal compression circuit 26. The wide system video signal compression circuit 26 weights the block data for the main picture portion signal in the low frequency range and compresses it. On the contrary, the wide format video signal compression circuit 26
Block data for horizontal and vertical reinforcement signals are weighted in a high frequency range and compressed.

That is, as shown in FIG. 11A, the shuffling circuit 31 of the wide-system video signal compression circuit 26 has four luminance blocks corresponding to the luminance signal and the color difference signal of the main image portion signal and each one. The respective color difference blocks are continuously arranged and output to the DCT circuit 32. Also, shuffling circuit
31 is a vertical reinforcement signal (V
DCT circuit in which four blocks for T, VH signals) and six blocks for horizontal reinforcement signals are continuously arranged
Output to 34. The DCT circuits 32 and 34 perform DCT processing on the input block data and output transform coefficients. These transform coefficients are quantized by the quantization circuits 33 and 35, respectively.
In this case, the quantization circuit 33 uses the low-frequency weighted quantization coefficient, and the quantization circuit 35 uses the high-frequency weighted quantization coefficient. As a result, it is possible to sufficiently reduce the amount of data and obtain horizontal and vertical reinforcement signals with sufficient power.

The outputs of the quantizing circuits 33 and 35 are transmitted in the same format. That is, as shown in FIG. 13A, the output of the quantization circuit 33 is coded in macroblock units composed of six blocks, and the output of the quantization circuit 33 is also shown in FIG. 13B. As described above, encoding is performed for every 6 blocks, that is, a block for four vertical reinforcement signals and a block for two horizontal reinforcement signals. The outputs of the quantizing circuits 33 and 35 are given to the variable length coding circuit 8 via the switch 36 and variable length coded and outputted. The compressed data of the wide-system video signal compression circuit 26 is given to the error correction coding / decoding circuit 29 via the switch 28, multiplexed with the discrimination signal and then error correction coded to be output to the recording system.

On the other hand, at the time of reproduction, the reproduction signal from the reproduction system is error correction decoded by the error correction coding / decoding circuit 29. In this case, the switches 23 and 28 select the terminal b by the discrimination signal from the discrimination circuit 22. The reproduced signal is given to the wide type video signal decompression circuit 27 to be decompressed and output via the switch 23.

At the time of recording, the block data for the horizontal and vertical reinforcement signals are weighted in the high frequency range and compressed, and the high frequency components are recorded with sufficient power. Therefore, at the time of reproduction, since the horizontal and vertical reinforcement signals can be reproduced without deterioration, the quality of the reproduced image can be improved.

[0074]

As described above, according to the present invention, it is possible to obtain a reproduced image with sufficient image quality even when the second generation EDTV signal is compressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a video signal compression device and a video signal expansion device according to the present invention.

FIG. 2 is a block diagram showing a specific configuration of a current system video signal compression circuit in FIG.

FIG. 3 is a block diagram showing a specific configuration of a current system video signal expansion circuit in FIG.

FIG. 4 is a block diagram showing a specific configuration of a wide-type video signal compression circuit in FIG.

5 is a block diagram showing a specific configuration of a wide system video signal expansion circuit in FIG. 1. FIG.

FIG. 6 is an explanatory diagram for explaining zigzag scanning.

FIG. 7 is an explanatory diagram for explaining quantized coefficients.

FIG. 8 is an explanatory diagram for explaining area numbers.

FIG. 9 is an explanatory diagram for explaining quantized coefficients.

FIG. 10 is an explanatory diagram for explaining the video processing circuit in FIG. 4.

11 is an explanatory diagram for explaining the shuffling circuit in FIG. 4. FIG.

FIG. 12 is an explanatory diagram for explaining quantized coefficients.

FIG. 13 is an explanatory diagram for explaining the operation of the embodiment.

[FIG. 14] The current NT for the letterbox format video signal
Explanatory drawing which shows the screen display at the time of receiving with a television receiver of SC system.

FIG. 15 is an explanatory diagram for explaining a multiplexed state of horizontal and vertical reinforcement signals.

FIG. 16 is a block diagram showing a digital VTR incorporating a conventional video signal compression device and video signal expansion device.

FIG. 17 is an explanatory diagram showing blocking.

FIG. 18 is an explanatory diagram showing the structure of a macro block.

[Explanation of symbols]

22 ... Discrimination circuit, 23, 28 ... Switch, 24 ... Current system video signal compression circuit, 25 ... Current system video signal decompression circuit, 26 ...
Wide system video signal compression circuit, 27 ... Wide system video signal decompression circuit, 29 ... Error correction encoding / decoding circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takehiko Okuyama 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Inside the Multimedia Technology Laboratory, Toshiba Corporation (72) Minoru Yoneda 8 Shinsita-cho, Isogo-ku, Yokohama-shi, Kanagawa Incorporated company Toshiba Multimedia Technology Laboratory (72) Inventor Takashi Terui 8 Shinsita-cho, Isogo-ku, Yokohama City, Kanagawa Prefecture Incorporated Toshiba Multimedia Technology Laboratory (72) Inventor Yoshihisa Sakazaki Shinsugita-cho, Isogo-ku, Yokohama City, Kanagawa Prefecture 8 Incorporated Toshiba Corporation Multimedia Technology Laboratory (72) Inventor Shuji Abe 8 Shinsita-cho, Isogo-ku, Yokohama-shi Kanagawa Inside Toshiba Multimedia Technology Laboratory

Claims (6)

[Claims] 1. A discriminating unit which receives an input video signal based on a wide aspect television signal or a non-wide aspect television signal, discriminates a system of the input video signal, and outputs a discrimination result, and the non-wide aspect television. Non-wide format video signal compression means for compressing a signal, wide format video signal compression means for compressing the wide aspect television signal, output of the non-wide format video signal compression means or for the wide format video signal A video signal compression apparatus comprising: a selection means for selectively outputting the output of the compression means; and a multiplexing means for multiplexing the output of the selection means and the discrimination result and outputting a multiplexed signal. 2. The wide aspect television signal is multiplexed with a vertical reinforcement signal for improving the vertical resolution of the main picture portion during the non-picture portion period, and horizontal reinforcement for improving the horizontal resolution during the main picture portion period. The video signal compression apparatus according to claim 1, wherein the video signal is a second-generation EDTV video signal in which signals are multiplexed and an identification signal indicating a system is multiplexed. 3. The video signal compression apparatus according to claim 1, wherein the discrimination means discriminates a system of the input video signal based on the identification signal. 4. The wide-type video signal compression means comprises:
3. The video signal compression apparatus according to claim 2, further comprising a compression circuit that compresses the wide aspect television signal so as to transmit power in a higher frequency band than a low frequency band. 5. The wide type video signal compression means comprises:
Orthogonal transformation means for orthogonally transforming the wide aspect television signal and outputting a transformation coefficient, and for the transformation coefficient corresponding to the luminance signal and the color difference signal of the main image section, to transmit power in a lower frequency band than in a high frequency band. First quantizing means for weighting and quantizing, and for transform coefficients corresponding to the horizontal reinforcing signal and the vertical reinforcing signal, weighting and quantizing so as to transmit power in a higher frequency band than in a lower frequency band. The video signal compression apparatus according to claim 2, further comprising: two quantization means. 6. A compressed signal for a wide aspect television signal or a non-wide aspect television signal and whether the compressed signal is based on a wide aspect television signal or a non-wide aspect television signal. A non-wide video signal expansion unit for inputting a multiplex signal including a determination signal for determining, and expanding the compressed signal for the non-wide aspect television signal to obtain the non-wide aspect television signal; A wide-system video signal expansion unit that receives a signal and expands a compressed signal for the wide-screen television signal to obtain the wide-aspect television signal; and the non-wide-screen system based on the determination signal included in the multiplex signal. Output of video signal expansion means or Video signal decompression apparatus being characterized in that; and a switching means for outputting the switched output of the system video signal decompression means.