JPH08329677A - Power supply voltage detecting device in semiconductor device and semiconductor device - Google Patents

Abstract

(57) [Summary] [Purpose] To enable selection of appropriate circuits or operations according to the power supply voltage. [Structure] The voltage detection circuit 20 detects whether or not the power supply voltage exceeds a reference voltage, and outputs the detection result as a voltage detection signal. The word line boosting circuit 14 operates only when the power supply voltage is equal to or lower than the reference voltage according to the voltage detection signal, and the dummy cell driver 15 operates only when the power supply voltage exceeds the reference voltage according to the voltage detection signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply voltage detecting device for detecting a power supply voltage in a semiconductor device and a semiconductor device including the power supply voltage detecting device.

[0002]

2. Description of the Related Art In recent years, a semiconductor device such as a semiconductor memory is required to have a wide circuit operation margin with respect to a power supply voltage as the power supply voltage used is widened (lowered). In this case, the circuit design is focused on guaranteeing the operation on the low voltage side.

[0003]

Conventionally, for example, a booster circuit has been used as a means for ensuring the operation of the semiconductor device on the low voltage side. However, in the conventional booster circuit, if the boosted potential (the magnitude of the voltage to be boosted) is set according to the case where the power supply voltage is low, there is a problem that the potential is raised more than necessary when the power supply voltage is high. It was

Further, in the output circuit of the conventional semiconductor memory or the like, a large size transistor is required as the output stage transistor in order to guarantee the operation on the low voltage side. However, in this case, when the power supply voltage is high, the through current of the transistor becomes large, and this through current becomes noise, which causes deterioration of the operation margin of not only the semiconductor device itself but also the external circuit.

Further, when the circuit is designed so as to guarantee the operation on the low voltage side, when the power supply voltage is high, the current consumption of the circuit increases more than necessary, and the specifications of the semiconductor device only deteriorate. However, there is a problem that the operation margin on the high voltage side is insufficient and the amount of heat generation increases. Conventionally, this problem has been dealt with by, for example, manually switching an external terminal by a user or a down converter (step-down circuit). However, the switching of the external terminals is to specify the power supply voltage in effect,
There is a problem that the operation is complicated. On the other hand, the down converter has a complicated circuit configuration, and has a problem that the design and manufacturing process is difficult.

The present invention has been made in view of the above problems, and a first object thereof is to detect the power supply voltage of the semiconductor device so that the semiconductor device can select an appropriate circuit or operation according to the power supply voltage. An object is to provide a power supply voltage detection device for a semiconductor device.

A second object of the present invention is to provide a semiconductor device in which an appropriate circuit or operation can be selected according to the power supply voltage.

[0008]

According to a first aspect of the present invention, there is provided a power supply voltage detecting device for a semiconductor device, wherein the power supply voltage detecting means generates a substantially constant comparison potential within a predetermined power supply voltage range regardless of the power supply voltage. And a detection unit that detects whether or not the power supply voltage exceeds a predetermined voltage by comparing the potential that changes according to the power supply voltage with the comparison potential generated by the comparison potential generation unit. It is a thing.

According to a second aspect of the present invention, there is provided a power source voltage detecting device for a semiconductor device according to the first aspect, wherein the detecting means inputs the comparison potential generated by the comparison potential generating means, and compares the comparison potential. It is configured to have a logic circuit that outputs different logic values depending on the magnitude relation between the working potential and the logic threshold value that changes according to the power supply voltage.

According to another aspect of the semiconductor device of the present invention, a comparison potential generating means for generating a substantially constant comparison potential within a predetermined power supply voltage range regardless of the power supply voltage, and a potential changing according to the power supply voltage. Detection means for detecting whether or not the power supply voltage exceeds a predetermined voltage by comparing with the comparison potential generated by the comparison potential generation means, and a circuit to be used based on the detection result of this detection means Alternatively, a selection means for selecting an operation is provided.

According to a fourth aspect of the present invention, there is provided a semiconductor device according to the third aspect, wherein the selection means is a dynamic circuit.
In the random access memory, when the power supply voltage exceeds a predetermined voltage, the dummy cell driver that drives the dummy cell is operated, and when the power supply voltage does not exceed the predetermined voltage, the word line potential is boosted. It is configured to operate the word line boosting circuit.

According to a fifth aspect of the present invention, in the semiconductor device according to the third aspect, the selecting means, in the step-up circuit for stepping up the power supply voltage, sets the magnitude of the step-up voltage based on the detection result of the detecting means. It is configured to be selected.

According to a sixth aspect of the present invention, in the semiconductor device according to the third aspect, the selecting means is an output circuit for outputting a digital signal, and in accordance with a value of the digital signal based on a detection result of the detecting means. It is configured to selectively select the number of transistors that allow current to pass.

According to a seventh aspect of the present invention, in the semiconductor device according to the third aspect, the selecting means selects the number of transistors through which a current for supplying to the logic circuit passes, based on the detection result of the detecting means. It is configured to do.

[0015]

In the power supply voltage detecting device in the semiconductor device according to the first aspect of the invention, the comparison potential generating means generates a substantially constant comparison potential within the predetermined power supply voltage range regardless of the power supply voltage, and the detecting means. The potential changing according to the power supply voltage is compared with the comparison potential generated by the comparison potential generation means to detect whether the power supply voltage exceeds a predetermined voltage. In the power supply voltage detection device in the semiconductor device according to claim 2, the logic circuit as the detection means receives the comparison potential generated by the comparison potential generation means and changes according to the comparison potential and the power supply voltage. A different logical value is output according to the magnitude relationship with the logical threshold value.

According to another aspect of the semiconductor device of the present invention, the comparison potential generation means generates a substantially constant comparison potential within the predetermined power supply voltage range regardless of the power supply voltage, and the detection means responds to the power supply voltage. The potential that changes as a result of comparison is compared with the comparison potential generated by the comparison potential generation means to detect whether the power supply voltage exceeds a predetermined voltage, and based on the detection result of this detection means, the selection means. By
The circuit or operation used is selected. According to another aspect of the semiconductor device of the present invention, in the dynamic random access memory, the selecting means operates a dummy cell driver that drives a dummy cell when the power supply voltage exceeds a predetermined voltage, and the power supply voltage is predetermined. If the voltage does not exceed the voltage, the word line boosting circuit that boosts the potential of the word line is operated. According to another aspect of the semiconductor device of the present invention, in the booster circuit for boosting the power supply voltage, the selecting means selects the magnitude of the boosting voltage based on the detection result of the detecting means. In the semiconductor device according to claim 6, in the output circuit that outputs the digital signal, the selection means selects the number of transistors that selectively pass the current according to the value of the digital signal based on the detection result of the detection means. To do. According to another aspect of the semiconductor device of the present invention, the selecting means selects the number of transistors through which the current for supplying to the logic circuit passes, based on the detection result of the detecting means.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a semiconductor device including a power supply voltage detecting device according to the first embodiment of the present invention. In this embodiment, a DRAM (dynamic
This is an example applied to a row address control system of a random access memory).

As shown in FIG. 1, DR in this embodiment
AM is an address buffer 11 for latching an address signal AX ₀ ~AX _n, the word lines of the memory cell array (not shown) decodes a row address based on the address signal XA ₀ ~XA _n latched in the address buffer 11 An address decoder 12 that outputs a decoder signal for selection, a word line driver 13 that drives a word line of the memory cell array according to the decoder signal from the address decoder 12, and a word line booster circuit that boosts the potential of the word line. 14, a dummy cell driver 15 for driving a dummy cell, and a row address strobe signal R
It is provided with an RAS system timing generator 16 for inputting ASB and generating a timing signal for an address buffer 11, an address decoder 12, a word line driver 13, a word line booster circuit 14 and a dummy cell driver 15. The DRAM in this embodiment further includes an R
A voltage detection circuit 20 is provided as a detection means that receives a timing signal from the AS-system timing generator 16 and detects whether or not the power supply voltage exceeds a predetermined voltage.

FIG. 2 is a circuit diagram showing the configuration of the voltage detection circuit 20 shown in FIG. The voltage detection circuit 20 includes a voltage detection unit 21 and an output holding unit 22. The voltage detection unit 21 receives the input signal IN, which is the timing signal from the RAS system timing generator 16, as the buffer 2
3 and an inverter 2 for inputting the output of the buffer 23
4 and an nMOS transistor 25 having a drain connected to a point which is a connection point between the buffer 23 and the inverter 24.
It has and. The source of the transistor 25 is grounded, and the gate is connected to the drain. Buffer 23
Is composed of two inverters connected in series.
The buffer 23 and the transistor 25 correspond to the comparison potential generating means in the present invention, and the inverter 24 corresponds to the detecting means in the present invention.

The output holding unit 22 includes a transfer gate 26 for selectively passing the output of the buffer 24 and an inverter 27 for inputting the input signal IN. The transfer gate 26 includes a pMOS transistor and an nMO.
It is configured by connecting the drain and the source of the S transistor and the source and the drain. The output of the inverter 27 is applied to the gate of the pMOS transistor, and nM
The input signal IN is applied to the gate of the OS transistor. The output holding unit 22 further includes an inverter 28 that inputs the output of the transfer gate 26,
An inverter 29 whose input end is connected to the output end of the inverter 28 and whose output end is connected to the input end of the inverter 28.
And an inverter 30 for inputting the output of the inverter 28. The output of the inverter 30 is the voltage detection circuit 2
The voltage detection signal DS is an output signal of 0.

Next, the operation of the voltage detection circuit 20 shown in FIG. 2 will be described with reference to FIGS. 3 and 4.

In the voltage detector 21, when the input signal IN goes to the "H" level, the buffer 23 and the transistor 25 cause a substantially constant comparison potential v at the point a within a predetermined power supply voltage range regardless of the power supply voltage. ₂ is generated. The relationship between the power supply voltage and the potential at the point a is indicated by reference numeral 31 in FIG. The range of the power supply voltage is, for example, 1.5 to 4 V, and the potential at the point a is substantially constant (v ₂ ) in this range. The size of the comparison potential v ₂ is the buffer 23 and the transistor 2
It can be controlled by the capability of 5 (size of passing current). On the other hand, the logical threshold value of the inverter 24 is as shown in FIG.
As indicated by reference numeral 32, the higher the power supply voltage, the higher the power supply voltage. Here, the magnitude of the power supply voltage when the logical threshold value of the inverter 24 matches the comparison potential v ₂ is set as the reference voltage v ₁ . The magnitude of the reference voltage v ₁ can be controlled by the number of stages in which the transistor 25 is connected in series. When the power supply voltage is the reference voltage v ₁ or less, the logic threshold value of the inverter 24 becomes the comparison potential v ₂ or less, the output of the inverter 24 for inputting the comparison potential v ₂ becomes "L" level. On the other hand, when the power supply voltage exceeds the reference voltage v ₁ , the logic threshold value of the inverter 24 exceeds the comparison potential v ₂ and the output of the inverter 24 becomes the “H” level.

In the output holding section 22, the transfer gate 26 passes the output of the voltage detecting section 21 (the output of the inverter 24) when the input signal IN is at "H" level. The inverters 28 to 30 form an inverter type latch circuit, hold the output of the voltage detection unit 21 that has passed through the transfer gate 26 until the transfer gate 26 is opened next time, and output it as the voltage detection signal DS.

FIG. 4 shows the waveform of each part of the voltage detection circuit 20 when the power supply voltage V _cc exceeds the reference voltage v ₁ . In this figure, reference numeral 33 indicates the potential at point a, and 34 indicates the logical threshold value of the inverter 24. In the example shown in this figure, since the logical threshold value 34 of the inverter 24 exceeds the comparison potential v ₂ , the output of the inverter 24 becomes the “H” level and the voltage detection signal output from the voltage detection circuit 20. DS is also at "H" level.

By the above operation, the voltage detection circuit 20 becomes
When the power supply voltage is lower than the reference voltage v ₁ , the voltage detection signal D
"L" level is output as S and the power supply voltage is the reference voltage v
When exceeding ₁ , "H" as voltage detection signal DS
Output level. The voltage detection signal DS is input to the word line boosting circuit 14 and the dummy cell driver 15. In this embodiment, the word line boosting circuit 14 outputs the voltage detection signal DS
Accordingly, the dummy cell driver 15 operates only when the power supply voltage is equal to or lower than the reference voltage v ₁ , and the dummy cell driver 15 operates only when the power supply voltage exceeds the reference voltage v ₁ according to the voltage detection signal DS. This is because the dummy cell driver 15 is suitable when the power supply voltage is high and prevents the potential of the word line from being unnecessarily increased when the power supply voltage is high.

FIG. 5 shows the word line driver 1 in FIG.
3 is a circuit diagram showing the configurations of the word line boosting circuit 3 and the word line boosting circuit 14. In addition, in FIG. 5, regarding the word line driver 13,
Only the portion corresponding to one word line is shown. The word line boosting circuit 14 has an inverter 41 for receiving the voltage detection signal DS from the voltage detecting circuit 20 and a NAND gate for receiving the output of the inverter 41 and the boosting signal S ₁ from the RAS system timing generator 16. 42, inverters 43 and 44 for inputting the output of the NAND gate 42, a pMOS transistor 45,
The boosting capacitor 46 has one end connected to the output end of the inverter 44. A power supply voltage _Vcc is applied to the source of the transistor 45, the gate is connected to the output terminal of the inverter 43, and the drain is connected to the other end of the boosting capacitor 46. The inverter 41 and the NAND gate 42 correspond to a part of the selection means in the present invention.

The word line drivers 13 are CMOs, respectively.
The inverters 47 and 48 configured by S are provided. The decoder signal S ₂ from the address decoder 12 is input to the input terminal of the inverter 47. The output terminal of the inverter 47 is connected to the input terminal of the inverter 48, and the output terminal of the inverter 48 is connected to a word line of a memory cell array (not shown). Each inverter 47,
The source of the pMOS transistor 48 is connected to the word line driver power supply line 49, and the inverters 47 and 4 are connected.
The source of the nMOS transistor 8 is grounded.
The word line driver power supply line 49 is connected to a connection point between the transistor 45 and the boosting capacitor 46 in the word line boosting circuit 14.

The operation of the word line boosting circuit 14 and the word line driver 13 shown in FIG. 5 will be described with reference to the timing chart of FIG. The boosting signal S ₁ becomes “H” level when the row address is decoded. When the power supply voltage exceeds the reference voltage v ₁ , that is, when the voltage detection signal DS is at “H” level, regardless of whether the boost signal S ₁ is at “H” level or “L” level, The output a _{1 of the} NAND gate 42 becomes "H" level (FIG. 6 (a)). At this time, the output b ₁ of the word line boosting circuit 14, that is, the power supply line 49 for the word line driver
Is the power supply voltage _Vcc (FIG. 6 (b)). On the other hand, when the power supply voltage is equal to or lower than the reference voltage v ₁ , that is, when the voltage detection signal DS is at “L” level, the output a of the NAND gate 42 is output only when the boost signal S ₁ is at “H” level.
₁ becomes "L" level (FIG. 6 (a)). At this time,
The output b ₁ of the word line boosting circuit 14, that is, the potential of the word line driver power supply line 49 becomes a boosted potential by adding the amount of discharge from the boosting capacitor 46 to the power supply voltage V _cc (FIG. 6 (b )). Word line driver 13, the decoder signal S ₂ becomes "H" level (FIG. 6 (c)), the potential of the word line "H" to level (FIG. 6 (d)). At this time, the potential of the word line becomes the potential of the power supply line 49 for word line driver. With the above operation, the potential of "H" level when the word line, the potential is boosted when next supply voltage V _cc, the power supply voltage of the reference voltage v ₁ below when the power supply voltage exceeds the reference voltage v ₁ Become.

FIG. 7 is a circuit diagram showing configurations of dummy cell driver 15 and dummy cells in FIG. Note that FIG. 7 shows only the dummy cells 60 corresponding to one bit line pair bar BL _n , BL _n . The dummy cell driver 15 includes a RAS timing generator 16
AND gate 5 for inputting the dummy cell signal S ₃ from the voltage detection circuit 20 and the voltage detection signal DS from the voltage detection circuit 20.
1, inverters 52 and 53 for inputting the output of the AND gate 51, and an inverter 54 for inputting the output of the inverter 52. The AND gate 51 corresponds to a part of the selection means in the present invention.

The dummy cell 60 has a MOS transistor 61 having a drain connected to the bit line BL _n on the reference side, a capacitor 62 having one end connected to the source of the transistor 61, and a drain connected to the source of the transistor 61. And a MOS transistor 63. The gate of the transistor 61 is connected to the output terminal of the inverter 54 of the dummy cell driver 15. The capacitor 62 has, for example, a half capacity of the storage capacity of the memory cell, and the plate potential is applied to the other end. The gate of the transistor 63 is connected to the output terminal of the inverter 53 of the dummy cell driver 15, and the source is grounded.

The operation of the dummy cell driver 15 and the dummy cell 60 shown in FIG. 7 will be described with reference to the timing chart of FIG. Dummy cell driver 1
5 is operated by the AND gate 51 only when the voltage detection signal DS from the voltage detection circuit 20 is at "H" level. When the dummy cell driver 15 is not operated, the output a _{2 of the} inverter 54 is at "L" level and the output b _{2 of the} inverter 53 is at "H" level (see FIG. 8).
(A), (b)), the transistor 61 is turned off, the potential c ₂ of the bit line bar BL _n and the potential d of the bit line BL _n .
₂ are equal (FIG. 8 (c)). Voltage detection signal D
When S is at "H" level, the dummy cell signal S ₃
If There becomes "H" level, first, as an output b ₂ is "L" level of the inverter 53 (FIG. 8 (b)), the transistor 63 is turned off, a little later, output a ₂ of the inverter 54 becomes " At the H "level (FIG. 8A), the transistor 61 is turned on, the reference side bit line bar BL _n is connected to the capacitor 62, and the potential c ₂ of the bit line bar BL _n decreases (FIG. 8). (C)). The charge charged in the capacitor 62 is discharged the next time the transistor 63 is turned on.

By the above operation, the dummy cell driver 1
5 is operated only when the power supply voltage exceeds the reference voltage v ₁ . When using the dummy cell driver 15, word line boosting is not performed. Therefore, the data amount of the memory cell at the time of data “1” may be insufficient. Accordingly, and to lower the potential of the bit line bar BL _n of the reference side by the above-described operation.

As described above, according to this embodiment,
The voltage detection circuit 20 automatically detects whether or not the power supply voltage exceeds the reference voltage v ₁ , and automatically selects an appropriate circuit (word line booster circuit 14, dummy cell driver 15) according to the power supply voltage. can do. As a result, there is no need to guarantee a wide range of power supply voltage margin in one circuit as in the conventional case.

Further, the voltage detection circuit 20 according to the present embodiment.
Can be composed of a usual simple logic circuit. Further, since the voltage detection circuit 20 detects the power supply voltage using the pulse signal from the RAS system timing generator 16, the through current is small and the current consumption can be reduced as compared with the case where the power supply voltage is constantly detected. .

Next, a second embodiment of the present invention will be described with reference to FIGS. The present embodiment is an example in which the present invention is applied to a booster circuit that boosts a power supply voltage.

First, for comparison with this embodiment, a conventional booster circuit will be described with reference to FIG. The booster circuit includes an inverter 171 that receives the boosted signal S ₄ and an inverter 172 that receives the output of the inverter 171.
And a power supply voltage is applied to the source and a gate is connected to the output terminal of the inverter 172.
3 and a boosting capacitor 174 having one end connected to the output end of the inverter 172 and the other end connected to the drain of the transistor 173. The drain potential of the transistor 173 becomes the output OUT of the booster circuit. In this booster circuit, if the boosted potential (the magnitude of the voltage to be boosted) is set according to the case where the power supply voltage is low, there is a problem that the potential is raised more than necessary when the power supply voltage is high. In addition, with the miniaturization of semiconductor devices, the gate breakdown voltage of transistors becomes a problem. In order to deal with this, as shown in FIG. 9, there is also one in which a pMOS transistor 145 for clamping is provided in the output stage. This transistor 145
Has a drain connected to the drain of the transistor 173, and a power supply voltage is applied to its gate and source.
The transistor 145 is for suppressing the potential increase by causing a current to flow from the drain side to the source side when the potential of the output OUT of the booster circuit rises excessively, but the effect is actually small.

FIG. 10 is a circuit diagram showing the structure of the booster circuit according to this embodiment. This booster circuit can be used as the word line booster circuit 14 in FIG. 1, for example.
This booster circuit includes an inverter 7 for inputting a booster signal S _4.
1 and an inverter 72 for inputting the output of the inverter 71, a power supply voltage is applied to the source, and a pMOS transistor 7 whose gate is connected to the output terminal of the inverter 72
3 and a boosting capacitor 74a having one end connected to the output end of the inverter 72 and the other end connected to the drain of the transistor 73. The potential of the drain of the transistor 73 becomes the output OUT of the booster circuit. The booster circuit of this embodiment further includes two boosting capacitors 74b and 74c.
And an inverter 77 for inputting the voltage detection signal DS from the voltage detection circuit 20 shown in FIG. 2, and four MOS transistors 75a, 75b, 76a, 76b whose gates are connected to the output terminals of the inverter 77, respectively. ing. One of the source and the drain of the transistor 75a is connected to the output terminal of the inverter 72, and the other is connected to the boosting capacitor 7a.
It is connected to one end of 4b. One of the source and the drain of the transistor 75b is connected to the drain of the transistor 73, and the other is connected to the other end of the boosting capacitor 74b. One of the source and the drain of the transistor 76a is connected to the output end of the inverter 72, and the other is connected to one end of the boosting capacitor 74c. One of the source and the drain of the transistor 76b is connected to the drain of the transistor 73, and the other is connected to the other end of the boosting capacitor 74c. The boosting capacitors 74a, 74b, 74c, the transistors 75a, 75b, 76a, 76b and the inverter 77 correspond to the selecting means in the present invention.

Next, the operation of the booster circuit in this embodiment will be described. The boosting signal S ₄ becomes “H” level when boosting. When the boost signal S ₄ is at “H” level,
When the power supply voltage is equal to or lower than the reference voltage v ₁ , that is, when the voltage detection signal DS is at “L” level, the transistor 75
a, 75b, 76a, 76b are turned on, and all three boosting capacitors 74a, 74b, 74c are used. On the other hand, when the boosted signal S ₄ is at “H” level and the power supply voltage exceeds the reference voltage v ₁ , that is, when the voltage detection signal DS is at “H” level, the transistor 7
5a, 75b, 76a and 76b are turned off, and only the boosting capacitor 74a is used.

By the above operation, reference numeral 7 in FIG.
In the conventional booster circuit, as shown by 8, the boosted potential continuously increases as the power supply voltage increases, whereas in the booster circuit of the present embodiment, as shown by reference numeral 79, the power supply voltage is the reference voltage v ₁ When it exceeds, the boosted potential is suppressed to a low level and the potential is prevented from being raised more than necessary. Other configurations, operations and effects are similar to those of the first embodiment.

Next, a third embodiment of the present invention will be described with reference to FIGS. In this embodiment, the DRA
It is an example in which the present invention is applied to an output circuit that outputs a digital signal such as an output circuit in M.

First, for comparison with the present embodiment, FIG.
A conventional output circuit will be described using. This output circuit has an inverter 181 for inputting a digital signal D.
An inverter 182 for inputting the output of the inverter 181, an inverter 183 for inputting the output of the inverter 182, a MOS transistor 184 having a gate connected to the output end of the inverter 182, and a gate for the output end of the inverter 183. And a connected MOS transistor 185. A power supply voltage is applied to the drain of the transistor 184, the source of the transistor 184 is connected to the drain of the transistor 185, and the source of the transistor 185 is grounded. Transistor 1
The source of 84 and the drain of transistor 185 are connected to output 186.

In this output circuit, when the digital signal D is at "L" level, the transistor 184 is turned off,
The transistor 185 is turned on, and the potential of the output terminal 186 becomes "L" level. On the other hand, when the digital signal D is at "H" level, the transistor 184 turns on,
The transistor 185 is turned off, and the potential of the output terminal 186 becomes "H" level. In this output circuit, in order to guarantee operation on the low voltage side, transistors 184 and 185 are provided.
Was used as a large size. Therefore, when the power supply voltage is high, the transistors 184, 18
The through current of No. 5 becomes large, and this through current becomes noise, and there is a problem in that not only the semiconductor device itself but also the operating margin of the external circuit deteriorates.

FIG. 13 is a circuit diagram showing the structure of the output circuit in this embodiment. This output circuit includes an inverter 81 that receives the digital signal D, an inverter 82 that receives the output of the inverter 81, and an inverter 82.
And an MOS transistor 84a whose gate is connected to the output terminal of the inverter 82.
And a gate whose gate is connected to the output terminal of the inverter 83
S-transistor 85a. The output circuit of this embodiment further receives an AND gate 87 for receiving the output of the inverter 82 and the voltage detection signal DS from the voltage detection circuit 20 shown in FIG. 2, and an output of the inverter 83 and the voltage detection signal DS. The AND gate 88 includes a MOS transistor 84b having a gate connected to the output terminal of the AND gate 87, and a MOS transistor 85b having a gate connected to the output terminal of the AND gate 88. A power supply voltage is applied to the drains of the transistors 84a and 84b, the sources of the transistors 84a and 84b are connected to the drains of the transistors 85a and 85b, and the sources of the transistors 85a and 85b are grounded. Sources of transistors 84a and 84b and transistor 85
The drains of a and 85b are connected to the output terminal 86.
Transistors 84b and 85b and an AND gate 87,
88 corresponds to the selection means in the present invention.

Next, the operation of the output circuit in this embodiment will be described. When the power supply voltage is below the reference voltage v ₁ ,
That is, when the voltage detection signal DS is at "L" level,
The transistors 84b and 85b are always off. In this state, when the digital signal D is "L" level, the transistor 84a is turned off, the transistor 85a is turned on, the potential of the output terminal 86 is "L" level, and when the digital signal D is "H" level, the transistor 84a is turned on. 8
4a is turned on, the transistor 85a is turned off, and the potential of the output terminal 86 becomes "H" level. On the other hand, when the power supply voltage exceeds the reference voltage v ₁ , that is, the voltage detection signal D
When S is "H" level, digital signal D is "L"
When the level is high, the transistors 84a and 84b are off, the transistors 85a and 85b are on, the potential of the output terminal 86 is at the "L" level, and when the digital signal D is at the "H" level, the transistors 84a and 84b.
Is turned on, the transistors 85a and 85b are turned off, and the potential of the output terminal 86 becomes "H" level.

With the above operation, in the output circuit of this embodiment, the number of the transistors 84a, 84b, 85a, 85b that selectively pass the current is selected based on the voltage detection signal DS in accordance with the value of the digital signal. To be done. As a result, in the conventional output circuit, as shown by reference numeral 89 in FIG.
The through currents of Nos. 4 and 185 also continuously increase, while in the output circuit of this embodiment, as indicated by reference numeral 90,
When the power supply voltage exceeds the reference voltage v ₁ , the transistor 84
a, 84b, 85a, 85b has a through current of 1/2
It can be kept low. Other configurations, operations and effects are similar to those of the first embodiment.

Next, a fourth embodiment of the present invention will be described with reference to FIGS. The present embodiment is an example in which the present invention is applied to a logic circuit.

First, for comparison with the present embodiment, FIG.
A conventional logic circuit will be described with reference to FIG. FIG. 15 shows an example of a buffer in which inverters 191 and 192 are connected in series as a logic circuit. In this buffer, the output signal S ₁₆ of the inverter 192 is
It has the same logical value as the input signal S _{15 of} 91. In such a conventional logic circuit, when the circuit is designed so as to guarantee the operation on the low voltage side, there is a problem that the current consumption of the circuit increases more than necessary when the power supply voltage is high.

FIG. 16 is a circuit diagram showing the structure of the logic circuit in this embodiment. This figure shows an example of a buffer as a logic circuit. This logic circuit has an input signal S
An inverter 91 for inputting ₅ and an inverter 92 for inputting the output of the inverter 91 and outputting an output signal S ₆ are provided. The logic circuit of this embodiment further includes a pMOS transistor 93 whose gate is grounded.
a and 94a, and the voltage detection circuit 20 shown in FIG.
PMOS transistors 93b and 94b to which the voltage detection signal DS from is applied. Transistor 93
A power supply voltage is applied to the sources of a, 93b, 94a, and 94b. The drains of the transistors 93a and 93b are connected to the source of the depletion type pMOS transistor of the inverter 91. Transistor 94
The drains of a and 94b are connected to the source of the depletion type pMOS transistor of the inverter 92. The transistors 93a, 93b, 94a, 94b correspond to the selecting means in the present invention.

Next, the operation of the logic circuit in this embodiment will be described. The transistors 93a and 94a are always on. When the power supply voltage is below the reference voltage v ₁ ,
That is, when the voltage detection signal DS is at "L" level,
Further, the transistors 93b and 94b are also turned on.
In this state, the inverter 91 has a transistor 93
The current that has passed through a and 93b is supplied to the inverter 92
Is supplied with the current that has passed through the transistors 94a and 94b. On the other hand, when the power supply voltage exceeds the reference voltage v ₁ , that is, when the voltage detection signal DS is at "H" level, the transistors 93b and 94b are off.
In this state, the inverter 91 has a transistor 93a.
The current that has passed through only the transistor 94a is supplied to the inverter 92. The output signal S ₆ of the inverter 92 is
Has the same logical value as that of the input signal S ₅ of.

According to the above operation, in this embodiment, the number of transistors that pass the current for supplying to the logic circuit is selected based on the voltage detection signal DS. As a result, as shown in FIG. 17, in the conventional logic circuit, the current consumption of the logic circuit continuously increases as the power supply voltage increases, whereas in the logic circuit of the present embodiment, as shown in FIG. When the power supply voltage exceeds the reference voltage v ₁ , the transistors 93b and 94b are turned off, and the current consumption of the logic circuit can be suppressed low. Other configurations, operations and effects are similar to those of the first embodiment.

The present invention is not limited to the above embodiments, and for example, the voltage detection circuits 20 having different reference voltages from each other.
It is also possible to provide a plurality of types, classify the power supply voltage into three or more types, and select three or more types of circuits or operations according to the power supply voltage.

[0053]

As described above, according to the power supply voltage detecting device in the semiconductor device of the first aspect, the comparison potential generating means allows a substantially constant comparison within the predetermined power supply voltage range regardless of the power supply voltage. A potential for use is generated, and the detection means compares the potential which changes according to the power supply voltage with the potential for comparison generated by the comparison potential generation means to detect whether or not the power supply voltage exceeds a predetermined voltage. Therefore, there is an effect that the power supply voltage of the semiconductor device can be detected so that the semiconductor device can select an appropriate circuit or operation according to the power supply voltage.

According to the power supply voltage detecting device in the semiconductor device of the second aspect, the comparing potential generated by the comparing potential generating means is inputted as the detecting means, and changes according to the comparing potential and the power supply voltage. Since a logic circuit that outputs different logic values according to the magnitude relationship with the logic threshold value is used, in addition to the above effects, there is an effect that the power supply voltage detection device can be configured with a simple logic circuit.

According to the semiconductor device of any one of claims 3 to 7, the comparison potential generating means generates a substantially constant comparison potential within the predetermined power supply voltage range regardless of the power supply voltage. The detection means compares the potential that changes according to the power supply voltage with the comparison potential generated by the comparison potential generation means to detect whether the power supply voltage exceeds a predetermined voltage. Based on the above, since the circuit or operation to be used is selected by the selecting means, there is an effect that an appropriate circuit or operation can be selected according to the power supply voltage.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor device including a power supply voltage detection device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a voltage detection circuit in FIG.

FIG. 3 is a characteristic diagram for explaining the operation of the voltage detection unit in FIG.

FIG. 4 is a waveform diagram for explaining the operation of the voltage detection circuit shown in FIG.

5 is a circuit diagram showing a configuration of a word line driver and a word line boosting circuit in FIG.

FIG. 6 is an explanatory diagram for explaining the operation of the word line driver and the word line booster circuit shown in FIG.

FIG. 7 is a circuit diagram showing configurations of a dummy cell driver and a dummy cell in FIG.

FIG. 8 is an explanatory diagram for explaining operations of the dummy cell driver and the dummy cell shown in FIG. 7.

FIG. 9 is a circuit diagram showing a configuration of a conventional booster circuit for comparison with the second embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a booster circuit according to a second embodiment of the present invention.

11 is a characteristic diagram for explaining the operation of the booster circuit shown in FIG. 9 and the booster circuit shown in FIG.

FIG. 12 is a circuit diagram showing a configuration of a conventional output circuit for comparison with a third embodiment of the present invention.

FIG. 13 is a circuit diagram showing a configuration of an output circuit according to a third embodiment of the present invention.

14 is a characteristic diagram for explaining the operation of the output circuit shown in FIG. 12 and the output circuit shown in FIG.

FIG. 15 is a circuit diagram showing a configuration of a conventional logic circuit for comparison with the fourth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a configuration of a logic circuit according to a fourth exemplary embodiment of the present invention.

17 is a characteristic diagram for explaining the operation of the logic circuit shown in FIG.

FIG. 18 is a characteristic diagram for explaining the operation of the logic circuit shown in FIG.

[Explanation of symbols]

 13 word line driver 14 word line booster circuit 15 dummy cell driver 20 voltage detection circuit 21 voltage detection unit 22 output holding unit 23 buffer 24 inverter 25 MOS transistor

Claims (7)

[Claims] 1. A comparison potential generation means for generating a substantially constant comparison potential within a predetermined power supply voltage range regardless of the power supply voltage, and a potential changing according to the power supply voltage by the comparison potential generation means. A power supply voltage detection device in a semiconductor device, comprising: a detection unit that detects whether or not the power supply voltage exceeds a predetermined voltage by comparing with the generated comparison potential. 2. The detection means receives the comparison potential generated by the comparison potential generation means and receives the comparison potential and a logic threshold value that changes according to the power supply voltage in accordance with the magnitude relationship. The power supply voltage detection device in a semiconductor device according to claim 1, further comprising a logic circuit that outputs different logic values. 3. A comparison potential generation means for generating a substantially constant comparison potential within a predetermined power supply voltage range without depending on the power supply voltage, and a potential changing according to the power supply voltage by the comparison potential generation means. Detection means for detecting whether or not the power supply voltage exceeds a predetermined voltage by comparing with the generated comparison potential, and selection for selecting a circuit or operation to be used based on the detection result of the detection means. And a semiconductor device. 4. The dynamic random access memory, wherein the selecting means operates a dummy cell driver for driving a dummy cell when the power supply voltage exceeds a predetermined voltage, and the power supply voltage exceeds the predetermined voltage. 4. The semiconductor device according to claim 3, wherein a word line boosting circuit for boosting the potential of the word line is operated when not operating. 5. The boosting circuit for boosting a power supply voltage, the selecting means, based on a detection result of the detecting means,
4. The semiconductor device according to claim 3, wherein the magnitude of the boosted voltage is selected. 6. The selection means, in an output circuit for outputting a digital signal, selects the number of transistors for selectively passing a current according to the value of the digital signal based on the detection result of the detection means. The semiconductor device according to claim 3, wherein 7. The semiconductor device according to claim 3, wherein the selection means selects the number of transistors through which a current for supplying to the logic circuit passes, based on the detection result of the detection means.