JPH08329692A - Batch chip erasing type eeprom, its design method and using method - Google Patents

Abstract

PURPOSE: To electrically separate a used region and an unused region by fixing an assigned terminal for inputting an address to a level 0 or a level 1 at the time of using a part of whole memory capacity up to 1/2N. CONSTITUTION: This ROM is constituted of four bit lines 11 and Y (Y=2<y> , y=0, 1,...) pieces of word lines 13. At the time, a bit line system selecting address is made 2 bits, the number of a word line system address becomes log2 Y, and the number of terminals for address input becomes (2+log2 Y). This is included in a system using a half of a whole memory capacity, and I pieces of terminals counted from the terminal of the most significant bit or counted from the terminal of the least significant bit out of the (2+log2 Y) terminals are assigned to terminals for selecting bit line system address. The assigned terminals for address input are fixed to a level of 0 or a level of 1. At this time, as transistors 19c, 19d or transistors 19a, 19b are not selected, bit lines relating to these transistors are separated from a sense amplifier, a selection memory region can be separated from a non-selection memory region, and an adverse effect of a memory cell in a over erasing state can be eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip erasing type E
EPROM (Electrically Erasable Programmable Rea
d Only Memory) and its designing and using method, and particularly suitable for preventing the occurrence of data rewrite failure when using only half or less of the memory capacity of the EEPROM. The present invention relates to a batch erasable EEPROM, its design method and its use method.

[0002]

2. Description of the Related Art In a semiconductor memory device, an address viewed from outside the device, that is, an address designated by an address designation terminal (hereinafter referred to as "logical address"),
Correspondence with addresses within the device (hereinafter referred to as "physical addresses") (hereinafter referred to as "address scramble")
Say. ) Is generally made at the system design stage of the semiconductor memory device. When determining the address scramble, it is common not to intentionally match the logical address and the physical address, and it is common to make the determination in the direction of minimizing the propagation delay of the output signal of each address buffer. Is.

[0003]

However, in the case of the chip batch erase type EEPROM, when the address scrambling is determined only from the viewpoint of minimizing the propagation delay of the output signal of each address buffer as described above,
The following problems may occur. For the user, for example, in order to reduce the cost, one type of chip batch erase type EEPR
OM is often purchased in large quantities and used in various systems. Therefore, the EEPROM may be used in a system that needs to use only half or less of the total memory capacity of the EEPROM. In such a case, in particular, when the number of times of data rewriting increases, each memory cell in the unused area may be in an over-erased state, resulting in a rewrite failure resulting in a problem. This will be described in detail below.

In the chip batch erasing type EEPROM, when writing data to this, each memory cell is individually accessed and executed, while when erasing data, the data of all memory cells are erased collectively. However, in the chip batch erasing type EEPROM, in order to store predetermined information, there are mixed memory cells in which a fixed charge is stored in the floating gate and memory cells in which the stored charge is zero. . If the chip batch erase type EEPROM in such a state is collectively erased, that is, the charges are extracted from all the memory cells, the floating gate is likely to be in the over-erased state in the memory cells in which the accumulated charges are zero. Since the floating gate is positively charged, the threshold value of the transistor provided in this memory cell shifts in the negative direction, and as a result, this memory cell itself becomes a depletion state. If many such memory cells exist on the same bit line, even if an attempt is made to apply a high voltage to this bit line for the purpose of writing data to the memory cell belonging to this bit line, the leakage current in the memory cell in the depletion state Due to this, the voltage cannot be increased and data cannot be rewritten.
In order to avoid this, a chip batch erase type EEPROM
In this case, data writing (hereinafter referred to as “all address data writing before erasing”) is performed on all memory cells before collectively erasing all memory cells (for example, Document I: Intel Databook (1992). Annual version,
Pp. 3-92, Fig. 6)). However, when only half or less of the total memory capacity of the chip batch erasing type EEPROM is used (generally speaking, only 1/2 ^N (N is a positive integer excluding 0) is used), the address data Is (MN) for the number of address data bits (total number of logical address input lines) M that can access all memory cells.
Since only bits are originally used, all the address data before erasure cannot be written to the memory cells belonging to the unused area. Therefore, the memory cell belonging to the unused area has a problem due to the above-mentioned overerasure. In order to avoid this, it is conceivable that the system side is provided with an addressing function for an unused area to write all address data before erasing, but this is not preferable because it is an extra function and trouble in the first place.

Even if the chip batch erase type EEPROM is used only for a part up to 1/2 ^N (N is a positive integer other than 0) of the total memory capacity, rewriting due to the overerasure is performed. A technique that can easily prevent the occurrence of defects is desired.

[0006]

Therefore, according to the first invention of this application, in a chip batch erasing type EEPROM, up to 1/2 ^N (N is a positive integer except 0) of the total memory capacity of the EEPROM. Considering some use, the EEPR
One of the address input terminals provided in the OM is characterized in that N terminals counted from the most significant bit or N terminals counted from the least significant bit are allocated for bit line system address selection.

Further, according to the second invention of this application, in designing the chip batch erase type EEPROM, the address scrambling is determined by 1/2 ^N of the total memory capacity of the EEPROM (N is a positive integer except 0). ) In consideration of the partial use up to the above), for N input lines or the least significant bit counting from the most significant bit among all M logical address input lines (M is M> N and an integer) of the EEPROM. N counting from
This is performed by a process including a process of assigning a book input line for bit line system address selection.

Further, according to the third invention of this application, in consideration of partial use up to 1/2 ^N (N is a positive integer except 0) of the total memory capacity, among the address input terminals, A chip batch erasing type EEPROM, in which N for the most significant bit or N for the least significant bit is assigned for bit line system address selection,
When only the area up to / 2 ^N is used, the assigned N address input terminals are fixed to 0 level or 1 level and used.

[0009]

The chip batch erase type EEP of the first invention of this application
In a ROM, when it is used by incorporating it into a system that uses only 1/2 ^N of its total memory capacity, ^{N number} of address input terminals provided in the EEPROM are assigned for bit line system address selection. _Is connected to 0 level (eg ground potential V _SS ) or 1 level (eg power supply potential V _CC ). By doing so, only the bit line group corresponding to 1/2 ^N of the total memory capacity is selected according to the connected level. Then, the memory area of the non-selected portion and the selected memory area are electrically separated. These will be described more specifically with reference to a schematic circuit diagram of a small-capacity chip batch erasing type EEPROM. FIG. 4 shows four bit lines 11 and one word line 1.
3 is a schematic diagram of a circuit configuration of a portion necessary for explaining the present invention of a chip batch erase type EEPROM in which 3 is Y (Y = 2 ^y , y is 0, 1, ...). In FIG. 4, 15 is a memory cell, 17 is a sense amplifier, 19 is a multiplexer, 19a to 19d are bit line selection transistors provided in the multiplexer 19, and 21 is a common node used for reading / writing / erasing data of each memory cell. , B
D indicates an output signal from the bit line decoder, and WD indicates an output signal from the word line decoder. Note that each of the bit line selection transistors 19a to 19d is MO
It is assumed that the SFET is used and each memory cell 15 is formed of a MOSFET having a floating gate. Since there are four bit lines 11, the bit line system selection address is composed of 2 bits, and the word line 13 is Y.
Since it is a book, the word line system address is composed of log ₂ Y lines, so the number of address input terminals of this chip batch erase type EEPROM is (2 + log ₂ Y). Here, consider an example in which this chip batch erasing type EEPROM is incorporated and used in a system that uses only 1/2 of the total memory capacity. Then, in the first and second inventions, (2
Among the + log ₂ Y) address input terminals, one terminal counting from the most significant bit (or one terminal counting from the least significant bit) is assigned for bit line system address selection. Then, when this EEPROM is used, the assigned address input terminal is fixed to 0 level or 1 level. If the assigned address input terminal is fixed to 0 level (1 level), the transistors 19c and 19d (19a and 19b) in FIG. 4 are not selected, so that these transistors 19c and 19d are not selected. The bit line associated with (19a, 19b) is electrically disconnected from the sense amplifier.
As a result, the selected memory area and the non-selected memory area can be electrically separated.

Chip erasure type EEP having such a configuration
In the ROM, as in the ordinary one, (1) a high voltage that may cause a tunnel phenomenon is applied to the memory cell common node 21 when erasing the data of each memory cell, and (2) each memory. When writing data to a cell or reading data from each memory cell, 0 level (ground potential) is applied. Even in this EEPROM, the non-selected memory area is in the over-erased state as the number of data rewrites increases, but when writing data to each memory cell or reading data from each memory cell, the selected memory area is as described above. Since the non-selected memory region and the non-selected memory region are electrically separated, the adverse effect of the over-erased memory cell can be excluded.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the first to third inventions of this application will be described below with reference to the drawings. However, the drawings used for the explanation are shown schematically so that the present invention can be understood. Further, in each of the drawings used for the description, the same components are denoted by the same reference numerals, and the duplicate description may be omitted.

FIG. 1 is a diagram for explaining the chip collective erase type EEPROM of the first and second embodiments.
It is an external view at the time of making a PROM into a typical DIP type product. Further, FIG. 2 illustrates logical addresses (sometimes referred to as address input terminals in consideration of products) A0 to A1 in order to explain the concept of address scrambling in the first embodiment.
7 is a diagram for explaining the correspondence between No. 7 and physical addresses B0 to B17. However, in all figures, the chip batch erase type EEPROM with a memory capacity of 2M (mega)
An example is shown in consideration of the case where only capacity (that is, 512 Kb (kilobit)) up to 4 (that is, N = 2 at 1/2 ^N ) is used. Further, an example is shown in which among the physical addresses B0 to B17 composed of 18 bits, 7 bits are set as the bit line system address I (see FIG. 2) and 11 bits are set as the word line system address II. Therefore, the number of bit lines is 2 ⁷ = 128.

In the chip batch erase type EEPROM of the first embodiment, of the address input terminals A0 to A17 provided in the EEPROM, two terminals are counted from the terminal A17 for the most significant bit, that is, A17 and A1.
Address input terminals designated by 6 are assigned to, for example, B6 and B7 of the bit line system selection addresses B0 to B6 (see FIG. 2). Of course, A17 and A16
Can be assigned to any two of B0 to B6,
The allocation destinations are not limited to B6 and B7. Also, A17
And remaining address input terminals A0 to A other than A16
The method of assigning 15 to physical addresses B0 to B17 (excluding those assigned above) is arbitrary (see FIG. 2).

When the chip collective erase type EEPROM of the first embodiment is used only in a region of 1/4 of the total memory capacity, the A16 terminal is set to 0 level (eg ground potential V _SS ) or in the present invention. It is fixed at 1 level (power supply potential V _CC ), and the terminal of A17 is fixed at 0 level or 1 level. By doing so, similar to the principle already described with reference to FIG. 4, a bit line group (1 in this example, which corresponds to 1/4 of the entire memory area of this EEPROM by the fixed level).
Only 28/4 = 32 bit line groups) are selected. Then, the 1/4 bit line group and the unused bit line group not selected this time are electrically separated. Therefore, since the memory cells in the unused area can be separated from the sense amplifier, the memory cells in the unused area cannot be written to all the address data before erasing, resulting in an over-erased state and becoming a depletion type transistor, causing a leak current. However, this does not affect the memory cell group in the used area. Of course, it goes without saying that desired address data is input to the address input terminals A0 to A15 excluding A16 and A17 according to the clock. In addition, the chip collective erase type EE of the first embodiment
When the PROM is incorporated into a system that uses only 1/2 of the total memory capacity, if the memory capacity of 1/2 is used, the terminal of A17 may be fixed to 0 level or 1 level.

On the other hand, when the chip batch erase type EEPROM of the first embodiment is used in a system which uses the entire memory capacity thereof, all address inputs including A16 and A17 are input as usual. Terminals A0-A1
Data may be input / output by inputting desired address data to 7 according to a clock.

From the above, the chip batch erase type EEPROM of the present invention has a total memory capacity of 1/2 ^N
It is understood that it is not necessary to add a circuit having a special function or change the pattern layout when using up to (N is a positive integer except 0) or when using the entire memory capacity. it can.

FIG. 3 is an explanatory diagram of the chip batch erase type EEPROM of the second embodiment. In particular, in order to explain the concept of the address scramble of the second embodiment, a logical address (address input considering the product is input. It is also called a terminal.) A diagram illustrating the correspondence between A0 to A17 and physical addresses B0 to B17. However, in this case as well, the chip batch erase type EEPROM having a memory capacity of 2M is
Up to the capacity (that is, 512 Kb) is used in the example considered.

Chip erasure type EE of the second embodiment
In the PROM, of the address input terminals A0 to A17 provided in the EEPROM, the terminal A for the least significant bit is used.
Two address input terminals counted from 0, that is, address input terminals with A0 and A1 are assigned to, for example, B2 and B1 of the bit line system selection address input terminals B0 to B6 (see FIG. 3). Of course, A0 and A1 are B0
It is sufficient to allocate to any two of B6 to B6 and is not limited to B2 and B1. Other address input terminals A2
.. to A17 are assigned to physical addresses B0 to B17 (excluding those assigned above) arbitrarily.

Chip collective erasing type EE of the second embodiment
When the PROM is used for a partial area up to ¼ of its total memory capacity (including usage of ½), the terminals of A0 and / or A1 are fixed to 0 level or 1 level, and A2 and A17 Other than inputting the address data to the terminal, it can be performed in the same manner as in the first embodiment, and therefore its explanation is omitted.

In the above description, an example in which a partial use up to 1/4 of a chip batch erase type EEPROM having a memory capacity of 2M is considered, but of course a partial use up to 1/2 is considered. , Or when considering partial use up to 1/2 ^N where ^N is an integer of 3 or more, these inventions can of course be applied.

[0021]

As is apparent from the above description, according to the first invention of this application, the chip batch erasing type EEPROM
1/2 ^N of the total memory capacity of M (N is a positive integer excluding 0)
In consideration of the partial use up to N, N is counted from the most significant bit of the address input terminals provided in the EEPROM.
, Or N for the least significant bit are assigned for bit line system address selection. For this reason, when partly using up to 1/2 ^{N of the} total memory capacity, the allocated address input terminal is fixed to 0 level or 1 level, and the used area and the unused area are electrically separated. it can. As a result, even if the memory cell in the unused area is in the over-erased state, it can be prevented from affecting the used area, so that it is possible to prevent the occurrence of the data write failure in the used area due to the over-erasure of the unused area.

Further, according to the designing method of the second invention, it is possible to obtain the chip collective erasing type EEPROM in which the data rewriting failure does not occur even when the partial memory area of the chip collective erasing type EEPROM is used.

According to the method of use of the third invention, the chip batch erase type EEPROM of the first invention can be effectively used.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of first and second embodiments, showing an example in which the present invention is applied to a typical DIP type EEPROM.

FIG. 2 is an explanatory diagram of the first embodiment and is a diagram showing a correspondence relationship between a logical address and a physical address.

FIG. 3 is an explanatory diagram of the second embodiment and is a diagram showing a correspondence relationship between a logical address and a physical address.

FIG. 4 is a diagram for explaining the operation of each invention of this application.

[Explanation of symbols]

11: Bit line 13: Word line 15: Memory cell 17: Sense amplifier 19: Multiplexer 19a to 19d: Bit line selection transistor 21: Memory cell common node A: Logical address B0 to B17: Physical address A16, A17: Bit line Address input terminals assigned for system address selection (in the case of the first embodiment) A0, A1: Bit lines Address input terminals assigned for system address selection (in the case of the second embodiment) I: Bit lines System address II: Word line system address

Claims (3)

[Claims] 1. A chip batch erasing type EEPROM, considering the partial use up to 1/2 ^N (N is a positive integer except 0) of the total memory capacity of the EEPROM,
Of the address input terminals provided in the above, N number counted from the most significant bit or N number counted from the least significant bit are assigned for bit line system address selection . 2. When designing a chip batch erasing type EEPROM, address scrambling is determined in consideration of partial use up to 1/2 ^N (N is a positive integer except 0) of the total memory capacity of the EEPROM. The EEPROM
Of all the logical address input lines (M is M> N and an integer), N input lines counting from the most significant bit or N input lines counting from the least significant bit A method of designing a chip batch erasing type EEPROM, which is characterized in that it is performed by a process including a process of assigning for address selection. 3. Considering a partial use up to 1/2 ^N (N is a positive integer except 0) of the total memory capacity, N pieces are counted from the most significant bit of the address input terminals. Or, a chip batch erasing type EEPROM in which N pieces are counted for bit line system address selection from the least significant bit
When only the area up to 1/2 ^N of the total memory capacity is used, the assigned N address input terminals are fixed to 0 level or 1 level and used. How to use.