JPH08330860A - Scaler circuit - Google Patents

Abstract

(57) [Summary] [Purpose] It is an object to provide a scaler circuit capable of reducing the number of unit capacitances. [Configuration] An odd number of MOS inverters are connected in series,
A ground capacitance is connected between the output of the final stage MOS inverter and the ground, and the output of the MOS inverter is connected to the power supply and the ground by a pair of balanced resistances before the final stage MOS inverter.
The output of the MOS inverter at the final stage is fed back to the input of the first stage inverter, and a reference voltage is generated as the output of the reference voltage generation circuit.
The S inverter and the MOS inverters of the first and second inverting amplification sections are set to have the same circuit characteristics and are arranged close to each other on the LSI.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scaler circuit, and more particularly to a scaler circuit for adjusting the output level of analog voltage.

[0002]

2. Description of the Related Art The applicant of the present application has implemented a weighted addition in which a plurality of capacitances are connected in parallel in an analog computer, and has realized a multiplication circuit for ensuring linearity and drive capability by a MOS inverter including its output feedback capacitance. (Japanese Patent Laid-Open No. 06-162
230, etc.). In such a computer, if the calculation path becomes complicated, the input range and the output range may become inconsistent, and it is necessary to actively perform range adjustment. Therefore, the applicant of the present application has proposed a scaler circuit for matching the input and output ranges in Japanese Patent Application No. 05-042048.

In this proposed circuit, as shown in FIG. 4, an input voltage Vin is capacitively coupled C via a switch circuit SWC1.
It is connected to P1 and the output of this capacitive coupling CP1 is input to the inverting amplifier INV1. The output of INV1 is input to the parallel feedback capacitance group CF1 and the output of CF1 is connected to the input side of INV1 by the switch circuit SWC2. The switch circuit SWC1 connects the capacitors C12 to C14 of CP1 to Vin or the ground, and the switch circuit SWC2 inputs the input of INV1 to CF1.
Connected to the capacitances C22 to C24 or ground. In such a configuration, if the sum of the capacitances of the capacitors C11 and CP1 connected to Vin by SWC1 (referred to as “effective combined capacitance”) is (C11 + ΣC1i) and the effective combined capacitance of CP2 is (C21 + ΣC2i), INV1 Output V '
V ′ = − Vin (C11 + ΣC1i) / (C21 + ΣC2i) (1)

The output of INV1 is supplied to the inverting amplifier INV via the switch circuit SW3 and the capacitive coupling CP2 having the same structure.
The output of INV2 is fed back to its input via the feedback capacitance group CF2 and the switch circuit SWC4. Assuming that the output of INV1 is V ′, the output Vout of INV2 is Vout = −V ′ (C31 + ΣC3i) / (C41 + C4i) (2), and the output level is adjusted by weighting these.

Then, SWC2 to SWC4 are set so that the effective combined capacities of CP2, CP3, and CP4 are equal,
And (C11 + C12 + C13 + C14) = (C31 +
By setting C32 + C33 + C34), I
The offset voltages of NV1 and INV2 are canceled.

The multiplier of such a scaler circuit is determined by the capacitance value of the capacitance. On an LSI (Large Scale Integrated Circuit), the capacitance is configured by connecting a plurality of unit capacitances, so that a large multiplier is realized. In order to do so, an extremely large number of unit capacitances are required, and there is a problem that the circuit area becomes large. Further, when there is an error between the input offset voltage and the reference voltage, a large offset component is generated in the output signal, which adversely affects the circuit operation. Therefore, it is necessary to delicately adjust the capacitance value of the capacitance to suppress the offset component of the output.

[0007]

SUMMARY OF THE INVENTION The present invention was devised to solve the above-mentioned conventional problems, and an object thereof is to provide a scaler circuit capable of reducing the number of unit capacitances.

[0008]

A scaler circuit according to the present invention has an odd number of MOS inverters connected in series,
A ground capacitance is connected between the output of the MOS inverter of the final stage and the ground, and the output of the MOS inverter is connected to the power supply and the ground by a pair of balanced resistances before the MOS inverter of the final stage. The reference voltage is generated as the output of the reference voltage generation circuit that is fed back to the input of the first stage inverter, and the output of the
The inverter and the MOS inverters of the first and second inverting amplification units are set to have the same circuit characteristics and are arranged close to each other on the LSI. Further, regarding the offset component of the output, in order to have the degree of freedom of capacitance, the circuit configurations of the reference voltage generation circuit and the inverter circuit are made as close as possible to each other, and the difference between the input offset voltage, the reference voltage and the reference voltage is reduced. .

[0009]

According to the scaler circuit of the present invention, since the capacitance value of each stage is suppressed by weighting the first inverting amplifier unit and the second inverting amplifier unit in two stages, the number of unit capacitances is suppressed, and The offset voltage of the MOS inverter of the reference voltage generation circuit and the offset voltage of the MOS inverter of the inverting amplification unit cancel each other out, and the output accuracy becomes good. Furthermore, the degree of freedom in selecting the capacitance value of the capacitance can be secured.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, one embodiment of a scaler circuit according to the present invention will be described with reference to the drawings.

In FIG. 1, the scaler circuit comprises a switch circuit SWC1, a capacitive coupling CP1, an inverting amplifier INV1, a switch circuit SWC3, a capacitive coupling CP2 and an inverting amplifier INV2 connected in series, and an input voltage Vin is a switch circuit SWC1. It is connected to the.

The switch circuit SWC1 includes a plurality of switches SW which selectively connect Vin or a reference voltage to an output.
1, SW2, SW3, and SW4 are connected in parallel. The reference voltage is generated by the reference voltage generation circuit Vref, and a voltage that is ½ of the power supply voltage Vdd common to the entire circuit, that is, (Vdd / 2) is generated. The capacitive coupling CP1 integrates the outputs of the capacitances C1, C2, C3 and C4 respectively connected to the switches SW1 to SW4,
The output is input to INV1. Switch circuit S
WC1 selectively applies Vin or a reference voltage to each capacitance of the capacitive coupling CP1, and the integrated output thereof is input to INV1.

A switch circuit SWC2 formed by connecting a plurality of switches SW5, SW6, SW7 and SW8 in parallel is connected to the output of the inverting amplifier INV1, and a plurality of capacitors C5, C6, C7 and C8 are connected in parallel to the SWC2. The feedback capacitance group CF1 formed by is connected.
The outputs of C5 to C8 are integrated and connected to the input of INV1, and each switch SW5 to SW8 connects the INV1 output or ground to the corresponding capacitance C5 to C8.

Further, a reference voltage capacitance Cr1 in parallel with the capacitances C1 to C4 is connected to the capacitive coupling CP1, and the reference voltage generating circuit Vref is constantly connected to Cr1.
Is connected. This reference voltage capacitance is used in a multiplication circuit with similar capacitive coupling,
This is effective in achieving consistency with the multiplication circuit and sharing of the circuit pattern.

Although details of the reference voltage generation circuit Vref and the inverting amplifier INV1 will be described later, these circuits mainly include a three-stage serial MOS inverter, but the reference voltage and the INV1 input are offset. The voltage Voff may be included. Therefore, the reference voltage generating circuit and the MOS inverter of the inverting amplifier are set to have the same characteristics and are arranged close to each other on the LSI. As a result, the offset voltage of each MOS inverter becomes equal, and as will be described later, capacitive coupling CP1, CP
2 and the feedback capacitance group will offset each other.

A switch circuit SWC2 formed by connecting a plurality of switches SW5, SW6, SW7, SW8 in parallel is connected to the output of the inverting amplifier INV1, and a plurality of capacitors C5, C6, C7, C8 are connected in parallel to the SWC2. The feedback capacitance group CF1 formed by is connected.
The outputs of C5 to C8 are integrated and connected to the input of INV1, and each switch SW5 to SW8 connects the INV1 output or reference voltage to the corresponding capacitance C5 to C8.

Here, the sum of the capacitances of the capacitances connected to Vin of C1 to C4 is called the effective combined capacitance of CP1, expressed as Σ (CP1), and connected to the INV1 output in the feedback capacitance group CF1. The sum of the capacitances of the existing capacitances is called the effective combined capacitance, and Σ (CF
Express in 1). The sum of the capacitances of C1 to C4 is T (CP
1), the sum of the capacities of C5 to C8 is expressed as T (CF1),
Further, T (CP1) −Σ (CP1) = S (CP1) (3) T (CF1) −Σ (CF1) = S (CF1) (4)

In the above configuration, the output of INV1 is V
1. If the input-side offset voltage of INV1 is Voff and the reference voltage is Vref, Σ (CP1) (Vin-Voff) + Σ (CF1) (V1-Voff) + S (CP1) (Vref- Voff) + S (CF1) (Vref−Voff) = 0 (5).

From the equation (5), V1-Voff =-{Σ (CP1) / Σ (CF1)} (Vin-Voff)-[{S (CP1) + S (CF1)} / Σ (CF1)] × ( Vref-Voff) (6) is obtained. Then, (Vref-Voff) is extremely small (on the order of 0.1 mV), and the equation (6) is substantially approximated to the following equation (7). V1-Voff =-{Σ (CP1) / Σ (CF1)} (Vin-Voff) (7)

The switch circuit SWC3 includes a plurality of switches S
W9, SW10, SW11, and SW12 are connected in parallel, and the capacitive coupling CP2 has capacitances C9, C10, and C.
11, C12 and Cr2 are connected in parallel. Each switch SW9-SW12 has a corresponding capacitance C9-C.
12 respectively to connect the INV1 output or ground to the corresponding capacitance. Cr2 is a reference voltage capacitance similar to Cr1 and is connected to the reference voltage generation circuit Vref.

The switch circuit SWC3 has a capacitive coupling CP2.
Vin or ground is selectively applied to the individual capacitances of the above, and the integrated output is input to INV2.

A switch circuit SWC4 formed by connecting a plurality of switches SW13, SW14, SW15 and SW16 in parallel is connected to the output of the inverting amplifier INV2, and SWC4.
Has a plurality of capacitances C13, C14, C15, C
A feedback capacitance group CF2 formed by connecting 16 in parallel is connected. The outputs of C13 to C16 are integrated and I
Each switch SW13 to SW1 is connected to the input of NV1.
6 connects the INV2 output or ground to the corresponding capacitances C13-C16.

Here, the sum of the capacitances of the capacitances connected to V1 among C9 to C12 is called the effective combined capacitance of CP2 and is expressed by Σ (CP2), and is connected to the INV2 output in the feedback capacitance group CF2. The sum of the capacitances of the existing capacitances is called the effective combined capacitance, and Σ (CF
Express in 2). Further, the sum of the capacities of C9 to C12 is T (C
The sum of the capacities of P2) and C13 to C16 is expressed as T (CF2), and T (CP2) -Σ (CP2) = S (CP2) (8) T (CF2) -Σ (CF2) = S (CF2) ) (9) is expressed.

In the above configuration, the output of INV2 is V
The offset voltage on the input side of out and INV2 is
When Voff is made equal to the input side offset voltage of 1, and the reference voltage is Vref, Σ (CP2) (V1-Voff) + Σ (CF2) (Vout-Voff) + S (CP2) (Vref-Voff) + S (CF2) ( Vref-Voff) = 0 (10). This formula (10) is similar to the formula (7), and
f-Voff) is disregarded and it rearranges like Formula (11). Vout-Voff =-{Σ (CP2) / Σ (CF2)} (V1-Voff) (11)

From equations (7) and (11), Vout-Voff = {Σ (CP1) / Σ (CF1)} × {Σ (CP2) / Σ (CF2)} × (Vin-Voff) (12) Relationship is obtained. This is obtained by multiplying (Vin-Voff) by two multipliers {Σ (CP1) / Σ (CF1)} and {Σ (CP2) / Σ (CF2)},
It can be seen that it is possible to obtain the result of multiplying (Vin-Voff) by a sufficiently large multiplier while suppressing the individual multipliers to be relatively small.

Further, the offset voltage Voff can be predicted in advance, and the output level can be adjusted with sufficiently high accuracy by using the scaler circuit in consideration of this Voff.

In FIG. 2, the inverting amplifier INV1 has three stages of serial MOS inverters I1, I2, I3, and constitutes an inverting amplifier having a high gain given by the product of the gains of these inverters. The output of INV1 is fed back to its input by the feedback capacitance group CF1, and good linear characteristics of input and output are guaranteed. The output of the final-stage MOS inverter I3 has a capacitance CG connected to the reference voltage generation circuit Vref.
And the balanced resistances RE1 and RE2 connected to the power supply voltages Vdd and Vref, respectively, are connected to the output of the second-stage MOS inverter I2, which is generated by feeding back an inverted amplified signal of high gain. Occasional oscillation can be prevented. Further, a refresh switch SW21 capable of short-circuiting its input and output is connected to the inverting amplifier INV1, and this refresh switch is closed at a proper time, and at the same time, the switches SW1 to SW4.
By connecting SW9 to SW12 to the Vref side, the offset voltage on the input side of the inverting amplifier is eliminated. The inverting amplifier INV2 has the same structure as the INV1 and thus will not be described.

In FIG. 3, the reference voltage generating circuit Vref
Is a three-stage serial MOS inverter I1, I'2, I'3
The output of is returned to the input, and the return path is always closed (not opened) dummy switch SW31.
Is provided. As a result, the circuit pattern of the reference voltage generating circuit can be configured in the same manner as the inverting amplifier INV1 (including the switch), and its electrical characteristics, particularly the offset voltage can be set to be substantially the same. Further, the reference voltage generating circuit has the same capacitance CG ′ as the inverting amplifier INV1.
Further, processing for preventing oscillation by the balance resistances RE1 ′ and RE2 ′ is performed. When the input / output characteristics of the entire three-stage inverter are expressed as y = f (x) with input x and output y, x = f (x) due to the relationship of x = y due to the connection of the output to the input, As this solution, x = Vdd
The characteristics of each MOS inverter, particularly the threshold value, are set so that / 2 is obtained.

The reference voltage thus determined is theoretically equal to the offset voltage Voff, and the difference can be treated as a minute error as described above.

FIG. 4 shows a modification of the above embodiment, in which the reference voltage generating circuit Vref connected to the capacitive couplings CP1 and CP2 and the capacitances Cr1 and Cr2 for connecting them are omitted. There is. As a result, the features of consistency with the multiplication circuit and common pattern are lost, but the circuit is simplified, and Cr1, Cr2
It is possible to avoid an adverse effect on calculation accuracy due to.

As described above, in the scaler circuit according to the present invention, odd-numbered MOS inverters are connected in series,
A ground capacitance is connected between the output of the MOS inverter of the final stage and the ground, and the output of the MOS inverter is connected to the power supply and the ground by a pair of balanced resistances before the MOS inverter of the final stage. The reference voltage is generated as the output of the reference voltage generation circuit that is fed back to the input of the first stage inverter, and the output of the
The inverter and the MOS inverters of the first and second inverting amplification sections are set to have the same circuit characteristics and are arranged close to each other on the LSI, and there are two stages of the first inverting amplification section and the second inverting amplification section. Since the capacitance value of each stage is suppressed by weighting, the number of unit capacitances is suppressed, and the offset voltage of the MOS inverter of the reference voltage generation circuit and the offset voltage of the MOS inverter of the inverting amplification unit are substantially canceled out, and the output accuracy is improved. It has an excellent effect that Furthermore, since the reference voltage generating circuit is configured to approximate an inverting amplifier circuit, the difference in offset voltage can be minimized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a scaler circuit according to the present invention.

FIG. 2 is a circuit diagram showing an inverting amplification unit in the embodiment.

FIG. 3 is a circuit diagram showing a reference voltage generating circuit in the embodiment.

FIG. 4 is a circuit diagram showing a modification of the first embodiment.

FIG. 5 is a circuit diagram showing a conventional scaler circuit.

[Explanation of symbols]

INV1, INV2. ． ． Inverting amplifiers SWC1, SWC2, SWC3, SWC4. ． ． Switch circuits CP1, CP2. ． ． Capacitive coupling CF1, CF2. ． ． Feedback capacitance group Vref. ． ． Reference voltage generation circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Yamamoto 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Co., Ltd. (72) Inventor Nao Takatori 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Shares Company Takayamauchi

Claims (4)

[Claims] 1. A first switch circuit comprising a plurality of switches which are alternatively connected to an input voltage or a reference voltage, and an output side of each switch of the first switch circuit which is respectively connected and outputs are integrated. And a first inverting amplification section comprising an odd-numbered series MOS inverter connected in series to the output of the first capacitance coupling, the first inverting amplification section being connected in parallel with the first inverting amplification section. First
A plurality of first feedback capacitance groups each including a plurality of capacitances connected by capacitive coupling and a plurality of capacitances of the first feedback capacitance group that are alternatively connected to the output of the first inverting amplification unit or the reference voltage. A second switch circuit composed of a switch, a third switch circuit composed of a plurality of switches connected in parallel to the output of the first inverting amplifier section or a reference voltage, and connected to the output side of each switch of the third switch circuit. And a second capacitive coupling having integrated outputs, a second inverting amplifying section comprising an odd number of series MOS inverters connected to the output of the second capacitive coupling, and the second inverting amplifying section in parallel with the second inverting amplifying section. The second feedback capacitance group composed of a plurality of capacitances connected to the second capacitive coupling and the output of the second inverting amplification unit or the reference voltage are set to 2
A scaler circuit including a fourth switch circuit including a plurality of switches for selectively connecting the respective capacitances of the second feedback capacitance group, wherein an odd number of MOS stages
Connect the inverter in series, connect the ground capacitance between the output of the final stage MOS inverter and the ground, and connect the output of the MOS inverter in the stage before the final stage MOS inverter to the power supply and the ground by a pair of balanced resistances. Then, the output of the final-stage MOS inverter is fed back to the input of the first-stage inverter, and the reference voltage is generated as the output of the reference voltage generation circuit.
A scaler circuit characterized in that the MOS inverter of the reference voltage generation circuit and the MOS inverters of the first and second inverting amplification sections are set to have the same circuit characteristics and are arranged close to each other on the LSI. 2. A grounding capacitance is connected between the respective outputs of the first and second inverting amplifiers and the ground, and the grounding capacitance of the MOS inverter is provided in a stage preceding the final stage MOS inverter of the first and second inverting amplifiers. Connect the output to the power supply and ground by a pair of balanced resistances,
The scaler circuit according to claim 1, wherein the outputs of the first and second inverting amplifiers are connected to the respective inputs by a feedback capacitance. 3. The power supply voltage of the MOS inverter is Vdd
The scaler circuit according to claim 1, wherein the reference voltage is generated so that the reference voltage becomes Vdd / 2. 4. The first and second inverting amplifiers are connected to refresh switches for connecting their inputs and outputs as appropriate, and the reference voltage generating circuit has the same configuration as this refresh switch and is not released. The scaler circuit according to claim 1, wherein a dummy switch is connected.