JPH08335687A - Method for manufacturing thin film photoelectric conversion device - Google Patents
Method for manufacturing thin film photoelectric conversion deviceInfo
- Publication number
- JPH08335687A JPH08335687A JP7163098A JP16309895A JPH08335687A JP H08335687 A JPH08335687 A JP H08335687A JP 7163098 A JP7163098 A JP 7163098A JP 16309895 A JP16309895 A JP 16309895A JP H08335687 A JPH08335687 A JP H08335687A
- Authority
- JP
- Japan
- Prior art keywords
- film
- photoelectric conversion
- gate
- forming
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
- H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
(57)【要約】
【目的】光電変換素子と、その画素選択用スイッチとし
て特性の均一なLDD構造薄膜トランジスタを備えた薄
膜光電変換装置を、低コストで作製する製造方法を得
る。
【構成】絶縁性基板1上に多結晶シリコン層2、ゲート
絶縁膜13、ゲート電極膜16を順次積層し、その上部
にフォトリソによりフォトレジストマスク14を形成
し、これを用いてゲ−ト電極膜16を等方的にエッチン
グしてゲ−ト電極6とし、続いてゲート絶縁膜13を異
方的にエッチングしてゲ−ト絶縁層3とし、ゲート電極
6とゲート絶縁層3をマスクとして多結晶シリコン層2
に不純物を導入する。さらに下地電極膜20、半導体膜
21および透明導電膜22を順次積層し、1回のフォト
リソで形成したフォトレジストマスク15を用いて透明
導電膜22、半導体膜21および下地電極膜20をそれ
ぞれエッチングして下地電極10、半導体層11および
透明電極12からなる光電変換素子を形成する。
(57) [Summary] [Object] To obtain a manufacturing method for manufacturing a thin film photoelectric conversion device provided with a photoelectric conversion element and an LDD structure thin film transistor having uniform characteristics as a pixel selection switch at low cost. [Structure] A polycrystalline silicon layer 2, a gate insulating film 13, and a gate electrode film 16 are sequentially laminated on an insulating substrate 1, and a photoresist mask 14 is formed on the upper part thereof by photolithography, and a gate electrode is formed by using this. The film 16 is isotropically etched to form the gate electrode 6, the gate insulating film 13 is anisotropically etched to form the gate insulating layer 3, and the gate electrode 6 and the gate insulating layer 3 are used as masks. Polycrystalline silicon layer 2
Introduce impurities into. Further, the base electrode film 20, the semiconductor film 21, and the transparent conductive film 22 are sequentially stacked, and the transparent conductive film 22, the semiconductor film 21, and the base electrode film 20 are etched using the photoresist mask 15 formed by one-time photolithography. As a result, a photoelectric conversion element including the base electrode 10, the semiconductor layer 11 and the transparent electrode 12 is formed.
Description
【0001】[0001]
【産業上の利用分野】本発明は、ファクシミリ、スキャ
ナー、ディジタル複写機等の読み出し部に用いられる光
電変換装置の製造方法に関し、特に薄膜技術を用いた光
電変換素子と、光電変換素子で発生した電荷を外部に伝
達する選択用スイッチとしての薄膜トランジスタを併有
する薄膜光電変換装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a photoelectric conversion device used in a reading section of a facsimile, a scanner, a digital copying machine, etc., and particularly to a photoelectric conversion element using thin film technology and a photoelectric conversion element generated by the photoelectric conversion element. The present invention relates to a method for manufacturing a thin film photoelectric conversion device having a thin film transistor as a selection switch for transmitting charges to the outside.
【0002】[0002]
【従来の技術】近年の情報処理技術の発展に伴い安価で
高性能のデバイスや機器が求められている。ファクシミ
リにおいては、その主要構成である読み出し部、記録部
および通信部のうち、記録部はサーマルヘッドなどの発
達により、また通信部はLSIの発展により低コストか
つ高性能に作製する技術が開発されているが、一方読み
出し部は、複雑な光学系を有し、また光電変換装置自体
のコストが高いので、全体的な低コスト化を妨げてい
る。このため、読み出し部の低コスト化、高性能化を可
能にする技術が必要である。この読み出し部の低コスト
化、高性能化を可能にする方法として、光学系を簡単に
するため、読み取り対象と光電変換装置を密着させる構
造が提案されている。このような光電変換装置の一つ
に、薄膜技術を用いて、光電変換素子と光電変換素子で
発生した電荷を外部に伝達する選択用スイッチとしての
薄膜トランジスタとを同一基板上に形成した薄膜光電変
換装置が知られている。2. Description of the Related Art With the recent development of information processing technology, inexpensive and high-performance devices and equipment are required. Among facsimiles, which are the main components of a facsimile, a recording part is developed at a low cost and with high performance due to the development of a thermal head or the like in the recording part and the development of an LSI in the communication part. However, on the other hand, the reading section has a complicated optical system, and the cost of the photoelectric conversion device itself is high, which prevents an overall cost reduction. Therefore, there is a need for a technology that enables cost reduction and high performance of the reading unit. As a method for reducing the cost and improving the performance of the reading unit, a structure has been proposed in which the reading target and the photoelectric conversion device are in close contact with each other in order to simplify the optical system. One of such photoelectric conversion devices is a thin film photoelectric conversion in which a thin film technology is used to form a photoelectric conversion element and a thin film transistor as a selection switch for transmitting charges generated in the photoelectric conversion element to the outside on the same substrate. The device is known.
【0003】薄膜光電変換装置において使用される薄膜
トランジスタとしては、アモルファスシリコン、多結晶
シリコン等を使用したものがよく知られている。多結晶
シリコンを用いた薄膜トランジスタは、アモルファスシ
リコンを用いた場合と比較して高い移動度が得られるの
で、光電変換装置の駆動回路まで同一基板上に作製する
ことができるため、小型化、低コスト化に有利である。
また、外部駆動回路を同一基板上に組み込むことも可能
である。しかしながら、多結晶シリコン薄膜トランジス
タはリーク電流が多いという問題点がある。特に薄膜光
電変換装置においては、多結晶シリコン薄膜トランジス
タを、光電変換素子で発生した電荷を外部に伝達する選
択用スイッチとして使用するため高いS/N比が要求さ
れるので、リ−ク電流の影響が深刻である。As thin film transistors used in thin film photoelectric conversion devices, those using amorphous silicon, polycrystalline silicon or the like are well known. Since a thin film transistor using polycrystalline silicon has higher mobility than a case using amorphous silicon, a driving circuit of a photoelectric conversion device can be manufactured over one substrate, which leads to downsizing and cost reduction. It is advantageous to
It is also possible to incorporate an external drive circuit on the same substrate. However, the polycrystalline silicon thin film transistor has a problem that it has a large leak current. In particular, in a thin film photoelectric conversion device, since a polycrystalline silicon thin film transistor is used as a selection switch for transmitting charges generated in a photoelectric conversion element to the outside, a high S / N ratio is required. Is serious.
【0004】このリーク電流を低減するため、多結晶シ
リコンに形成されたチャネル領域とソ−ス領域間および
チャネル領域とドレイン領域間に、不純物が低濃度に導
入されたゲ−トオフセット領域を形成したLDD(Ligh
tly Doped Drain )構造の薄膜トランジスタが広く採用
されている(特公平3−38755号公報参照)。以
下、上記従来のLDD構造のnチャネル薄膜トランジス
タを有する薄膜光電変換装置の製造工程について図4お
よび図5の工程断面説明図を参照して説明する。In order to reduce this leak current, a gate offset region having a low concentration of impurities is formed between the channel region and the source region formed in the polycrystalline silicon and between the channel region and the drain region. LDD (Ligh
A thin film transistor having a tly Doped Drain structure has been widely adopted (see Japanese Patent Publication No. 3-38755). Hereinafter, a manufacturing process of the thin film photoelectric conversion device having the n-channel thin film transistor having the conventional LDD structure will be described with reference to process cross-sectional explanatory views of FIGS.
【0005】先ず、絶縁性基板1上に多結晶シリコン膜
を形成し、フォトリソ・エッチングにより島状の多結晶
シリコン層2を形成した後、CVD法などでシリコン酸
化膜からなるゲート絶縁膜13を形成する。さらにその
上部にTaからなるゲート電極膜16を形成する(図4
(a))。次に、ゲート電極膜16をフォトリソ・エッ
チングにより島状のゲ−ト電極6′に形成し、このゲー
ト電極6′をマスクとして多結晶シリコン層2にPを低
濃度にイオン注入して、チャネル領域2a′の両脇にn
型の低濃度領域5を形成する(図4(b))。この時、
ゲ−ト電極6′がイオン注入のマスクとなるので、ゲ−
ト電極6′の直下部のチャネル領域2a′は不純物が導
入されていない。First, a polycrystalline silicon film is formed on an insulating substrate 1, an island-shaped polycrystalline silicon layer 2 is formed by photolithography and etching, and then a gate insulating film 13 made of a silicon oxide film is formed by a CVD method or the like. Form. Further, a gate electrode film 16 made of Ta is formed on top of it (FIG. 4).
(A)). Next, the gate electrode film 16 is formed on the island-shaped gate electrode 6'by photolithography and etching, and P is ion-implanted at a low concentration into the polycrystalline silicon layer 2 using this gate electrode 6'as a mask to form a channel. N on both sides of the area 2a '
A low concentration region 5 of the mold is formed (FIG. 4 (b)). This time,
Since the gate electrode 6 'serves as a mask for ion implantation,
Impurities are not introduced into the channel region 2a 'immediately below the gate electrode 6'.
【0006】次に、フォトリソによりゲート電極6′の
上部および側部を覆うようなフォトレジストマスク1
4′を形成し、上部から多結晶シリコン層2にPを高濃
度にイオン注入してn型の高濃度領域であるソ−ス領域
4a′およびドレイン領域4b′を形成する(図4
(c))。この時、ゲ−ト電極6′およびフォトレジス
トマスク14′がイオン注入のマスクとなるので、チャ
ネル領域2a′とn型の低濃度領域5のうちフォトレジ
ストマスク14′に覆われた部分はそのままの状態であ
る。上記2回のイオン注入により、多結晶シリコン層2
には、チャネル領域2a′と、n型の高濃度領域である
ソ−ス領域4a′およびドレイン領域4b′と、n型の
低濃度領域であるゲ−トオフセット領域5a′および5
b′が形成される。Next, a photoresist mask 1 covering the upper and side portions of the gate electrode 6'with photolithography.
4'is formed, and P is ion-implanted into the polycrystalline silicon layer 2 from above in a high concentration to form a source region 4a 'and a drain region 4b' which are n-type high concentration regions (FIG. 4).
(C)). At this time, since the gate electrode 6'and the photoresist mask 14 'serve as a mask for ion implantation, the portions of the channel region 2a' and the n-type low concentration region 5 covered by the photoresist mask 14 'remain unchanged. Is the state of. By the above-mentioned two times of ion implantation, the polycrystalline silicon layer 2
Are the channel region 2a ', the source region 4a' and the drain region 4b 'which are n-type high concentration regions, and the gate offset regions 5a' and 5 which are n-type low concentration regions.
b'is formed.
【0007】次に、フォトレジストマスク14′を除去
し、全面にSiO2をCVD法により被着形成し、トラ
ンジスタ特性を改善するために必要に応じて水素化処理
を行う。次に、光電変換素子を構成する下地電極膜2
0、半導体膜21、透明導電膜22を積層する(図5
(a))。次に、フォトリソによりフォトレジストマス
ク(図示せず)を形成し、透明導電膜22、半導体膜2
1をエッチング分離し、さらにフォトリソにより異なる
フォトレジストマスク(図示せず)を形成し下地電極膜
20をエッチング分離し、下地電極10′、半導体層1
1′、透明電極12′を順次積層した光電変換素子を形
成する(図5(b))。Next, the photoresist mask 14 'is removed, SiO 2 is deposited on the entire surface by the CVD method, and a hydrogenation process is performed if necessary to improve the transistor characteristics. Next, the base electrode film 2 that constitutes the photoelectric conversion element
0, the semiconductor film 21, and the transparent conductive film 22 are laminated (FIG. 5).
(A)). Next, a photoresist mask (not shown) is formed by photolithography, and the transparent conductive film 22 and the semiconductor film 2 are formed.
1 is separated by etching, a different photoresist mask (not shown) is formed by photolithography, and the base electrode film 20 is separated by etching to form the base electrode 10 'and the semiconductor layer 1
A photoelectric conversion element in which 1'and the transparent electrode 12 'are sequentially laminated is formed (FIG. 5B).
【0008】続いて、全面に層間絶縁膜7を形成した
後、フォトリソ・エッチングにより層間絶縁膜7にコン
タクトホールを形成し、この上部からAl膜を被着形成
した後、フォトリソ・エッチングにより配線8′を形成
し、これらの上部にパシベーション膜9を形成すること
により、薄膜光電変換装置の光電変換素子と選択用スイ
ッチの薄膜トランジスタを同時に完成させる(図5
(c))。Subsequently, after forming an interlayer insulating film 7 on the entire surface, a contact hole is formed in the interlayer insulating film 7 by photolithography and etching, and an Al film is formed on the contact hole, and then a wiring 8 is formed by photolithography etching. ′ Is formed and the passivation film 9 is formed on these, thereby completing the photoelectric conversion element of the thin film photoelectric conversion device and the thin film transistor of the selection switch at the same time (FIG. 5).
(C)).
【0009】[0009]
【発明が解決しようとする課題】上記薄膜光電変換装置
の製造方法によると、マスクを用いてフォトレジストを
パタ−ン化するフォトリソ工程の回数は7回であり、ま
た不純物導入のためのイオン注入の回数は2回である
が、読み出し部を低コスト化するためには、これらの回
数を低減することが要件となる。また、LDD構造多結
晶シリコン薄膜トランジスタの特性を左右するゲ−トオ
フセット領域5a′および5b′は、ゲ−ト電極6′作
製とフォトレジストマスク14′作製のための2回のフ
ォトリソ工程により形成されるので、マスク合わせにず
れが生じた場合には、ゲ−トオフセット領域5a′およ
び5b′の長さが設計値に対してばらつきを生じ、光電
変換素子の選択用スイッチとして用いた場合、読取り性
能の不均一性を生じるという問題点があった。According to the method of manufacturing a thin film photoelectric conversion device described above, the number of photolithography steps for patterning a photoresist using a mask is seven, and ion implantation for introducing impurities is performed. However, in order to reduce the cost of the reading unit, it is necessary to reduce the number of times. Further, the gate offset regions 5a 'and 5b' which influence the characteristics of the LDD structure polycrystalline silicon thin film transistor are formed by two photolithography processes for producing the gate electrode 6'and the photoresist mask 14 '. Therefore, when the mask alignment is deviated, the lengths of the gate offset regions 5a 'and 5b' vary with respect to the design values, and when used as a selection switch of the photoelectric conversion element, the reading is performed. There is a problem in that non-uniformity of performance occurs.
【0010】本発明は上記実情に鑑みてなされたもの
で、光電変換素子と、その画素選択用スイッチとしての
LDD構造多結晶シリコン薄膜トランジスタを備えた薄
膜光電変換装置を低コストで作製し、かつ、LDD構造
多結晶シリコン薄膜トランジスタの特性を均一にする製
造方法を提供するものである。The present invention has been made in view of the above circumstances, and a thin film photoelectric conversion device including a photoelectric conversion element and a polycrystalline silicon thin film transistor having an LDD structure as a pixel selection switch is manufactured at low cost, and An LDD structure polycrystalline silicon thin film transistor is provided with a manufacturing method for making the characteristics uniform.
【0011】[0011]
【課題を解決するための手段】上記目的を達成するため
請求項1の発明は、薄膜光電変換装置の製造方法におい
て以下の工程を具備することを特徴としている。絶縁性
基板上に多結晶シリコン膜を形成する工程。前記多結晶
シリコン膜をフォトリソ・エッチングにより多結晶シリ
コン層に形成する工程。前記多結晶シリコン層上にゲー
ト絶縁膜を形成する工程。前記ゲート絶縁膜上にゲート
電極膜を形成する工程。前記ゲート電極膜上にフォトリ
ソによりフォトレジストマスクを形成する工程。前記ゲ
−ト電極膜を等方的エッチングにより前記フォトレジス
トマスクより狭い幅のゲ−ト電極に加工する工程。前記
ゲート絶縁膜を異方的エッチングにより前記フォトレジ
ストマスクと同じ幅のゲ−ト絶縁層に加工する工程。前
記ゲート電極および前記ゲート絶縁層をマスクとして前
記多結晶シリコン層に不純物を導入して、不純物が高濃
度に導入されたソ−ス領域およびドレイン領域と、不純
物が低濃度に導入されたゲ−トオフセット領域を同時に
形成する工程。これらすべての上部に下地電極膜、半導
体膜および透明導電膜を順次積層する工程。フォトリソ
により前記ドレイン領域上(または前記ソ−ス領域上)
にフォトレジストマスクを形成する工程。前記フォトレ
ジストマスクを用いて前記透明導電膜、前記半導体膜お
よび前記下地電極膜をそれぞれエッチングして、下地電
極、半導体層および透明電極からなる光電変換素子を形
成する工程。これら全ての上部に層間絶縁膜を形成する
工程。前記層間絶縁膜にフォトリソ・エッチングにより
コンタクトホ−ルを形成する工程。これら全ての上部に
導電膜を形成する工程。前記導電膜をフォトリソ・エッ
チングにより配線に形成する工程。In order to achieve the above-mentioned object, the invention of claim 1 is characterized by comprising the following steps in a method of manufacturing a thin film photoelectric conversion device. A step of forming a polycrystalline silicon film on an insulating substrate. Forming the polycrystalline silicon film on the polycrystalline silicon layer by photolithography and etching. Forming a gate insulating film on the polycrystalline silicon layer; Forming a gate electrode film on the gate insulating film; Forming a photoresist mask on the gate electrode film by photolithography. Processing the gate electrode film into a gate electrode having a width narrower than that of the photoresist mask by isotropic etching. Process the gate insulating film into a gate insulating layer having the same width as the photoresist mask by anisotropic etching. Impurities are introduced into the polycrystalline silicon layer by using the gate electrode and the gate insulating layer as a mask, and a source region and a drain region in which impurities are introduced at a high concentration and a gate region in which impurities are introduced at a low concentration are introduced. Process of simultaneously forming the offset region. A step of sequentially laminating a base electrode film, a semiconductor film, and a transparent conductive film on all of these. On the drain region (or on the source region) by photolithography
Forming a photoresist mask on. A step of etching the transparent conductive film, the semiconductor film, and the base electrode film using the photoresist mask to form a photoelectric conversion element including the base electrode, the semiconductor layer, and the transparent electrode. A step of forming an interlayer insulating film on all of these. Forming a contact hole in the interlayer insulating film by photolithography etching. The process of forming a conductive film on all of these. A step of forming the conductive film on a wiring by photolithography / etching.
【0012】[0012]
【作用】本発明によれば、光電変換素子とその選択用ス
イッチとしてのLDD構造多結晶シリコン薄膜トランジ
スタとを有する薄膜光電変換装置を、5回のフォトリソ
工程と、1回の不純物導入工程とにより作製することが
できるので、コストを低減することができる。また、L
DD構造多結晶シリコン薄膜トランジスタの特性を左右
するゲ−トオフセット領域の長さを均一に形成すること
ができるので、薄膜光電変換装置において各光電変換素
子に対応するスイッチの特性が均一になり、読み取り性
能を均一にすることができる。According to the present invention, a thin film photoelectric conversion device having a photoelectric conversion element and a polycrystalline silicon thin film transistor having an LDD structure as a switch for selecting the photoelectric conversion element is manufactured by five photolithography steps and one impurity introduction step. Therefore, the cost can be reduced. Also, L
Since the length of the gate offset region that influences the characteristics of the DD-structure polycrystalline silicon thin film transistor can be formed uniformly, the characteristics of the switch corresponding to each photoelectric conversion element in the thin film photoelectric conversion device become uniform, and the reading can be performed. The performance can be made uniform.
【0013】[0013]
【実施例】以下、本発明に係る薄膜光電変換装置の製造
方法の一実施例について、図1乃至図3の工程断面説明
図を参照しながら説明する。先ず、絶縁性基板1上に、
例えばLPCVD(減圧化学気相成長)法によりa−S
iを約100nm堆積し、引き続き、例えばエキシマレ
ーザを照射してa−Siを多結晶シリコンとし、さらに
フォトリソ・エッチングにより多結晶シリコン層2を島
状に形成する。次に、例えばECRプラズマCVD法に
よりシリコン酸化膜を約100nm堆積してゲート絶縁
膜13を形成し、さらに、例えばスパッタ法によりTa
を約500nm着膜してゲート電極膜16を形成する。
次に、チャネル領域を形成する部分の上部に、フォトリ
ソによりフォトレジストマスク14を形成する(図1
(a))。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method of manufacturing a thin film photoelectric conversion device according to the present invention will be described below with reference to the cross sectional explanatory views of FIGS. First, on the insulating substrate 1,
For example, a-S is formed by LPCVD (Low Pressure Chemical Vapor Deposition) method.
i is deposited to a thickness of about 100 nm, and then a-Si is converted to polycrystalline silicon by irradiating, for example, an excimer laser, and the polycrystalline silicon layer 2 is formed in an island shape by photolithography and etching. Next, a gate oxide film 13 is formed by depositing a silicon oxide film to a thickness of about 100 nm by, for example, ECR plasma CVD method, and further Ta is formed by, for example, a sputtering method.
Is deposited to a thickness of about 500 nm to form the gate electrode film 16.
Next, a photoresist mask 14 is formed by photolithography on the portion where the channel region is to be formed (FIG. 1).
(A)).
【0014】次に、フォトレジストマスク14をマスク
として、例えばCF4とO2ガスを用いてCDE(ケミカ
ルドライエッチング)法によりゲート電極膜16を等方
的にエッチングし、フォトレジストマスク14より幅が
狭いゲート電極6を形成する(図1(b))。続いて、
同じフォトレジストマスク14をマスクとして、例えば
CHF3とO2ガスとを用いてRIE(リアクティブ・イ
オン・エッチング)法により、ゲート絶縁膜13を異方
的にエッチングすることで、フォトレジストマスク14
と同じ幅で、ゲート電極6より広い幅のゲ−ト絶縁層3
を形成する(図1(c))。ここで、ゲ−ト電極6とゲ
−ト絶縁層3はいずれも同一のフォトレジストマスク1
4を用いたエッチングにより形成しているので、左右対
称に形成される。Next, using the photoresist mask 14 as a mask, the gate electrode film 16 is isotropically etched by the CDE (chemical dry etching) method using CF 4 and O 2 gas, for example, and the width of the gate electrode film 16 is made wider than that of the photoresist mask 14. Forming a narrow gate electrode 6 (FIG. 1B). continue,
Using the same photoresist mask 14 as a mask, the gate insulating film 13 is anisotropically etched by, for example, RIE (reactive ion etching) method using CHF 3 and O 2 gas.
Gate insulating layer 3 having the same width as that of the gate electrode 6 but wider than the gate electrode 6.
Are formed (FIG. 1C). Here, the gate electrode 6 and the gate insulating layer 3 are the same photoresist mask 1
Since it is formed by etching using No. 4, it is formed symmetrically.
【0015】次に、フォトレジストマスク14を剥離し
た後、例えば非質量分離型のイオンドーピング法によ
り、上方よりゲート電極6及びゲート絶縁層3をマスク
として多結晶シリコン層2にP等の不純物イオンを導入
する。この時、多結晶シリコン層2は、1回の不純物導
入工程により、ゲ−ト電極6でマスクされるチャネル領
域2aには不純物イオンが全く導入されず、ゲ−ト絶縁
層3のみでマスクされる領域は低濃度に不純物が導入さ
れたゲ−トオフセット領域5aおよび5bとなり、マス
クのない部分は高濃度に不純物イオンが導入されたソー
ス領域4aおよびドレイン領域4bに形成される(図2
(a))。ここで、ゲ−ト電極6とゲ−ト絶縁層3が左
右対称に形成されているので、ゲ−トオフセット領域5
aおよび5bの長さは等しい。Next, after removing the photoresist mask 14, impurity ions such as P are added to the polycrystalline silicon layer 2 from above by the non-mass separation type ion doping method using the gate electrode 6 and the gate insulating layer 3 as a mask from above. To introduce. At this time, in the polycrystalline silicon layer 2, no impurity ions are introduced into the channel region 2a masked by the gate electrode 6, and only the gate insulating layer 3 is masked by one impurity introduction step. Regions become gate offset regions 5a and 5b in which impurities are introduced at a low concentration, and regions without a mask are formed in source regions 4a and drain regions 4b in which impurity ions are introduced at a high concentration (FIG. 2).
(A)). Here, since the gate electrode 6 and the gate insulating layer 3 are formed symmetrically, the gate offset region 5
The lengths of a and 5b are equal.
【0016】次に、例えば、スパッタ法によりTiから
なる下地電極膜20を約100nm堆積し、さらにプラ
ズマCVD法によりアモルファスSiからなる半導体膜
21を約1μm堆積し、さらにスパッタ法によりITO
からなる透明導電膜22を約60nm堆積する。続い
て、フォトリソにより、ドレイン領域4bの一部を覆う
ように光電変換素子形成用のフォトレジストマスク15
を形成する(図2(b))。次に、このフォトレジスト
マスク15を用いて、ウェットエッチングにより透明導
電膜22をエッチングし、さらに、RIEにて半導体膜
21をエッチングし、さらに下地電極膜20をウェット
エッチングし、下地電極10、半導体層11、透明電極
12を順次積層した光電変換素子を形成し、フォトレジ
ストマスク15を剥離する(図2(c))。Next, for example, a base electrode film 20 made of Ti is deposited to a thickness of about 100 nm by a sputtering method, a semiconductor film 21 made of amorphous Si is further deposited to a thickness of about 1 μm by a plasma CVD method, and further ITO is formed by a sputtering method.
The transparent conductive film 22 made of is deposited to a thickness of about 60 nm. Then, by photolithography, a photoresist mask 15 for forming a photoelectric conversion element is formed so as to cover a part of the drain region 4b.
Are formed (FIG. 2B). Next, using this photoresist mask 15, the transparent conductive film 22 is etched by wet etching, the semiconductor film 21 is further etched by RIE, and the base electrode film 20 is further wet-etched to form the base electrode 10 and the semiconductor. A photoelectric conversion element in which the layer 11 and the transparent electrode 12 are sequentially laminated is formed, and the photoresist mask 15 is peeled off (FIG. 2C).
【0017】次に、例えば、プラズマCVD法によりシ
リコン酸化膜を約1μm堆積して層間絶縁膜7を形成
し、続いて、フォトリソによりコンタクトホ−ルを形成
し、例えば、スパッタ法により約1μmのAl−Cu膜
を着膜してフォトリソ・エッチングによりパターニング
して配線8を形成する。さらに、例えば、プラズマCV
D法によりシリコン酸化膜を約1μm堆積してパシベー
ション膜9を形成することにより薄膜光電変換装置が完
成する(図3)。Next, for example, a silicon oxide film is deposited to a thickness of about 1 μm by a plasma CVD method to form an interlayer insulating film 7, and then a contact hole is formed by photolithography, for example, a sputtering method to a thickness of about 1 μm. An Al-Cu film is deposited and patterned by photolithography and etching to form the wiring 8. Furthermore, for example, plasma CV
A thin film photoelectric conversion device is completed by forming a passivation film 9 by depositing a silicon oxide film of about 1 μm by the D method (FIG. 3).
【0018】上記薄膜光電変換装置の製造方法において
は、フォトリソ工程を5回、不純物導入を1回行うこと
で薄膜光電変換装置が作製できるので、従来の製造方法
と比較して工程を低減でき、低コスト化することができ
る。また、ゲート電極6とゲ−ト絶縁層3を同一のフォ
トレジストマスク14を用いたエッチングにより形成し
た後、このゲ−ト電極6とゲ−ト絶縁層3をマスクとし
て上方から不純物イオンを導入しているので、低濃度不
純物領域のゲ−トオフセット領域5aおよび5bを自己
整合的に作製できるため、ゲ−トオフセット領域5aお
よび5bの長さのばらつきを減少でき、光電変換素子で
発生した電荷のスイッチとしての性能の均一化を図るこ
とができる。In the method of manufacturing a thin film photoelectric conversion device described above, the thin film photoelectric conversion device can be manufactured by performing the photolithography step 5 times and the impurity introduction once, so that the number of steps can be reduced as compared with the conventional manufacturing method. The cost can be reduced. Further, after the gate electrode 6 and the gate insulating layer 3 are formed by etching using the same photoresist mask 14, impurity ions are introduced from above by using the gate electrode 6 and the gate insulating layer 3 as a mask. Therefore, since the gate offset regions 5a and 5b of the low concentration impurity regions can be formed in a self-aligned manner, the variation in the length of the gate offset regions 5a and 5b can be reduced, which is caused by the photoelectric conversion element. It is possible to make the performance of the charge switch uniform.
【0019】上記実施例において用いた方法は必ずしも
これに限るものではない。例えば、a−Siの堆積には
プラズマCVD法、ECR−CVD法、スパッタ法、蒸
着法、などの方法を用いることができる。また、多結晶
シリコン膜は、a−SiをArレーザ、電子線、赤外線
ランプ等によりアニールして形成するなど、材料に適し
た方法で形成して用いることができる。また、ゲート絶
縁膜などの絶縁膜は、窒化シリコン、酸化窒化シリコン
などでも良く、その成膜方法は、LPCVD法、ECR
−CVD法、スパッタ法、蒸着法など材料に適した方法
を用いればよい。また、ゲート電極および光電変換素子
の下地電極はTi,W,Cr,Mo,Al,Cuなどの
金属材料、およびそれらの合金材料、およびそれらの珪
化材料などでも良く、その着膜方法も材料に適したもの
を用いれば良い。また、光電変換素子の加工方法は、C
DE法、ECRエッチング法、ヘリコン波エッチング法
などを用いてもよい。The method used in the above embodiment is not necessarily limited to this. For example, a plasma CVD method, an ECR-CVD method, a sputtering method, an evaporation method, or the like can be used for depositing a-Si. Further, the polycrystalline silicon film can be formed and used by a method suitable for the material such as a-Si being annealed by an Ar laser, an electron beam, an infrared lamp or the like. The insulating film such as the gate insulating film may be silicon nitride, silicon oxynitride, or the like, and the film forming method is LPCVD method or ECR.
-A method suitable for the material such as a CVD method, a sputtering method, or a vapor deposition method may be used. Further, the gate electrode and the base electrode of the photoelectric conversion element may be made of metal materials such as Ti, W, Cr, Mo, Al, Cu, their alloy materials, and their silicidized materials. Any suitable one may be used. Further, the processing method of the photoelectric conversion element is C
A DE method, an ECR etching method, a helicon wave etching method, or the like may be used.
【0020】[0020]
【発明の効果】本発明によれば、光電変換素子と、画素
選択用スイッチとしてのLDD構造多結晶シリコン薄膜
トランジスタを兼ね備えた薄膜光電変換装置の作製にお
いて、フォトリソおよび不純物導入の工程を従来と比較
して低減することができ、低コスト化できる。また、L
DD構造多結晶シリコン薄膜トランジスタにおいて、そ
の特性を左右するゲ−トオフセット領域の長さを均一に
形成できるので、薄膜光電変換装置の読み取り性能が均
一になり、画像品質を均一にすることができる。According to the present invention, in the production of a thin film photoelectric conversion device having a photoelectric conversion element and a polycrystalline silicon thin film transistor having an LDD structure as a pixel selection switch, the photolithography and impurity introduction steps are compared with those in the prior art. Can be reduced, and cost can be reduced. Also, L
Since the length of the gate offset region which influences the characteristics of the DD structure polycrystalline silicon thin film transistor can be made uniform, the reading performance of the thin film photoelectric conversion device becomes uniform and the image quality can be made uniform.
【図1】(a)(b)(c)は本発明に係る薄膜光電変
換装置の製造方法の主要工程を示す断面説明図である。1A, 1B, and 1C are cross-sectional explanatory views showing main steps of a method of manufacturing a thin film photoelectric conversion device according to the present invention.
【図2】(a)(b)(c)は本発明に係る薄膜光電変
換装置の製造方法の主要工程を示す断面説明図である。2 (a), (b) and (c) are cross-sectional explanatory views showing main steps of a method of manufacturing a thin film photoelectric conversion device according to the present invention.
【図3】本発明に係る薄膜光電変換装置の製造方法の主
要工程を示す断面説明図である。FIG. 3 is a cross-sectional explanatory view showing main steps of a method of manufacturing a thin film photoelectric conversion device according to the present invention.
【図4】(a)(b)(c)は従来の薄膜光電変換装置
の製造方法の主要工程を示す断面説明図である。4A, 4B, and 4C are cross-sectional explanatory views showing main steps of a conventional method for manufacturing a thin film photoelectric conversion device.
【図5】(a)(b)(c)は従来の薄膜光電変換装置
の製造方法の主要工程を示す断面説明図である。5A, 5B, and 5C are cross-sectional explanatory views showing main steps of a conventional method for manufacturing a thin film photoelectric conversion device.
1…絶縁性基板、 2…多結晶シリコン層、 2a…チ
ャネル領域、 3…ゲート絶縁層、 4a…ソース領
域、 4b…ドレイン領域、 5a,5b…ゲ−トオフ
セット領域、 6…ゲート電極、 7…層間絶縁膜、
8…配線、 9…パシベーション膜、 10…下地電
極、 11…半導体層、 12…透明電極、13…ゲ−
ト絶縁膜、 14,15…フォトレジストマスク、 1
6…ゲ−ト電極膜、 20…下地電極膜、 21…半導
体膜、 22…透明導電膜DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 2 ... Polycrystalline silicon layer, 2a ... Channel region, 3 ... Gate insulating layer, 4a ... Source region, 4b ... Drain region, 5a, 5b ... Gate offset region, 6 ... Gate electrode, 7 ... Interlayer insulating film,
8 ... Wiring, 9 ... Passivation film, 10 ... Base electrode, 11 ... Semiconductor layer, 12 ... Transparent electrode, 13 ... Gate
Insulating film, 14, 15 ... Photoresist mask, 1
6 ... Gate electrode film, 20 ... Base electrode film, 21 ... Semiconductor film, 22 ... Transparent conductive film
Claims (1)
る工程と、前記多結晶シリコン膜をフォトリソ・エッチ
ングにより多結晶シリコン層に形成する工程と、前記多
結晶シリコン層上にゲート絶縁膜を形成する工程と、前
記ゲート絶縁膜上にゲート電極膜を形成する工程と、前
記ゲート電極膜上にフォトリソによりフォトレジストマ
スクを形成する工程と、前記ゲ−ト電極膜を等方的エッ
チングにより前記フォトレジストマスクより狭い幅のゲ
−ト電極に加工する工程と、前記ゲート絶縁膜を異方的
エッチングにより前記フォトレジストマスクと同じ幅の
ゲ−ト絶縁層に加工する工程と、前記ゲート電極および
前記ゲート絶縁層をマスクとして前記多結晶シリコン層
に不純物を導入して、不純物が高濃度に導入されたソ−
ス領域およびドレイン領域と、不純物が低濃度に導入さ
れたゲ−トオフセット領域を同時に形成する工程と、こ
れらすべての上部に下地電極膜、半導体膜および透明導
電膜を順次積層する工程と、フォトリソにより前記ドレ
イン領域上(または前記ソ−ス領域上)にフォトレジス
トマスクを形成する工程と、前記フォトレジストマスク
を用いて前記透明導電膜、前記半導体膜および前記下地
電極膜をそれぞれエッチングして、下地電極、半導体層
および透明電極からなる光電変換素子を形成する工程
と、これら全ての上部に層間絶縁膜を形成する工程と、
前記層間絶縁膜にフォトリソ・エッチングによりコンタ
クトホ−ルを形成する工程と、これら全ての上部に導電
膜を形成する工程と、前記導電膜をフォトリソ・エッチ
ングにより配線に形成する工程と、を具備することを特
徴とする薄膜光電変換装置の製造方法。1. A step of forming a polycrystalline silicon film on an insulating substrate, a step of forming the polycrystalline silicon film into a polycrystalline silicon layer by photolithography and etching, and a gate insulating film on the polycrystalline silicon layer. A step of forming a gate electrode film on the gate insulating film, a step of forming a photoresist mask on the gate electrode film by photolithography, and an isotropic etching of the gate electrode film. Processing a gate electrode having a width narrower than that of the photoresist mask, processing the gate insulating film into a gate insulating layer having the same width as the photoresist mask by anisotropic etching, and the gate electrode An impurity is introduced into the polycrystalline silicon layer by using the gate insulating layer as a mask, and the impurity is introduced at a high concentration.
A gate region, a drain region, and a gate offset region in which impurities are introduced at a low concentration, and a step of sequentially laminating a base electrode film, a semiconductor film, and a transparent conductive film on top of all of them, and a photolithography process. Forming a photoresist mask on the drain region (or on the source region) by etching the transparent conductive film, the semiconductor film and the base electrode film respectively using the photoresist mask, A step of forming a photoelectric conversion element composed of a base electrode, a semiconductor layer and a transparent electrode, and a step of forming an interlayer insulating film on all of these,
The method further comprises a step of forming contact holes in the interlayer insulating film by photolithography / etching, a step of forming a conductive film on all of these, and a step of forming the conductive film in a wiring by photolithography / etching. A method for manufacturing a thin film photoelectric conversion device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7163098A JPH08335687A (en) | 1995-06-07 | 1995-06-07 | Method for manufacturing thin film photoelectric conversion device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7163098A JPH08335687A (en) | 1995-06-07 | 1995-06-07 | Method for manufacturing thin film photoelectric conversion device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08335687A true JPH08335687A (en) | 1996-12-17 |
Family
ID=15767147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7163098A Pending JPH08335687A (en) | 1995-06-07 | 1995-06-07 | Method for manufacturing thin film photoelectric conversion device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08335687A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2396744A (en) * | 1999-03-10 | 2004-06-30 | Matsushita Electric Industrial Co Ltd | Ldd tft |
| JP2009182134A (en) * | 2008-01-30 | 2009-08-13 | Fujifilm Corp | Method for manufacturing electromagnetic wave detection element |
| JP2009267343A (en) * | 2008-10-29 | 2009-11-12 | Epson Imaging Devices Corp | Solid state imaging apparatus and manufacturing method thereof |
| JP2009283896A (en) * | 2008-04-23 | 2009-12-03 | Epson Imaging Devices Corp | Solid-state image pickup device and manufacturing method thereof |
| WO2021134751A1 (en) * | 2020-01-02 | 2021-07-08 | Boe Technology Group Co., Ltd. | Thin film transistor and fabrication method thereof, display panel and display apparatus |
-
1995
- 1995-06-07 JP JP7163098A patent/JPH08335687A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2396744A (en) * | 1999-03-10 | 2004-06-30 | Matsushita Electric Industrial Co Ltd | Ldd tft |
| GB2396744B (en) * | 1999-03-10 | 2004-08-18 | Matsushita Electric Industrial Co Ltd | A semiconductor element |
| JP2009182134A (en) * | 2008-01-30 | 2009-08-13 | Fujifilm Corp | Method for manufacturing electromagnetic wave detection element |
| JP2009283896A (en) * | 2008-04-23 | 2009-12-03 | Epson Imaging Devices Corp | Solid-state image pickup device and manufacturing method thereof |
| US8497562B2 (en) | 2008-04-23 | 2013-07-30 | Epson Imaging Devices Corporation | Solid-state image pickup device |
| JP2009267343A (en) * | 2008-10-29 | 2009-11-12 | Epson Imaging Devices Corp | Solid state imaging apparatus and manufacturing method thereof |
| WO2021134751A1 (en) * | 2020-01-02 | 2021-07-08 | Boe Technology Group Co., Ltd. | Thin film transistor and fabrication method thereof, display panel and display apparatus |
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