JPH08340480A - Television camera system using digital signal processing. - Google Patents

Abstract

(57) [Abstract] [Purpose] When changing the number of CCD pixels, aspect ratio, etc. in a television camera device that performs digital signal processing, optimal video signal processing can be performed without changing units or increasing the circuit scale. , Is intended to be realized. [Structure] A ROM load type FPGA is used for processing a digital image A / D converted at a CCD clock rate, and the digital signal processing circuit in the FPGA is changed according to the number of CCD pixels or the aspect ratio of the screen. It is equipped with multiple ROMs that store different programs for each CCD pixel number or aspect ratio, and is linked to the pixel number or aspect ratio by using a means for detecting the pixel number or aspect ratio of the camera head by an external system or operation. A television camera system characterized in that the ROM data selected from a plurality of pieces is loaded into the FPGA.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to signal processing of a television camera which can perform digital signal processing and can change the aspect ratio or the number of pixels of CCD.

[0002]

2. Description of the Related Art With the technical progress of CCD elements used in television cameras, the number of CCD pixels is increasing year by year. Therefore, a camera user such as a broadcasting station may use a plurality of cameras having different numbers of pixels at the same time.
There is an increasing demand for television camera systems that can meet this demand. Especially in recent years, the aspect ratio of the screen (aspect ratio)
Has been widened from the conventional 4: 3 to 16: 9, and a broadcasting camera or the like is required to have a function of switching the aspect ratio of 4: 3 and 16: 9. By the way, as a method for changing the aspect ratio of 4: 3 and 16: 9, there are a method of changing the CCD reading method and a method of changing the writing and reading rates (clock frequency) using a memory. In either case, the effective CCD driving frequency changes.

Conventionally, even if the number of pixels of the CCD changes, when the camera control unit (hereinafter referred to as CCU) performs analog signal processing, there are few cases where the circuit needs to be changed, and it is possible to deal with it relatively easily and there is no problem. It was However, in recent years, digitalization has been a trend, and the signal processing of the camera has also been digitized, and the change in the number of CCD pixels in the camera head causes the following problems. That is, normally, in cameras that require the highest image quality, such as broadcast cameras, in order to prevent noise such as beat and folding distortion,
A method is adopted in which the clock rate of A / D conversion required when performing digital signal processing is adjusted to the CCD clock. When performing digital signal processing, for example, the frequency characteristic of the filter also changes depending on the signal processing rate. Therefore, in the case of a camera system that performs digital signal processing, when the number of pixels of CCD or the aspect ratio changes, the corresponding signal processing is performed. Requires circuit modification.

[0004]

As described above, in the conventional camera system that performs digital signal processing, it is necessary to change the signal processing circuit when the number of CCD pixels used or the aspect ratio changes. Therefore, in the conventional method, C
It is necessary to replace the corresponding signal processing unit according to the number of pixels or aspect ratio of the CD, or to provide a plurality of digital circuits that match each signal processing rate, resulting in an enormous circuit scale. Have. An object of the present invention is to eliminate the above-mentioned drawbacks and to perform digital signal processing adapted to a change in the number of pixels or aspect ratio of CCD without causing a large increase in circuit scale.

[0005]

In order to achieve the above object, the present invention provides a television camera system for performing video signal processing in the form of digital signals, in which the number of CCD pixels, aspect ratio, etc. of the television camera are changed. A field programmable logic device of ROM load type (hereinafter referred to as FPGA) is used in the digital signal processing circuit that needs to be changed according to the signal processing rate that changes with the number of CCD pixels and aspect ratio of the television camera. Based on the information indicating
The configuration in A is changed and set to the configuration of the corresponding signal processing circuit.

[0006]

According to the present invention, a plurality of ROMs in which the circuit configuration information corresponding to the number of pixels of CCD, the aspect ratio, etc. are written.
By loading the ROM program selected from among the above into the FPGA that performs digitized video signal processing, a digital signal suitable for the number of pixels, aspect ratio, etc. of the CCD can be achieved without significantly increasing the circuit scale. Processing becomes possible.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in FIG.
The present invention will be described in detail. The output video signal obtained from the CCD 1 is subjected to necessary processing such as amplification in the analog signal processing circuit 2 and then supplied to the A / D conversion circuit 3 to be supplied to the CCD.
It is sampled at the same rate as the driving clock and converted into a digital signal. Digitized image data, regardless of the number of CCD pixels, aspect ratio, etc.
Necessary signal processing is performed by the first digital signal processing circuit 4 that performs video signal processing (eg, gamma correction, knee correction, etc.) that can be processed by the same circuit. After that, it is composed of a field programmable logic device (FPGA), etc., and under the control of the central control unit (CPU) 5, C
The signal is supplied to the second digital signal processing circuit 6 which performs digital signal processing (for example, aperture correction, filtering processing, etc.) according to the number of pixels of CD 1, aspect ratio, and the like. Then, the signal subjected to such processing is D / A as a camera output of an analog or digital signal.
It is output through the conversion circuit 7 and the digital interface circuit 8.

Now, here, the ROM load type (SR
An AM type) FPGA configuration and a method of changing the signal processing circuit configuration using this FPGA according to the number of pixels of CCD, aspect ratio, etc. will be briefly described. As shown in FIG. 4, the ROM load type FPGA has a logic cell array unit 30 in which logic can be freely constructed by controlling switching transistors for wiring.
And a load circuit section 32 for reading data from an external ROM into the RAM section 31 when the power is turned on or when a load instruction from the outside is received. To be done.
That is, the signal processing circuit configured by such an FPGA can freely change the logical configuration by changing the data written in the external ROM.

In the present invention, by utilizing these characteristics, for example, a plurality of ROMs in which circuit data corresponding to a plurality of CCD pixel samplings and aspect ratios, which can be predicted in advance, are written are mounted in a camera device. Ap CP
Under the control of U, the corresponding one is selected from these ROMs, and the circuit data is loaded into the FPGA, so that the FPGA is changed to the configuration of the digital signal processing circuit according to the number of CCD pixels, the aspect ratio, etc. It is a thing.

Below, in FIG. 3, the CPU indicated by the broken line in FIG.
5, the detailed configuration of the second digital signal processing circuit 6 using an FPGA whose circuit configuration is changed according to the number of CCD pixels, aspect ratio, etc. will be shown, and its operation will be described. CPU
Reference numeral 5 detects pixel number information of the CCD mounted on the camera device, aspect ratio conversion operation information from an aspect ratio conversion operation unit (not shown), and sends this information to the ROM selection circuit 24. Based on this instruction, the ROM selection circuit 24 selects each ROM containing the signal processing circuit data suitable for the number of CCD pixels and the aspect ratio from the plurality of ROMs 21 to 23, and loads the load instruction when the power is turned on. When these are received, these data are controlled to be loaded into the FPGA 20. This enables the FPGA20
Has a signal processing circuit configuration adapted to the number of CCD pixels and the aspect ratio.

Here, for example, when the clock frequency changes due to a change in the number of pixels of the CCD, the characteristics of the digital filter formed in the FPGA change as shown in FIGS. 5A and 5B. However, depending on the number of pixels of the CCD,
As shown in (A) and (B) of FIG.
It is possible to maintain almost the same filter characteristics by changing to a circuit configuration having different filter coefficients and tap numbers. By doing so, in the present invention, the number of pixels of the CCD,
Digital signal processing suitable for aspect ratio etc. becomes possible.

FIG. 2 shows a second embodiment of the present invention. In this example, the present invention is applied to a camera head and a camera control unit (hereinafter referred to as CCU) separated type camera, which is often found in broadcast cameras and the like. In such a camera system, CCDs with different numbers of pixels in the same CCU
There is a case where a camera head with is connected or the aspect ratio is changed on the camera head side. Even in such a case, the present embodiment enables the CCU to perform digital signal processing suitable for the number of pixels of CCD, aspect ratio and the like.

The structure and operation of this embodiment will be described below with reference to FIG. Similar to the first embodiment, the camera head 10
1, the video signal output of the CCD 1 is subjected to necessary processing such as amplification in the analog signal processing circuit 2 and then input to the A / D conversion circuit 3 where it is sampled at the same rate as the CCD drive clock and converted into a digital signal. To be converted. The digitized image data is processed by the first digital signal processing circuit 4 that performs video signal processing (eg gamma correction, knee correction, etc.) that can be processed by the same circuit regardless of the number of pixels of CCD, aspect ratio, etc. , Required signal processing. The image-processed image signal data is sent to the digital signal transmission unit 13 and the CPU 12 of the camera head 10 including CCD pixel number information and aspect ratio conversion operation information.
Is multiplexed with the output data of and sent to the CCU 11.

The digital signal receiving unit 14 in the CCU 11 separates the CPU data and the image data, and sends the former to the CPU 15 of the CCU 11 and the latter to the digital signal processing circuit 16 of the CCU 11 composed of the ROM load type FPGA. . The configuration of the digital signal processing circuit 16 is exactly the same as that of the digital signal processing circuit 6 of the first embodiment shown in FIG. 3, and the number of pixels of CCD, the aspect ratio, etc. are controlled by the control of the CPU 15 of the CCU 11. Appropriate signal processing is performed. Then, the digital video signal 17 which has been subjected to such processing is output through the D / A conversion circuit 7 and the digital interface circuit 8 as a camera output of an analog or digital signal.

As described above, according to the present invention, it is possible to replace the units which are required in the conventional system without changing the units.
It is possible to connect camera heads having CCDs with different numbers of pixels to the same CCU, and it is possible to greatly improve the operability of the camera system. In the above description, based on the data stored in the ROM, the FP is used as an element that performs digital signal processing suitable for the number of pixels of the CCD.
Although the GA is used, a DSP (digital signal processor) may be used instead of the GA to obtain the same effect.

[0016]

As described above, when the present invention is used, C
It is possible to easily perform digital signal processing that is suitable for the number of CD pixels, aspect ratio, etc.
The cost can be reduced and the operability of the system can be improved, and the effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a digital signal processing circuit configured by the FPGA of the present invention.

FIG. 4 is a schematic diagram showing a configuration of a ROM load type FPGA.

FIG. 5 is a diagram showing frequency characteristics of a digital filter which changes according to a clock frequency.

FIG. 6 is a diagram showing a configuration of a filter circuit in the FPGA which is changed by ROM data.

[Explanation of symbols]

1: CCD 5, 12, 15: CPU 6, 16: Digital signal processing circuit composed of FPGA

Claims (2)

[Claims] 1. A television camera system that performs video signal processing in the form of a digital signal, needs to be changed according to a signal processing rate that changes with a change in the number of CCD pixels, aspect ratio, etc. of the television camera. ROM load type field programmable logic device (hereinafter referred to as FPGA
Based on the information indicating the number of CCD pixels, aspect ratio, etc. of the television camera.
A television camera system in which the configuration in A is changed and set to the configuration of a corresponding signal processing circuit. 2. A / A video signal at CCD clock rate
In a television camera system that performs D conversion and performs video signal processing in the form of a digital signal, a ROM load type FPGA is used for the digital signal processing, and the inside of the FPGA is adjusted according to the number of CCD pixels or the aspect ratio of the television camera. Represents a plurality of ROMs storing different programs (circuit configuration information) corresponding to various CCD pixel numbers or aspect ratios for changing the digital signal processing circuit of, and the CCD pixel number information or aspect ratio conversion operation. Means to detect information,
The FPG is provided with means for loading the data stored in the corresponding ROM in association with the detected CCD pixel number information or the aspect ratio conversion operation information.
A television camera system in which the configuration in A is changed and set to the configuration of a corresponding signal processing circuit.