JPH0834489B2 - AFC circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an AFC circuit used for stabilizing the center frequency of a digital modulation signal input to a demodulator when demodulating the digital modulation signal. .

2. Description of the Related Art Generally, when demodulating a digitally modulated signal that is modulated with a digital signal, an AFC circuit is used to suppress various frequency fluctuations in order to improve the demodulation characteristics of the demodulation circuit, especially the bit error rate characteristic. It is common practice to stabilize the center frequency of the digitally modulated signal input to. A conventional example of such an AFC circuit is shown in FIG.

In the figure, the digital modulation signal input to the frequency conversion circuit 100 is multiplied by the oscillation signal of the voltage controlled oscillator (VCO) 101 by the mixer 102 to be frequency converted. The frequency-converted digital modulation signal is input to the demodulation circuit 103,
After being band-limited by a band-pass BPF (band-pass filter) 104, the phase detector 105 multiplies the carrier fc output from the carrier recovery circuit 106 and demodulates. In this case, if the digital modulation signal is a 4-phase quadrature modulation signal, the demodulation signal is
It is demodulated as two signals of I and Q orthogonal to each other. Then, the demodulated two signals are fed back to the carrier wave reproduction circuit 106, and the carrier wave fc is reproduced. In addition, the carrier recovery circuit 106
Also outputs a synchronization detection signal 107 indicating the synchronization or non-synchronization of the carrier wave. The AFC circuit includes a microprocessor 108, a frequency divider 109 that divides a high-frequency signal by A (A ≧ 2), a counter 110 that counts the divided high-frequency signal controlled by the microprocessor 108 for a certain period, and a microprocessor 108. D / A converter 111 controlled and outputs AFC voltage for VCO 101
Composed of.

Next, the AFC circuit portion will be described. First, the digitally modulated signal band-limited by the band-limiting BPF 104 is frequency-divided by the frequency divider 109 and input to the counter 110. The microprocessor 108 operates the counter 110 for a certain period of time by the control signal LE112. The counter 110 counts the frequency-divided digital modulation signals and inputs the count value to the microprocessor 108 via the data line 113. The microprocessor 108 compares and counts the count value with a reference value set on the program, and D /
Send data to the A converter 111, change the AFC voltage, and
Control. By thus adjusting the oscillation frequency of the VCO 101, the frequency of the digital modulation signal input to the demodulation circuit 103 is stabilized.

Also, when comparing and calculating the count value and the reference value, if the allowable error range is set, it is not necessary to control the VCO 101 when the counted value is within the allowable error range, so when synchronizing the carrier wave,
The frequency of changing the VCO101 oscillation frequency can be suppressed. By the way, the control method of the VCO 101 until the carrier wave is synchronized is performed as follows in consideration of the followability of the carrier wave reproduction circuit 106.

As shown in FIG. 7, when the carrier wave is asynchronous (synchronization detection signal
(107 is low level), it sweeps at high speed up to near the carrier sync frequency (AFC voltage V ₁ → V ₂ ), and at low speed near the sync frequency (V ₂ → V ₃ ). AFC voltage is V ₃
At this time, when the carrier wave is synchronized (the synchronization detection signal 107 is high level), the sweep is stopped. Now, it is assumed that the center frequency of the frequency divider 109 is 140 MHz and the variable range of the VCO is +/− 5 MHz.
At this time, the frequency range of the digital modulation signal input to the frequency divider 109 is 140 MHz +/- 5 MHz. First, when the frequency count resolution during high-speed sweep is 200 kHz, the count value of the counter 110 is 700 counts, and when the frequency divider 109 is divided by 40, the operating time of the counter 110 is 0.
2 msec. The count value of 140 +/- 5MHz becomes 675 to 725 count, which is 1010100011B to 10110 when expressed in binary.
It becomes 10101B, and a counter of 7 to 10 bits is required as the counter 110.

On the other hand, the frequency count resolution during slow sweep is set to 20
If it is set to kHz and calculated in the same way, the operating time of the counter 110 is
It becomes 2 msec, and the count value of 140 MHz +/- 5 MHz is 6750 to 7250, which is 1101001011110B to 1110 when expressed in binary.
Since 001010010B, the number of bits of counter 110 is 11 to 1
It will be 3 bits.

The problem to be solved by the invention is that, in the above-mentioned conventional example, since the digital modulation signal is directly divided and counted by the counter, if the C / N of the digital modulation signal is lowered, the ratio of noise superimposed on the signal increases. The frequency cannot be accurately counted, and if the frequency is adjusted to the reference value set by the program of the microprocessor, the frequency of the digital modulation signal does not match the frequency that it should be, and the carrier wave is not synchronized. In such a case, the VCO oscillation frequency is swept until the carrier wave is synchronized, and even if a new reference value is set when synchronization is achieved, the carrier wave synchronization range has a certain width, so the input digital modulation signal Detune with the correct carrier,
It deteriorates the demodulation characteristics. In this case, since the spectrum of the digital modulation signal has a spread, jitter remains in the frequency-divided signal, which further adversely affects at low C / N.

Further, if delay occurs or the amplitude characteristic changes due to the temperature characteristic of the band limiting BPF 104, the digitally modulated signal undergoes phase or amplitude modulation and signal distortion becomes large, and accurate frequency counting cannot be performed. Further, as described above, there is a drawback that the number of bits of the counter increases in order to increase the frequency resolution during low speed sweep.

The present invention solves such a problem, not only has a simple structure and allows for cost reduction, but also stabilizes the frequency of the digital modulation signal input to the demodulation circuit without being affected by the temperature characteristics of the circuit elements and reproduces it. It is an object of the present invention to provide an AFC circuit that can stabilize a generated carrier wave.

Means for Solving the Problems In order to achieve the above object, the present invention provides a frequency conversion circuit that includes a voltage controlled oscillator and performs frequency conversion of an input digital modulation signal, and generates a carrier wave for demodulation and The frequency conversion circuit is provided with a carrier recovery circuit that synchronizes with the center frequency of the digital modulation signal by demodulation output and generates a synchronization detection signal indicating whether the carrier wave is synchronized with the digital modulation signal. A demodulation circuit that demodulates the digitally modulated signal that has been converted, and an AFC for controlling the voltage-controlled oscillator so as to frequency stabilize the frequency-converted digitally modulated signal that is input to the demodulation circuit in a circuit that includes: In the circuit, a frequency divider, a counter that counts the output of the frequency divider for a certain period, and the digitizer. Switch for selectively selecting one of the frequency-divided signals and the reproduced carrier wave so that the divided output is guided to a counter, and a switch for inputting the count value of the counter and the synchronization detection signal from the carrier wave reproduction circuit. And a control signal of a counter and a microprocessor for generating an AFC signal for controlling the oscillation frequency of the voltage controlled oscillator, and the AFC signal output from the microprocessor is D / A.
And a D / A converter for converting and supplying the voltage-controlled oscillator to the voltage-controlled oscillator, wherein the microprocessor causes the switch to select a digital modulation signal and counts the digital modulation signal when the synchronous detection signal indicates asynchronous. Compared the count value of the counter and the predetermined reference value, the frequency of the voltage controlled oscillator is swept so as to cancel the difference, and if it is detected that the frequency is in the vicinity of the synchronous frequency based on the count value, the reproduced carrier wave Is selected by the switch to perform low-speed sweep, and when the synchronization detection signal indicates synchronization, the frequency sweep of the voltage controlled oscillator is stopped and then the reproduced carrier wave is counted by the counter, and the count value and the predetermined reference The voltage-controlled oscillator is controlled so as to compare with the value and cancel the difference.

With this configuration, when the carrier wave is not synchronized, the digitally modulated signal selected by the switch is divided, and the divided signal is counted for a certain period of time so that the oscillation frequency of the voltage controlled oscillator can be swept, for example. Then, when the frequency is close to the carrier synchronization frequency, the switch is switched to divide the carrier, and the oscillation frequency of the voltage controlled oscillator is swept slowly until the carrier is synchronized, and when the carrier is synchronized, the carrier is divided. It is possible to control the voltage controlled oscillator so as to cancel the error by counting the signals for a certain period and comparing the count value with the reference value.

Embodiments Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the AFC circuit of this embodiment. Incidentally, in the figure, those having the same functions as those of the conventional example of FIG. 6 are designated by the same reference numerals.

The AFC circuit of the present embodiment is controlled by the microprocessor 1 and the switch 3 which is controlled by the control signal of the microprocessor 1 and selects one of the band-limited digital modulation signal and the carrier wave fc output from the carrier wave reproducing circuit 106.
And a frequency divider 4 that divides the high-frequency signal selected by the switch 3 by m (where m ≧ 2) and a control signal LE5 of the microprocessor 1, and counts the divided high-frequency signal for a certain period, An N-bit counter 7 that outputs the count value to the microprocessor 1 via the signal line 6, and a D / A that outputs the AFC voltage of the VCO 101 controlled by the microprocessor 1.
It is composed of a converter 111. It should be noted that the microprocessor 1 compares and calculates the count value and the reference value on the program, and the voltage controlled oscillator (VCO) 101 is arranged to cancel the error.
Control.

In the present embodiment, when the reproduced carrier wave is asynchronous, the digital modulation signal is selected by the switch, and when it comes close to the synchronous state,
The reproduced carrier wave is selected by the switch for the following reason. First, the carrier recovery circuit 106 is set so that its free-run frequency becomes the carrier frequency. When synchronized, the frequency is synchronized with the digital modulation signal. As a matter of course, it is in the free-run state when asynchronous. Therefore, in the free-run state, the frequency of the reproduced carrier becomes almost the same frequency as the carrier of the digital modulation signal (intermediate frequency), and when the frequency is counted, it almost agrees with the reference value. Because it can happen that they match,
It does not make sense to count the regenerated carriers when they are asynchronous. The difference from the reference value becomes clear by counting the digital modulation signals when they are asynchronous, and the VCO can be swept at high speed up to near the synchronization frequency.

After high-speed sweep up to near the synchronization frequency, switch 3
To switch to low speed sweep. At this time, it is desirable not to count the reproduced carrier wave for the above reason. When the synchronization detection signal indicates synchronization, the sweep is stopped and the number of reproduced carriers is counted. Considering the case where only the reproduced carrier wave is used without using the digital modulation signal, for the above reason,
Since the reproduced carrier wave cannot be counted from the beginning, it takes time to obtain the final synchronization. On the other hand, in the present embodiment, as described above, the high-speed sweep can be performed up to the vicinity of the synchronization frequency, so that the time until synchronization can be shortened.

Next, the AFC operation of the above configuration will be described. First,
When the oscillation frequency of the VCO 101 is swept at high speed when the carrier wave is asynchronous, the switch 3 is set by the microprocessor 1 so that the A side, that is, the band-limited digital modulation signal is selected. The modulated signal is input and divided by m. The divided signal is N
Inputted to the bit counter 7, the microprocessor 1 operates the N-bit counter 7 for a certain period of time via the control signal LE5. As a result, the counter 7 counts the divided digital signal. The counted value is taken into the microprocessor 1 through the signal line 6 and compared / calculated with the reference value set on the program of the microprocessor 1. Then, the microprocessor 1 sends data to the D / A converter 111 to change the AFC voltage so that the oscillation frequency of the VCO 101 is swept in a direction to cancel the error. At this time, the center frequency range of the digital modulation signal input to the demodulation circuit 8 is 140 MHz + /
-5MHz, frequency count resolution 200kHz, frequency divider 4
If divided by 40, the operating time of the N-bit counter 7 is 0.2m
Seconds, and the number of bits becomes 7 to 10 bits. When the frequency of the digitally modulated signal is counted, and it is determined from the count value that the frequency is close to the carrier synchronization frequency, the microprocessor 1 sets the switch 3 to the B side, that is, the reproduction which is the output of the carrier reproduction circuit 106. The carrier wave fc is changed to the low speed sweep of the VCO 101. When the microprocessor 1 detects that the carrier fc is synchronized via the synchronization detection signal 107, it stops the sweep of the VCO 101 and keeps the N-bit counter 7 constant via the control signal LE5 so as to count the divided carrier fc. Operate for a period. The counted value is taken into the microprocessor 1 via the signal line 6, compared with the reference value set on the program, and calculated,
The microprocessor 1 sends data to the D / A converter 111 in a direction of canceling the error, finely adjusts the oscillation frequency of the VCO 101, and stabilizes the frequency of the frequency-converted digital modulation signal input to the demodulation circuit 8. . At this time, the resolution of the frequency count is 20kHz and the synchronous frequency range of the carrier is 140MH.
Assuming that z +/− 1 MHz and the operating time of the N-bit counter 7 are 2 ms, the frequency divider 4 divides the frequency by 40, so that the count value of the N-bit counter is 6950 to 7050. This can be expressed in binary as 1101100100110B ~ 1101110001010B,
The number of bits of the N-bit counter 7 is 8 to 13 bits.
Therefore, the number of bits of the N-bit counter 7 may be 8 bits, which is a common number of bits during high speed sweep.

In this way, the frequency range of the VCO 101, the synchronization frequency range of the carrier wave fc, the resolution of the frequency count during the high speed sweep and the low speed sweep, the frequency division ratio of the frequency divider 4, and the operating time of the N-bit counter 7 are appropriately designed. If so, the number of bits of the N-bit counter 7 can be minimized. Although the switch 3 is switched when the low speed sweep is performed in the above description, the switch 3 may be switched after the carrier wave is synchronized.

According to the above description, the frequency of the digital modulation signal is counted only in the high-speed sweep, and when the carrier wave is synchronized, the frequency of the carrier wave is counted, so that the AFC operation does not occur even when the digital modulation signal is low C / N. The frequency of the digital modulation signal that is normally input to the demodulation circuit is stabilized. Further, it is not affected by the temperature characteristic of the band limiting BPF 104. Further, when the carrier wave is synchronized, the carrier wave is directly frequency-divided, so that the frequency-divided signal does not have jitter, so that the counter can accurately count.

FIG. 2 is a block diagram showing another embodiment of the AFC circuit of the present invention. A frequency divider 8 for dividing the digital modulation signal by m ′ and a frequency divider 9 for dividing the carrier wave fc by m ″ are provided, and each frequency divider 8,
A switch 12 for selecting the output of 9 by the control signal LE11 of the microprocessor 10 is provided between the N-bit counter 7 and the frequency dividers 8 and 9. The AFC operation is the same as that described above. Since the output of the frequency dividers 8 and 9 is a digital signal, the switch 12 can be easily configured by a digital IC. Further, the frequency division ratios of the frequency dividers 8 and 9 may be the same or different. In either case, the N-bit counter with the minimum number of bits can be used if properly designed from various conditions as described above.

FIG. 3 is a block diagram showing another embodiment of the AFC circuit of the present invention. In this embodiment, the digital modulation signal is branched from the input of the frequency conversion circuit 100 and input to the C / N detection circuit 13. The C / N detection circuit 13 measures C / N of the digital modulation signal and outputs a signal proportional to the value of C / N to the microprocessor 14 as a digital value of several bits. During the AFC operation described above, the microprocessor 14 determines the C / N value of the digital modulation signal from the output of the C / N detection circuit 13 to change the set value indicating the vicinity of the carrier synchronization frequency. For example, if the output value of the C / N detection circuit 13 is a value indicating C / N = 3 dB, the set value indicating the vicinity of the synchronization frequency is set to the synchronization frequency +
/ -1MHz and C / N is 6dB, set value is synchronous frequency +
/ -700kHz, C / N 10dB or more, synchronization frequency + /
Set to -400kHz.

In this way, by changing the set value indicating the vicinity of the synchronization frequency from the C / N of the digital modulation signal, it is possible to speed up carrier synchronization when the C / N of the digital modulation signal is good.

FIG. 4 shows another embodiment of the demodulation circuit. This demodulation circuit 15 is a band limiting LP for band limiting the demodulated signal by the band limiting BPF 104 in the demodulation circuit 8 shown in FIG.
It was replaced with F16 and 17, and the characteristics of the demodulation circuit did not change at all. As described above, even if the demodulation circuit 15 that band-limits the signal obtained by demodulating the digital-modulated signal without band-limiting is used, the digital-modulated signal is used during high-speed sweep according to the present invention, but is used during low-speed sweep and carrier synchronization. Since the frequency is counted by directly dividing the carrier wave, there is no problem in AFC operation. In this respect, in the conventional AFC circuit, since the digital modulation signal is exclusively used, if the signal is demodulated without band limiting the digital modulation signal and the band is limited after demodulation, the digital modulation signal input to the frequency divider is The spectrum of is wider than when the band is limited, and not only does the divided signal have more jitter, but the C / N of the digital modulation signal deteriorates as much as the band is not limited, and the error from the carrier increases. Will end up.

FIG. 5 is a block diagram showing another embodiment of the method of taking the count value of the N-bit counter into the microprocessor 18. The number of bits of the N-bit counter 7 is 8 bits in the above description. Therefore, many input / output ports of the microprocessor must be used. In order to save the input / output port of the microprocessor 18, the shift register 19 is provided between the N-bit counter 7 and the microprocessor 18.
After operating the N-bit counter 7 for a certain period,
The microprocessor 17 controls the control signal LE20 so that the count value of the N-bit counter 7 is transferred from the signal line 6 to the shift register 19
To enter.

Next, the microprocessor 18 sends the clock CK21 to the shift register 19 and serially fetches the data of the shift register 19 from the data line 22. This allows the I / O ports of the microprocessor 18 to be saved.

Although the digital modulation signal is treated as a 4-phase quadrature modulation signal in the above description, the AFC circuit of the present invention can be applied to any digital modulation signal as long as it is a demodulation circuit that employs a demodulation method that reproduces a carrier wave. .

EFFECTS OF THE INVENTION As described above, according to the present invention, a band-limited digital modulation signal input to a demodulation circuit is used for frequency counting during high-speed sweep, and is reproduced when a carrier wave reaches a synchronization frequency. Since the frequency of the carrier wave is directly counted, the configuration is simple and the AFC operation is performed normally even when the digital modulation signal has a low C / N, and the frequency of the digital modulation signal input to the demodulation circuit is stabilized and the demodulation characteristics Does not deteriorate. Further, it is not affected by the temperature characteristics of the circuit elements used, and since the carrier wave is directly divided when synchronizing the carrier wave, no jitter remains in the divided signal, and accurate frequency counting can be performed. Furthermore, the number of bits of the counter can be reduced by optimal design.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the AFC circuit of the present invention, and FIG. 3 is a further embodiment of the AFC circuit of the present invention. FIG. 4 is a configuration diagram showing another embodiment of the demodulation circuit, and FIG. 5 is a configuration diagram showing another embodiment for inputting a count value. FIG. 6 is a configuration diagram showing a conventional example, and FIG. 7 is an explanatory diagram thereof. 1, 10, 14, 18 ... Microprocessor, 3, 12 ... Switch, 4, 8, 9 ... Divider, 7 ... Counter, 8, 15 ... Demodulation circuit, 13 ... C / N detection circuit, 16, 17 ... LPF for band limitation, 19 ...
Shift register, 100 ... Frequency conversion circuit, 101 ... VCO, 102
… Mixer, 104… BPF for band limitation, 105… Phase detector, 106
… Carrier recovery circuit.

Claims (1)

[Claims] 1. A frequency conversion circuit having a voltage controlled oscillator for frequency-converting an input digital modulation signal, a carrier for demodulation is generated, and the carrier is synchronized with a center frequency of the digital modulation signal by a demodulation output. And a demodulation circuit that includes a carrier wave regeneration circuit that generates a synchronization detection signal that indicates whether the carrier wave is synchronized with the digital modulation signal, and that demodulates the digital modulation signal that has been frequency-converted by the frequency conversion circuit, In the AFC circuit for controlling the voltage-controlled oscillator so as to frequency-stabilize the frequency-converted digital modulation signal input to the demodulation circuit in the circuit including, a frequency divider, and A counter that counts the output for a certain period, and a divided output of one of the digital modulated signal and the reproduced carrier wave. A switch selectively selected to be guided to a computer, a count value of the counter and the synchronization detection signal from the carrier recovery circuit are input, and a control signal of the switch and a control signal of the counter, and the voltage controlled oscillator. A microprocessor for generating an AFC signal for controlling the oscillation frequency of, and a D / A converter which D / A converts the AFC signal output from the microprocessor and gives it to the voltage controlled oscillator, and When the synchronization detection signal indicates asynchronization, the microprocessor causes the switch to select a digital modulation signal, compares the count value of a counter that counts the digital modulation signal with a predetermined reference value, and cancels the difference. When the frequency of the voltage-controlled oscillator is swept rapidly and it is detected that the frequency is near the synchronous frequency based on the count value, The reproduced carrier wave is selected by the switch to perform low-speed sweeping, and when the synchronization detection signal indicates synchronization, the frequency sweep of the voltage controlled oscillator is stopped and then the reproduced carrier wave is counted by the counter, and the count value and the An AFC circuit, characterized in that the voltage controlled oscillator is controlled so as to cancel the difference by comparing with a predetermined reference value.