JPH0836558A - One-chip microcomputer - Google Patents

Abstract

PURPOSE:To provide a one-chip microcomputer which makes it easy to manufacture a product that uses it and reduces the manufacture cost of the product. CONSTITUTION:A CPU 100a which has become rewrite mode by a program rewrite command sent from a peripheral input/output circuit 110, stores program codes which are sent similarly through a data bus 100h according to a program strored in a ROM 1090d while instructing an address bus 100g of address to be written by an FRAM 100e.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip microcomputer, and more particularly to a one-chip microcomputer suitable for use in consumer-applied microcomputer application equipment.

[0002]

2. Description of the Related Art In recent years, a device equipped with a microcomputer has been developed in various ways. These devices are highly sophisticated, such as incorporating complex calculations such as neuro control and fuzzy control. Along with this, the size of the software of the microcomputer incorporated in the device has increased, resulting in a malfunction resulting from a programming mistake (commonly called "bug"). In addition, the product life of these products is shortened, and the drastic reduction of the development period puts a burden on software designers, further spurring the occurrence of bugs.

In response to such a tendency, a read-only memory (hereinafter referred to as "ROM") containing a program
Abbreviated), the rewritable ROM is increasingly used from the mask ROM, which has the lowest cost but cannot be changed. This trend is especially prevalent in early versions of new products. This is a first conventional example.

In addition to the passive examples such as the above-mentioned countermeasures against bugs, video tape recorders and compact discs
With the development of software in the automatic control field of products such as disc players, a plurality of microcomputers and processors have come to be incorporated in products. As a result, a hierarchical structure is established in which peripheral control processors are controlled by commands from the microcomputer of the system controller that controls the entire system. Along with this, a random access memory (hereinafter referred to as “RA”) for rewriting the control constants of the control processor, which are conventionally stored in the mask ROM as fixed values, by communicating with the system controller.
It is also becoming more common to memorize in "M". This is a second conventional example.

The above-mentioned two conventional examples will be described with reference to the drawings. Figure 10
2 is a block schematic diagram showing a configuration and peripheral circuits of a one-chip microcomputer in a first conventional example. In FIG. 10, 10 is a one-chip microcomputer, 20 is a rewritable programmable ROM (hereinafter,
"PROM") and is a microcomputer 1
The program of is stored. Reference numeral 30 is a peripheral input / output circuit.

The operation of the conventional one-chip microcomputer constructed as above and its peripheral circuits will be described below. The microcomputer 10 includes a central processing unit (hereinafter abbreviated as “CPU”) 1, a RAM 2, an input / output port 3, a control bus 4, an address bus 5, a data bus 6, and an input / output bus 7. There are cases in which various functions are realized in a circuit using such a microcomputer 10, but here, the functions of each unit and their basic operations will be described only.

The CPU 1 includes a control bus 4 and an address bus 5.
The internal RAM 2 and the input / output port 3 and the external PROM 20 are controlled via the data bus 6. The input / output of the peripheral input / output circuit 30 is C via the input / output port 3.
It sends data on the data bus 6 according to instructions from the PU 1 or receives data from the CPU 1 via the data bus 6. The RAM 2 writes data to an address designated by the CPU 1 via the address bus 5 or reads data from the designated address.

The PROM 20 stores codes to be executed by the CPU 1 and data to be referred to, and the control bus 4
In accordance with the instruction, data or code is sent from the address specified by the address bus 5 to the CPU 1 via the data bus 6. As such a PROM 20, a rewritable one is used for the reasons described above.
Besides, Erasable and Electrically
A programmable ROM (hereinafter abbreviated as “EPROM”) or an electrically erasable programmable ROM (hereinafter abbreviated as “EEPROM”) is used.

FIG. 11 is a block diagram showing the peripheral circuit of the conventional one-chip microcomputer in the second conventional example. In FIG. 11, 10 is a one-chip microcomputer, 40 is a first control processor, 50 is a second control processor, 60 is an external data bus, 70 is a sub power supply, 80 is a power switch, and 90 is a main power supply. .

The operation of the peripheral circuit of the conventional one-chip microcomputer configured as described above will be described. The first control processor 40 and the second control processor 50 respectively perform automatic control of peripheral mechanisms (not shown). For example, in the case of a compact disc player, the first control processor 40 is an optical pickup. Disc follow-up control, and the second control processor 50 controls the movement of this optical pickup in the disc radial direction. In this case, one chip
The microcomputer 10 sends the control gain data, which varies depending on the disc variation, to the first control processor 40 and the second control processor 50 via the external data bus 60. This control gain data is stored in the built-in RAM through the input / output port of each control processor.

The power supply for the one-chip microcomputer 10, the first control processor 40, and the second control processor 50 is supplied from the main power supply 90 because the power switch 80 is closed during normal operation. Cage,
There is no problem at all. However, when the power supply is cut off, the stored data in the RAM in each control processor disappears. Therefore, in such a state that the power switch 80 is opened, the auxiliary power supply 70 operates to constantly supply a voltage that does not erase the data in the RAM in each processor. As the sub power source 70, a large capacity capacitor such as a battery or a gold capacitor is often used.

As a third conventional example, although not shown, the rewritable PROM 20 in the first conventional example may be built in the one-chip microcomputer 10. Such a one-chip microcomputer 10, which has a built-in PROM and is writable only once, is called a one-time microcomputer, and is an EPROM or an EEPROM.
It is called a multi-time microcomputer because the built-in one can write multiple times.

[0013]

However, each of the above-mentioned conventional configurations has the following problems.
The first conventional example uses an external PROM, EPROM, EEPROM or the like, and thus has a problem that the substrate area increases. In addition, such a ROM usually has a high cost and requires a special equipment called a "ROM writer". Moreover, since the ROM is manually inserted into the socket during the process, the mass productivity is poor and the equipment cost, man-hours, and materials are low. There is also the problem of increasing manufacturing costs such as costs.

In the second conventional example, when a battery is used, the user is required to periodically replace the battery, which is inconvenient. Further, even if the battery is replaced by a rechargeable battery or a capacitor is used, there is a problem that an increase in substrate area and an increase in material cost due to increase in parts cannot be avoided.

In the third conventional example, the substrate area is the first.
Although smaller than the conventional example, PROM, EPRO
Since M and EEPROM generally require a high voltage for a write operation, there is a problem that it is difficult to use them in a device using a low voltage such as a portable product. Furthermore, the response of these PROMs is generally slow, and the use of such a PROM in the RAM area in the second conventional example is not suitable for a control processor that requires high-speed processing.

Furthermore, in the third conventional example, when the EPROM is used as the multi-time microcomputer, it is necessary to irradiate the ultraviolet rays to erase the EPROM. Therefore, the second conventional example is improved. RAM as a measure
There is a problem that it cannot be used as. E
When an EPROM is used, writing and erasing can be performed electrically, but there are problems that writing and erasing take time and the chip area of the microcomputer becomes large.

The present invention solves the above problems,
It is an object of the present invention to provide a one-chip microcomputer that makes it easier to produce the products used in the first conventional example and the third conventional example and can simplify the manufacturing process of the products. Compared to the second conventional example, it is a one-chip type that improves usability by using it.
The purpose is to provide a microcomputer.

[0018]

In order to achieve the above object, the one-chip microcomputer of the present invention is characterized in that the memory area is a ferroelectric random access memory.

Further, it is provided with a first storage means for storing a program rewritable by an external operation, and a second storage means for rewriting and storing data in accordance with an internal arithmetic processing.

Further, in the one-chip microcomputer provided with the first storage means for storing the non-rewritable program and the second storage means for rewriting and storing the data in accordance with the internal arithmetic processing, The storage means is a ferroelectric random access memory.

[0021]

According to the present invention, the contents of the program can be freely rewritten as required by the above-mentioned constitution, and the stored contents will not be lost even if the power supply is cut off.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block schematic diagram of a one-chip microcomputer in the first embodiment of the present invention and shows a solution to the above-mentioned first conventional example. In the figure, 100 is a one-chip microcomputer, and 110 is a peripheral input / output circuit.

One-chip microcomputer 100
Is a CPU 100a that controls the whole, an input / output port 100c that communicates with the outside, a RAM 100b that is used as a work area of the CPU 100a, and a ferroelectric RAM (hereinafter referred to as "F") that constitutes a program area that stores an application program.
It is composed of a RAM 100e, a mask type ROM 100d in which an initial program to be operated at the time of initialization is stored, an input / output bus 100f, an address bus 100g, a data bus 100h and a control bus 100i.
The feature of this embodiment is that the program area is a partial ROM.
And the rest is FRAM.

A memory cell of such an FRAM is shown in FIG.
It has a configuration like. In the figure, 40 is a capacitor using a ferroelectric substance, 41 is a metal oxide semiconductor transistor for switching the capacitor 40, 42 is a bit line connected to a sense amplifier for reading data, 43 is data for the capacitor 40
It is a word line for storing in. Such a structure is merely known as a dynamic RAM (hereinafter, abbreviated as "DRAM") only by replacing the capacitor 40 with a ferroelectric substance, and detailed operation description will not be given.

The characteristic of such an FRAM is that it can hold 10 times or more electric charges as compared with an ordinary capacitor and can be made non-volatile. Further, the write voltage and the write speed are no different from those of the normal DRAM and have excellent characteristics that they can be handled in the same manner as the normal RAM.

By the way, the program stored in the factory of the one-chip microcomputer 100 is only the initial program stored in the ROM 100d, and the application program in the use form in the final product is the FRAM 100e. It is stored in the set manufacturer, etc.

One-chip microcomputer 100
Sends a predetermined command through the peripheral input / output circuit 110 in the set maker to activate the program in the ROM 100d. The method of sending this command may be either a serial communication method or a parallel communication method. This RO
The operation of the one-chip microcomputer 100 according to the program stored in the M100d is represented by the flowchart shown in FIG.

First, in step 101, the program code sent from the peripheral input / output circuit 110 is stored in a register (not shown) in the CPU 100a via the input / output port 100c. Then, in step 102, a program write (PWR) signal is sent to the control bus to put the FRAM 100e in the write mode, and this program code is transferred to the address of the FRAM 100e designated by the address bus 100g via the data bus 100h. After that, it is determined whether or not an end code indicating the end of data is input to the input / output port 100c. If the end code is not sent, the process is returned to step 101, and otherwise. A series of program writing processing ends.

Incidentally, the end of the data reception is the step 10
Although the end code is discriminated in 3, the end signal may be received from the outside by providing a dedicated signal line.

After these initialization processes are completed,
In the FRAM 100e, the one-chip microcomputer 100 has the same function as the microcomputer 10 of the conventional example shown in FIG. 10 unless the program write processing as described above is performed.

FIG. 4 is a schematic block diagram of a one-chip microcomputer in the second embodiment of the present invention, showing a solution to the above-mentioned first conventional example.
In the figure, CPU 200a, RAM 200b, FR
The AM 200e, the address bus 200g, and the data bus 200h are the CPUs 100a, R in the first embodiment.
AM100b, FRAM100e, address bus 100
g and the data bus 100h. The feature of this embodiment is that the transfer of the program code to the FRAM 100e, which is performed by executing the program on the ROM 100d in the first embodiment, is burdened by providing the rewriting circuit 200d which is a dedicated hardware. is there.

When the peripheral I / O circuit 110 instructs the I / O port 200c to transfer the program code, the rewrite command signal St is sent from the I / O port 200c to the rewrite circuit 200d. As a result, the rewriting circuit 200
d sends the PWR signal on the control bus 200i,
Set the M200e to the write mode and set the address bus 200
The address to write the program code is designated on g, and the program code is transferred to the FRAM 200e via the data bus 200h.

As described above, according to the first and second embodiments, the program of the one-chip microcomputer 100 can be freely rewritten by the peripheral input / output circuit 110 when the set maker desires. EEP
ROM etc. are unnecessary.

FIG. 5 is a block diagram of a one-chip microcomputer according to the third embodiment of the present invention and shows a solution to the above-mentioned second conventional example. In the figure, a CPU 300a, an address bus 300f, a data bus 300g, and a control bus 300.
h is the same as the CPU 1, address bus 6, data bus 5 and control bus 4 shown in FIG. The feature of this embodiment is that the FRAM 300b is provided as a work area of the CPU 300a.

As a result, the data once stored in the FRAM 300b remains stored even when the power is turned off. This enables the application as shown in FIG. That is, as shown in FIG. 6, even when the first control processor 310 and the second control processor 320 also use the FRAM in the work area, even if the power source 90 is cut off by opening the power switch 80, FIG. The control constants and the like are held even if the battery 70 shown is not provided. Further, since it can operate at a low voltage, it can be used in a battery-specific device such as a portable product.

As described above, according to this embodiment, the battery is essentially unnecessary and the usability for the user is improved.

In the above embodiments, the memory cell of the FRAM is a DRAM type, but the capacitor may be a ferroelectric as the memory cell structure of the static RAM. Further, the case where the work area is replaced with the FRAM and the case where the program area is replaced with the FRAM have been made independent, but all of these areas may be made the FRAM.

FIG. 7 to FIG. 9 show such a case.
become that way. That is, in FIG. 7, RA in FIG.
M100b and ROM100d are respectively FRAM100
j and 100k, the RAM 200b in FIG. 4 is replaced with the FRAM 200j in FIG. 8, and the ROM 300b in FIG. 5 is replaced with the FRAM 200j in FIG.
The case where the RAM 300i is replaced is shown. In any of these FIGS. 7 to 9, the same functions as in the cases of FIGS. 1, 4 and 5, respectively.

[0039]

According to the one-chip microcomputer of the present invention as in the above-mentioned embodiments, the FRs in claims 1 to 5 are:
Since the program area constituted by AM can be freely rewritten by communication from the outside, in the first conventional example, the product is a PROM, EPROM or EE.
Since it is not necessary to attach a PROM or the like externally and the substrate area is small, the product can be easily downsized. In addition, there is no need for a dedicated ROM writer, and there is no need to manually insert the ROM element into the socket during the process, improving mass productivity,
Further, manufacturing costs such as equipment costs, man-hours, and material costs can be reduced.

Further, since the low voltage operation is possible and the writing / erasing time is improved, the application to the low voltage operating product, which is a problem of the conventional one-time microcomputer, is not limited. Also, by communicating for program rewriting, even if there is a bug in the program, it is possible to rewrite the program on the product, so the product or the board on which the microcomputer is mounted is not made a defective product. Moreover, since the product with the bug fixed can be manufactured in a short time, the development period of the product can be shortened and the quality of the product can be improved.

According to the sixth aspect of the invention, since the work area is composed of the FRAM, it is not necessary to use the battery for holding the RAM in the second conventional example, so that the user does not have to perform the periodical battery replacement. It will be easy to use without hanging up. In addition, since it is possible to suppress an increase in substrate area due to the battery and an increase in material cost due to an increase in parts, cost reduction and downsizing are facilitated.

[Brief description of drawings]

FIG. 1 is a one-chip chip according to a first embodiment of the present invention.
1 is a block schematic diagram of a microcomputer.

FIG. 2 is a configuration diagram of an FRAM in the same embodiment.

FIG. 3 is a flowchart showing an initial operation of the one-chip microcomputer in the embodiment.

FIG. 4 is a one-chip chip according to the second embodiment of the present invention.
1 is a block schematic diagram of a microcomputer.

FIG. 5 is a one-chip chip according to the third embodiment of the present invention.
1 is a block schematic diagram of a microcomputer.

FIG. 6 is a circuit configuration diagram when a plurality of one-chip microcomputers are used in the embodiment.

FIG. 7 is a one-chip chip according to the first embodiment of the present invention.
FRA for RAM and ROM for microcomputers
It is a block schematic diagram when changing to M.

FIG. 8 is a one-chip chip according to the second embodiment of the present invention.
It is a block schematic diagram when changing RAM to FRAM about a microcomputer.

FIG. 9 is a one-chip chip according to the third embodiment of the present invention.
It is a block schematic diagram when changing ROM to FRAM about a microcomputer.

FIG. 10 is a block schematic diagram of a one-chip microcomputer in the first conventional example of the present invention.

FIG. 11 is a block schematic diagram of a one-chip microcomputer in a second conventional example of the present invention.

[Explanation of symbols]

60 external data bus 80 power switch 90 main power supply 100, 200, 300 one-chip microcomputer 110 peripheral input / output circuit 310, 320 control processor

Claims (8)

[Claims] 1. A one-chip microcomputer, characterized in that the memory area is a ferroelectric random access memory. 2. A one-chip micro, comprising a first storage means for storing a program rewritable by an external operation, and a second storage means for rewriting and storing data in accordance with internal arithmetic processing. Computer. 3. The first storage means is a ferroelectric random access memory.
The one-chip microcomputer described in. 4. The first storage means comprises a receiving means for receiving a communication command from the outside, a non-rewritable read-only memory in which a program to be started according to the output of the receiving means is stored, and A storage area constituted by a dielectric random access memory, and the output of the receiving means is transferred to the storage area according to a program stored in the read-only memory. The one-chip microcomputer described in 2. 5. The first storage means includes first receiving means for receiving a communication permission command from the outside, second receiving means for receiving communication data from the outside, and ferroelectric random access memory. The one-chip according to claim 2, further comprising: a storage area configured by a memory; and a transfer means for transferring an output of the second reception means to the storage area according to an output of the first reception means. -Microcomputer. 6. The second storage means is a ferroelectric random access memory.
The one-chip microcomputer described in. 7. A third memory for storing a non-rewritable program.
In the one-chip microcomputer, the fourth storage means includes a ferroelectric random access memory and a fourth storage means for rewriting and storing data according to internal arithmetic processing. A one-chip microcomputer characterized by: 8. A ferroelectric random access memory is provided for both the area for storing a program and the area for storing data.
A one-chip microcomputer characterized by being a memory.